WO2002047145A1 - Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing - Google Patents

Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing Download PDF

Info

Publication number
WO2002047145A1
WO2002047145A1 PCT/US2001/045829 US0145829W WO0247145A1 WO 2002047145 A1 WO2002047145 A1 WO 2002047145A1 US 0145829 W US0145829 W US 0145829W WO 0247145 A1 WO0247145 A1 WO 0247145A1
Authority
WO
WIPO (PCT)
Prior art keywords
nickel
high resistance
nickel silicide
processing process
semiconductor processing
Prior art date
Application number
PCT/US2001/045829
Other languages
French (fr)
Inventor
Eric N. Paton
Ercan Adem
Jacques J. Bertrand
Paul R. Besser
Matthew S. Buynoski
John Clayton Foster
Paul L. King
George Jonathan Kluth
Minh Van Ngo
Christy Mei-Chu Woo
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/729,699 external-priority patent/US6605513B2/en
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to JP2002548768A priority Critical patent/JP2004521486A/en
Priority to EP01990802A priority patent/EP1342260A1/en
Priority to AU2002230565A priority patent/AU2002230565A1/en
Priority to GB0315661A priority patent/GB2390224B/en
Publication of WO2002047145A1 publication Critical patent/WO2002047145A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance nickel silicide region (56, 58). Unreacted nickel (54) is removed. A dielectric layer (60) is then deposited over the high resistance nickel silicide regions (56, 58). In a second temperature treatment, the at least one high resistance nickel silicide regions (56, 58) and dielectric (60) are reacted at a prescribed temperature to form at least one low resistance silicideregion (64, 66) and process the dielectri c layer (60). Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel (54) between silicide region (56, 58) is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions (56, 58) and the dielectric layer (60) are conveniently combined into a single temperature treatment. In other embodiments, the second temperature treatment is performed prior to, and separate from, the depositing and processing of the dielectric layer (60).

Claims

CLAIMSWHAT IS CLAIMED IS
1. A semiconductor processing process, comprising the steps of: depositing nickel metal or nickel alloy (52) on at least one silicon layer (46); reacting at least a portion of the nickel metal or nickel alloy (52) with the silicon layer (46) at a first temperature for a first period of time to form at least one high resistance nickel silicide region (56, 58); removing unreacted nickel metal or nickel alloy (54); and reacting the high resistance nickel silicide region (56, 58) at a second temperature for a second period of time to form at least one low resistance nickel silicide region (64, 66).
2. The semiconductor processing process of claim 1, further comprising depositing a dielectric layer (60) over at least one high resistance nickel silicide region (56 58) prior to reacting the high resistance nickel silicide region (56, 58).
3. The semiconductor processing process of claim 1, wherein the first temperature is in the range of about 250°C to about 350°C.
4. The semiconductor processing process of claim 1, wherein the second temperature is in the range of about 400°C to about 600°C.
5. The semiconductor processing process of claim 1, wherein the high resistance nickel silicide region (56, 58) is at least one of Ni3Si and Ni2Si and the low resistance nickel silicide region (64, 66) is NiSi.
6. The semiconductor processing process of claim 1, wherein the first period of time is about 15 to about 90 seconds and the second period of time is about 15 to about 90 seconds.
7. The semiconductor processing process of claim 1, wherein the first period of time is about 30 to about 60 seconds and the second period of time is about 30 to about 60 seconds.
8. The semiconductor processing process of claim 1, wherein the first and second reacting steps form a two-step rapid thermal anneal process.
9. The semiconductor processing process of claim 2, wherein the first reacting step and the second reacting step from a one-step rapid thermal anneal with backend processing process.
PCT/US2001/045829 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing WO2002047145A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2002548768A JP2004521486A (en) 2000-12-06 2001-12-03 Method for forming nickel silicide using one-step rapid thermal annealing process and back-end process
EP01990802A EP1342260A1 (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
AU2002230565A AU2002230565A1 (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
GB0315661A GB2390224B (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US72969800A 2000-12-06 2000-12-06
US09/729,699 2000-12-06
US09/729,699 US6605513B2 (en) 2000-12-06 2000-12-06 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
US09/729,698 2000-12-06

Publications (1)

Publication Number Publication Date
WO2002047145A1 true WO2002047145A1 (en) 2002-06-13

Family

ID=27111928

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/045829 WO2002047145A1 (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Country Status (7)

Country Link
EP (1) EP1342260A1 (en)
JP (1) JP2004521486A (en)
CN (1) CN1633703A (en)
AU (1) AU2002230565A1 (en)
GB (1) GB2390224B (en)
TW (1) TW531792B (en)
WO (1) WO2002047145A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7232756B2 (en) 2003-04-16 2007-06-19 Samsung Electronics Co., Ltd. Nickel salicide process with reduced dopant deactivation
CN100336186C (en) * 2003-06-27 2007-09-05 三星电子株式会社 Method for forming nickel silicide and semiconductor device
WO2007131907A2 (en) * 2006-05-16 2007-11-22 F. Hoffmann-La Roche Ag 1h-indol-5-yl-piperazin-1-yl-methanone derivatives
US7385294B2 (en) 2005-09-08 2008-06-10 United Microelectronics Corp. Semiconductor device having nickel silicide and method of fabricating nickel silicide
EP1946361A2 (en) * 2005-10-03 2008-07-23 International Business Machines Corporation Method and apparatus for forming nickel silicide with low defect density in fet devices
US7622374B2 (en) 2005-12-29 2009-11-24 Infineon Technologies Ag Method of fabricating an integrated circuit
US8541297B2 (en) 2010-03-29 2013-09-24 Renesas Electronics Corporation Manufacturing method of semiconductor device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006001271A1 (en) * 2004-06-23 2006-01-05 Nec Corporation Semiconductor device and manufacturing method thereof
CN1937181B (en) * 2005-09-19 2010-11-17 联华电子股份有限公司 Semiconductor element with nickel silicide and method for preparing nickel silicide
JP2007242894A (en) * 2006-03-08 2007-09-20 Toshiba Corp Semiconductor device and its manufacturing method
CN100442460C (en) * 2006-04-03 2008-12-10 中芯国际集成电路制造(上海)有限公司 Method for forming nickel silicide by plasma annealing
CN102468150B (en) * 2010-11-19 2013-12-04 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor device
CN103165485B (en) * 2011-12-08 2015-11-25 中芯国际集成电路制造(上海)有限公司 The monitoring method of Millisecond annealing technology stability

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0831521A2 (en) * 1996-09-18 1998-03-25 Texas Instruments Incorporated Method for forming a silicide region
EP0836223A2 (en) * 1996-10-08 1998-04-15 Texas Instruments Inc. Method of forming a silicide layer
EP0936664A2 (en) * 1998-02-13 1999-08-18 Sharp Kabushiki Kaisha Partial silicidation method to form shallow source/drain junctions
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0831521A2 (en) * 1996-09-18 1998-03-25 Texas Instruments Incorporated Method for forming a silicide region
EP0836223A2 (en) * 1996-10-08 1998-04-15 Texas Instruments Inc. Method of forming a silicide layer
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device
EP0936664A2 (en) * 1998-02-13 1999-08-18 Sharp Kabushiki Kaisha Partial silicidation method to form shallow source/drain junctions

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7232756B2 (en) 2003-04-16 2007-06-19 Samsung Electronics Co., Ltd. Nickel salicide process with reduced dopant deactivation
DE102004019199B4 (en) * 2003-04-16 2012-02-16 Samsung Electronics Co., Ltd. Method for producing a semiconductor component
CN100336186C (en) * 2003-06-27 2007-09-05 三星电子株式会社 Method for forming nickel silicide and semiconductor device
US7385294B2 (en) 2005-09-08 2008-06-10 United Microelectronics Corp. Semiconductor device having nickel silicide and method of fabricating nickel silicide
US7572722B2 (en) 2005-09-08 2009-08-11 United Microelectronics Corp. Method of fabricating nickel silicide
EP1946361A2 (en) * 2005-10-03 2008-07-23 International Business Machines Corporation Method and apparatus for forming nickel silicide with low defect density in fet devices
EP1946361A4 (en) * 2005-10-03 2011-03-09 Ibm Method and apparatus for forming nickel silicide with low defect density in fet devices
US7622374B2 (en) 2005-12-29 2009-11-24 Infineon Technologies Ag Method of fabricating an integrated circuit
WO2007131907A2 (en) * 2006-05-16 2007-11-22 F. Hoffmann-La Roche Ag 1h-indol-5-yl-piperazin-1-yl-methanone derivatives
WO2007131907A3 (en) * 2006-05-16 2008-01-24 Hoffmann La Roche 1h-indol-5-yl-piperazin-1-yl-methanone derivatives
US7432255B2 (en) 2006-05-16 2008-10-07 Hoffmann-La Roche Inc. 1H-indol-5-yl-piperazin-1-yl-methanone derivatives
US8541297B2 (en) 2010-03-29 2013-09-24 Renesas Electronics Corporation Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
GB0315661D0 (en) 2003-08-13
TW531792B (en) 2003-05-11
EP1342260A1 (en) 2003-09-10
GB2390224B (en) 2004-12-08
AU2002230565A1 (en) 2002-06-18
JP2004521486A (en) 2004-07-15
CN1633703A (en) 2005-06-29
GB2390224A (en) 2003-12-31

Similar Documents

Publication Publication Date Title
JP2586345B2 (en) Semiconductor device comprising cobalt silicide film and method of manufacturing the device
EP0501561B1 (en) Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed
WO2002047145A1 (en) Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
TWI261309B (en) Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same
EP1522093A1 (en) Method using silicide contacts for semiconductor processing
US6605513B2 (en) Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
EP0725431A3 (en) Method for forming ordered titanium nitride and titanium silicide upon a semiconductor wafer using a three step anneal process
US6589836B1 (en) One step dual salicide formation for ultra shallow junction applications
JP3469595B2 (en) Method of forming silicide plug in semiconductor device
KR100350600B1 (en) Method of manufacturing a semiconductor device
JPH01251611A (en) Manufacture of semiconductor device
WO1999062109A1 (en) Method of forming cobalt disilicide contacts by chemical vapor deposition
US6303504B1 (en) Method of improving process robustness of nickel salicide in semiconductors
US6797598B2 (en) Method for forming an epitaxial cobalt silicide layer on MOS devices
TWI233167B (en) Silicide formation using a metal-organic chemical vapor deposited capping layer
US7285491B2 (en) Salicide process
US6764912B1 (en) Passivation of nitride spacer
JP3258934B2 (en) Improved method for producing self-aligned silicides
TWI297178B (en) Salicide process
JP2003168652A5 (en)
JP3767583B2 (en) Manufacturing method of semiconductor device
JPH01105532A (en) Manufacture of semiconductor device
KR100273272B1 (en) Fabricating method of silicide
US20020132456A1 (en) One-step process for forming titanium silicide layer on polysilicon
KR100447784B1 (en) Method for manufacturing semiconductor device to reduce contact resistance using two-step annealing

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

ENP Entry into the national phase

Ref document number: 0315661

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20011203

Format of ref document f/p: F

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2002548768

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 018201865

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2001990802

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2001990802

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642