WO2002047145A1 - Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing - Google Patents

Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing Download PDF

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Publication number
WO2002047145A1
WO2002047145A1 PCT/US2001/045829 US0145829W WO0247145A1 WO 2002047145 A1 WO2002047145 A1 WO 2002047145A1 US 0145829 W US0145829 W US 0145829W WO 0247145 A1 WO0247145 A1 WO 0247145A1
Authority
WO
WIPO (PCT)
Prior art keywords
nickel
high resistance
nickel silicide
processing process
semiconductor processing
Prior art date
Application number
PCT/US2001/045829
Other languages
French (fr)
Inventor
Eric N. Paton
Ercan Adem
Jacques J. Bertrand
Paul R. Besser
Matthew S. Buynoski
John Clayton Foster
Paul L. King
George Jonathan Kluth
Minh Van Ngo
Christy Mei-Chu Woo
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US72969800A priority Critical
Priority to US09/729,698 priority
Priority to US09/729,699 priority patent/US6605513B2/en
Priority to US09/729,699 priority
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO2002047145A1 publication Critical patent/WO2002047145A1/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metallic silicode formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Abstract

A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance nickel silicide region (56, 58). Unreacted nickel (54) is removed. A dielectric layer (60) is then deposited over the high resistance nickel silicide regions (56, 58). In a second temperature treatment, the at least one high resistance nickel silicide regions (56, 58) and dielectric (60) are reacted at a prescribed temperature to form at least one low resistance silicideregion (64, 66) and process the dielectri c layer (60). Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel (54) between silicide region (56, 58) is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions (56, 58) and the dielectric layer (60) are conveniently combined into a single temperature treatment. In other embodiments, the second temperature treatment is performed prior to, and separate from, the depositing and processing of the dielectric layer (60).

Claims

CLAIMSWHAT IS CLAIMED IS
1. A semiconductor processing process, comprising the steps of: depositing nickel metal or nickel alloy (52) on at least one silicon layer (46); reacting at least a portion of the nickel metal or nickel alloy (52) with the silicon layer (46) at a first temperature for a first period of time to form at least one high resistance nickel silicide region (56, 58); removing unreacted nickel metal or nickel alloy (54); and reacting the high resistance nickel silicide region (56, 58) at a second temperature for a second period of time to form at least one low resistance nickel silicide region (64, 66).
2. The semiconductor processing process of claim 1, further comprising depositing a dielectric layer (60) over at least one high resistance nickel silicide region (56 58) prior to reacting the high resistance nickel silicide region (56, 58).
3. The semiconductor processing process of claim 1, wherein the first temperature is in the range of about 250°C to about 350°C.
4. The semiconductor processing process of claim 1, wherein the second temperature is in the range of about 400°C to about 600°C.
5. The semiconductor processing process of claim 1, wherein the high resistance nickel silicide region (56, 58) is at least one of Ni3Si and Ni2Si and the low resistance nickel silicide region (64, 66) is NiSi.
6. The semiconductor processing process of claim 1, wherein the first period of time is about 15 to about 90 seconds and the second period of time is about 15 to about 90 seconds.
7. The semiconductor processing process of claim 1, wherein the first period of time is about 30 to about 60 seconds and the second period of time is about 30 to about 60 seconds.
8. The semiconductor processing process of claim 1, wherein the first and second reacting steps form a two-step rapid thermal anneal process.
9. The semiconductor processing process of claim 2, wherein the first reacting step and the second reacting step from a one-step rapid thermal anneal with backend processing process.
PCT/US2001/045829 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing WO2002047145A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US72969800A true 2000-12-06 2000-12-06
US09/729,698 2000-12-06
US09/729,699 US6605513B2 (en) 2000-12-06 2000-12-06 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
US09/729,699 2000-12-06

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0315661A GB2390224B (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
EP20010990802 EP1342260A1 (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
JP2002548768A JP2004521486A (en) 2000-12-06 2001-12-03 Method for forming nickel silicide using one-step rapid thermal annealing process and back-end process
AU3056502A AU3056502A (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Publications (1)

Publication Number Publication Date
WO2002047145A1 true WO2002047145A1 (en) 2002-06-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/045829 WO2002047145A1 (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Country Status (7)

Country Link
EP (1) EP1342260A1 (en)
JP (1) JP2004521486A (en)
CN (1) CN1633703A (en)
AU (1) AU3056502A (en)
GB (1) GB2390224B (en)
TW (1) TW531792B (en)
WO (1) WO2002047145A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7232756B2 (en) 2003-04-16 2007-06-19 Samsung Electronics Co., Ltd. Nickel salicide process with reduced dopant deactivation
CN100336186C (en) * 2003-06-27 2007-09-05 三星电子株式会社 Method for forming nickel silicide and semiconductor device
WO2007131907A2 (en) * 2006-05-16 2007-11-22 F. Hoffmann-La Roche Ag 1h-indol-5-yl-piperazin-1-yl-methanone derivatives
US7385294B2 (en) 2005-09-08 2008-06-10 United Microelectronics Corp. Semiconductor device having nickel silicide and method of fabricating nickel silicide
EP1946361A2 (en) * 2005-10-03 2008-07-23 International Business Machines Corporation Method and apparatus for forming nickel silicide with low defect density in fet devices
US7622374B2 (en) 2005-12-29 2009-11-24 Infineon Technologies Ag Method of fabricating an integrated circuit
US8541297B2 (en) 2010-03-29 2013-09-24 Renesas Electronics Corporation Manufacturing method of semiconductor device

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7592674B2 (en) * 2004-06-23 2009-09-22 Nec Corporation Semiconductor device with silicide-containing gate electrode and method of fabricating the same
CN1937181B (en) 2005-09-19 2010-11-17 联华电子股份有限公司 Semiconductor element with nickel silicide and method for preparing nickel silicide
JP2007214269A (en) 2006-02-08 2007-08-23 Sony Corp Metal silicide forming method and method for manufacturing of semiconductor device
JP2007242894A (en) 2006-03-08 2007-09-20 Toshiba Corp Semiconductor device and its manufacturing method
CN100442460C (en) 2006-04-03 2008-12-10 中芯国际集成电路制造(上海)有限公司 Method for forming nickel silicide by plasma annealing
CN100576471C (en) 2006-12-05 2009-12-30 中芯国际集成电路制造(上海)有限公司 Method of manufacturing metal oxide semiconductor device
CN102468150B (en) * 2010-11-19 2013-12-04 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor device
CN103165485B (en) * 2011-12-08 2015-11-25 中芯国际集成电路制造(上海)有限公司 The monitoring method of Millisecond annealing technology stability

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0831521A2 (en) * 1996-09-18 1998-03-25 Texas Instruments Incorporated Method for forming a silicide region
EP0836223A2 (en) * 1996-10-08 1998-04-15 Texas Instruments Inc. Method of forming a silicide layer
EP0936664A2 (en) * 1998-02-13 1999-08-18 Sharp Kabushiki Kaisha Partial silicidation method to form shallow source/drain junctions
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0831521A2 (en) * 1996-09-18 1998-03-25 Texas Instruments Incorporated Method for forming a silicide region
EP0836223A2 (en) * 1996-10-08 1998-04-15 Texas Instruments Inc. Method of forming a silicide layer
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device
EP0936664A2 (en) * 1998-02-13 1999-08-18 Sharp Kabushiki Kaisha Partial silicidation method to form shallow source/drain junctions

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7232756B2 (en) 2003-04-16 2007-06-19 Samsung Electronics Co., Ltd. Nickel salicide process with reduced dopant deactivation
DE102004019199B4 (en) * 2003-04-16 2012-02-16 Samsung Electronics Co., Ltd. Method for producing a semiconductor component
CN100336186C (en) * 2003-06-27 2007-09-05 三星电子株式会社 Method for forming nickel silicide and semiconductor device
US7572722B2 (en) 2005-09-08 2009-08-11 United Microelectronics Corp. Method of fabricating nickel silicide
US7385294B2 (en) 2005-09-08 2008-06-10 United Microelectronics Corp. Semiconductor device having nickel silicide and method of fabricating nickel silicide
EP1946361A4 (en) * 2005-10-03 2011-03-09 Ibm Method and apparatus for forming nickel silicide with low defect density in fet devices
EP1946361A2 (en) * 2005-10-03 2008-07-23 International Business Machines Corporation Method and apparatus for forming nickel silicide with low defect density in fet devices
US7622374B2 (en) 2005-12-29 2009-11-24 Infineon Technologies Ag Method of fabricating an integrated circuit
US7432255B2 (en) 2006-05-16 2008-10-07 Hoffmann-La Roche Inc. 1H-indol-5-yl-piperazin-1-yl-methanone derivatives
WO2007131907A2 (en) * 2006-05-16 2007-11-22 F. Hoffmann-La Roche Ag 1h-indol-5-yl-piperazin-1-yl-methanone derivatives
WO2007131907A3 (en) * 2006-05-16 2008-01-24 Hoffmann La Roche 1h-indol-5-yl-piperazin-1-yl-methanone derivatives
US8541297B2 (en) 2010-03-29 2013-09-24 Renesas Electronics Corporation Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
AU3056502A (en) 2002-06-18
GB0315661D0 (en) 2003-08-13
TW531792B (en) 2003-05-11
EP1342260A1 (en) 2003-09-10
CN1633703A (en) 2005-06-29
GB2390224B (en) 2004-12-08
GB2390224A (en) 2003-12-31
JP2004521486A (en) 2004-07-15

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