1297178 % • 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種半導體林製程，尤指—種製作自對準金屬 石夕化物(salicide)的方法。 【先前技術】 在半導體積體電路的製程中，金屬氧化半導體 • (metal-oxide-semiconductor，MOS)電晶體是一種極重要的電子元 件’而Ik著半導體元件的尺寸越來越小，M〇s電晶體的製程步驟 也有許多的改進，以製造出體積小而高品質的M0S電晶體。· f知的MQS電㈣製程是在半導縣底上形成_結構之 後’再於閘極結構相對兩侧的基底中形成輕摻雜汲極結構(1咖^ dopeddram，LDD)。接著於閘極結構側邊形成侧壁子細_)，並 • β此閘極結構及側壁子做為遮罩，進行離子植入步驟，以於半導 體基底中形成源極/没極區。而為了要將電晶體的閘極、源極與汲 極適當電連接於電路中，因此需要形成接觸插塞(c〇ntactplug)來進 行導通。通常接觸插塞的材質為鎢(w)、銅等金屬導體，然其與閘 • 極結構、源極/沒極區等多晶或單晶矽等材質之間的直接導通並不 _ 理想，因此為了改善金屬插塞與閘極結構、源極/汲極區之間的歐 米接觸(Ohmicontact)，通常會在閘極結構、源極/汲極區的表面再 形成一金屬矽化物(silicide)。 6 1297178 目箾大夕疋利用自對準金屬砍化物(self_aligned迎如如，sa】icide) 製程來形成金屬矽化物；亦即在形成源極/汲極區之後，再形成一 銘(Co)、鈦(Ti)、鎳(Ni)等金屬層覆蓋於源極/汲極區與閘極結構上 方，然後進行-快速升溫退雄TA)製程使金屬層與酿結構、源 極/汲極區中的矽反應，形成金屬矽化物來降低源極以及極區的片電 阻(sheet resistance) 〇 然而，以這個方式形成金屬矽化物也會產生一些問題，就是在 形成金屬石夕化物時，金屬層中的金屬原子會擴散進石夕基底中並消 耗掉源極/汲極區中的矽來完成，不但原本源極級極區中的晶格結 構會遭到破壞’甚至會導致源極/汲極區和石夕基底之間力pN接合 與石夕化金屬層間之距離過近會與源極級極區中的石夕發生反應，並 破壞部分藤/紐_部分結構，尤其在超·面(_越〇w junction，·)的設計中，甚至會造成金屬石夕化物與基底直接接觸， 進而導致元件失效的狀況。 請參照第1圖，第1圖與第2圖為習知製作自對準金屬石夕化物 的製程不意®。如第1圖所示，首先在基底⑹上形成由閘極介電 層62與閘極64所構成的閘極結構66之後，接著進行一離子植入 乂驟以於基底60中形成輕摻雜没極結構？〇。隨後於閘極結構 66的侧壁形成襯墊層67及側壁子⑽，並進行另一離子植入步驟， 以於側壁子68 賊底6()巾形成雜級純域72。然後進行 -濕式清洗製程’以去除閘極結構66與源極/汲極區域π表面之 1297178 不純顆粒或原生氧化物，並進行一除水氣(degas)步驟來移除因濕 式清洗製程所形成之多餘水氣。隨後，於基底60表面濺鍍一金屬 層74，例如一鎳金屬層，並覆蓋在閘極64、侧壁子邰、以及基底 60表面。如第2圖所示，接著進行一快速升溫退火製程(rapid thermal anneal, RTA)，使金屬層74與閘極64以及源極/汲極區域 72接觸的部分反應成矽化金屬層76。最後再利用一選擇性濕式蝕 刻’例如以服4〇腕2〇2甩2〇或H2S〇4/H2〇2的混合溶液來去除未 I 反應成金屬石夕化物之金屬層74。 如上所述，為了避免電晶體的設計因元件積極度的增加而縮小 之後所竹生的MOS短通道效應(也如—ηηΜ effects)，並改善積體 電路的内連線電阻值(interconnect resistance)，因此必須縮小電晶體 之源極與没極的接合深度(junction depth)來製作含有金屬秒化物 之電晶體。然而在源極與没極的接合深度縮小的同時，若薄化源 極與汲極上的金屬矽化物的厚度，則可能會造成過高的内連線電 阻值(interconnect resistance)與接觸電阻(c〇ntact resistance);但是若 維持源極與汲極上的金屬石夕化物在一定厚度，則可能會導致源極/ 汲極區72和矽基底60之間的PN接合與矽化金屬層76間之距離 過近而使M0S電晶體發生誘發接合漏電。而且 在進行石夕化金屬反應如之濕式清洗製程所使用的溶劑亦會對閘極 與侧壁子之間的襯墊層造成侵钱，使後續進行魏金屬反應時， 石夕化金屬更容易接近通道區域，而產生所謂「⑦傾導通(nickd silicide piping)效應」。 1297178 除此之外’部份之金屬石夕化物的熱穩定性(thermal stability)不 佳’即使還未進行快速升溫退火處理之前，一開始在金屬濺鍍製 程中形成的初鍍膜(as-deposition)也會由於產生電漿之PVD反應室 之製程溫度較高，或因為金屬沈積前之除水氣步驟的高溫度而形 成呈多晶狀(polyCryStalline)結構的金屬矽化物，亦即當溫度太高或 尚/皿處理時間稍長時，j屬砂化物就金兹^凰塊4fefaggi〇merati〇n) 的現象’變成一塊塊不相聯的團狀物，導致片電阻(sheetresistance) 的上升’甚至在後續之高溫製程中發生轉換，消耗過多的矽，而 在淺接面上造成尖突(spiking)的現象或形成高電阻率(resistivity)的 結構’例如低電阻率之石夕化鎳型態(約小於⑼…-⑽)會被轉 變成高電阻率的二石夕化鎳(NiSi2)型態(約50// Ω-cm)。 【發明内容】 因此本發明之主要目的在於提供一種改良之自對準金屬石夕化 物製程，以解決上述習知技藝的問題。 根據本發明之申請專利範圍，係揭露一種自對準金屬矽化物 (salicide)製程。首先提供一基底，且該基底表面包含有至少一石夕導 電層’然後對該基底進行一除水氣(degas)步驟，並對該基底進行 冷部步驟；接著沈積一金屬層於該基底表面，且該金屬層與該 矽導電層表面相接觸，然後進行一熱製程，以使接觸該金屬層之 該石夕導電層表面形成—例b金屬層，最後去除未反應之該金屬層。 1297178 根據本發明之申請專利範圍，另揭露一種自對準金屬矽化物製 程。首先二^，且該基底表面包含有至少一矽導電層，然 後進行步驟，以於該基底表面髮成二_層，且 該金屬層與該梦導電層表面相接觸；接著進*一第二積步 驟，以於該金屬層表面形成-遮蓋層，然後升溫退火 製程(RTA) ’以使接觸該金屬層之該矽導電層表面形成一矽化金屬 層。最後去除未反應之該金屬層以及該遮蓋層。 本發明主要k供-種新製程以減低熱預算，並於形成自對準金 屬石夕化物於基底時，增進該自對準金屬石夕化物製程在熱預算上的 穩疋性’除了可減低習知金屬石夕化物因溫度太高或高溫處理時間 稍長而發生團快化現象而導致片電阻上升，並同時能改進後續因 回溫製程巾發生轉換，雜過麵㈣錢接社造成尖突現象 或低電阻率之石夕化鎳(NiSi)型態、會被轉變成高電阻率的二石夕化鎳 (NiSi2)型態的問題。 【實施方式】 請參照第3圖至第5圖，第3圖至第5圖為本發明之自對準金 屬石夕化物製程顧在M〇S電晶體的製程示細。如第3圖所示， 首先提供-基底1GG，例如mi(wafei·)或魏絕.緣(s〇I)基底， 且基底100表面具有至少一由單晶梦、多晶梦或蟲晶所組成之石夕 導電層(圖未示）。其中，該石夕導電層可針對不同產品需求與製程設 汁而包3有卩施、源極级極區域、字元線或電阻等結構，在本發 1297178 明第3圖至第5圖之最佳實施例中係以MOS電晶體的閘極結構 102與源極/汲極區域112進行說明。如第3圖所示，閘極結構1〇2 包含有閘極介電層102以及閘極104,且閘極介電層1〇2係由二氧 化矽等介電材料所構成，而閘極104則係由摻雜多晶矽(doped polysilicon)等導電材料所構成。 隨後進行一輕摻雜離子佈植製程，利用閘極104做為一遮罩並 將一輕捧雜質(圖未不)植入閘極104相對兩侧的基底1〇〇内，以於 基底100内形成源極/没極延伸區域110。接著於閘極結構1〇6周 圍侧壁形成一襯墊層107，例如一矽氧層，然後在襯墊層1〇7上再 形成一由氮矽化合物組成之侧壁子108。接著進行一重摻雜離子佈 植製私，利用閘極104與侧壁子108做為一遮罩並將^—重摻雜質(圖 未示)植入基底100内，以於基底100中形成一摻雜濃度較高的源 極/沒極區域112。緊接著進行一高溫回火(thermal annealing)製程， 利用1000至1050°C的高溫來活化基底100内的摻雜質，並同時修 補在各離子佈植製程中受損之基底100表面的晶格結構。 接著進行一濕式清洗步驟(wet cleaning step)，用以清除殘留於 閘極104頂部與源極/汲極區域112表面之原生氧化物(native 〇xide) 與其他不純物質。然後在將基底100置入一物理氣相沉積(PYJ)) 反應室之後，隨即利用100°c至400°c的溫度對基底100進行一除 水氣(degas)步驟’用以去除濕式清洗步驟所殘餘於基底1⑻表面 多餘之水氣。接著再進行一冷卻步驟，例如利用一惰性氣體或晶 11 1297178 圓冷聰雖afer cooling chiller)絲底loo接觸，用以冷卻基底 100至-預定溫度，例如5(rc以下，且本發明之最佳預定溫度係 為室溫。 、接著利用現場(in-situ)沈積的方式，控制PVD反應室内之製程 ’皿度在i5〇t以下，以於基底100上濺鑛一金屬層114，並覆蓋於 Θ極、、’。構106、側壁子以及源極/沒極區域us表面，如第3 圖所示。其中，金屬層m係選自鶴、銘、欽、錄、麵、把、翻 等或上述金屬的合金。此外，祕部份之金射化物在形成之後， 幻如NiSi ’ g會造成極大的接面漏電流，因此本發明可再利用一 遮蓋層來避免快速升溫退火(RTA)製程中的氧原子擴散進入，並改 。在7G件隔離區邊緣的材料應力。如第4圖所示持續維持該隱^ 反應室_製程溫度低於靴，並_沈積—由敍或氮化鈦所組 成的遮蓋層116於金屬層114表面，以利用遮蓋層116來抑制後 續快速升溫退火製程時金屬層m之氧含量，進而改善漏電流特 性0 如第5圖所不’接著進行一快速升溫退火製程(rta)，同樣可 利用現場(in-situ)升溫的方式，將基底1〇〇加熱至大約2〇〇〜4〇〇 度。在途行加熱步驟的同時，任何與金屬層m所棚到的閘極 104以及源極娜區域112表面將會反應並形成石夕化金屬層ιΐ8。 絲於快料溫退域爾，再·翻_侧鱗溶液，例 如氨水過氧化氫、鹽酸、硫酸、硝酸、以及醋酸等混和溶液來 12 1297178 進行一飯刻步驟，用以移除未反應之金屬層114以及遮蓋層116。 由於本發明係將置於PVD反應室之基底1〇〇,在完成10(rC至 4〇〇°C的除水氣(degas)步驟之後，便先對基底100進行一冷卻至室 溫的步驟，然後維持該反應室之製程溫度低於150。(：的條件下，依 序沈積一由鎳等原子所組成的金屬層114以及鈦或氮化鈦所組成 的遮蓋層116 ’因此可大量減少初鍍膜(as-(jep〇siti〇n)於金屬藏鏟與 沈積步驟中形成團塊化(agglomeration)及片電阻(sheet resistance) 上升的現象’進而減低淺接面上發生尖突(Spiking)的狀況。除此之 外’本發明在除水氣(degas)之後的冷卻步驟以及低溫濺鍍製程， 更可有效改善習知在進行金屬沈積製程中因溫度過高而導致接面 發生漏電流的問題，並同時降低自對準金屬石夕化物之穿刺(spiking) 以及導通(piping)等效應的產生。 綜合上述說明，請參照第6圖，第6圖為本發明製作一具有矽 化金屬之電晶體元件的流程示意圖。如第6圖所示，本發明之自 對準金屬矽化物(salicide)製程可簡述為下列步驟··首先將一矽晶圓 基底置於一製程反應室中，例如一物理氣相沈積(ρν〇)之製程反應 室，以進行一除水氣步驟161，其中該製程反應室之溫度係介於 100 C至400 C之間。接著進行一冷卻步驟162，用以冷卻該石夕晶 圓基底至一預定溫度，例如50°C以下，且該最佳預定溫度係為一 室溫，藉以降低除水氣步驟161而升高的晶圓溫度。然後控制製 程反應室内的溫度於150°C以下，並進行一金屬濺鍍步驟163，以 13 1297178 . 於制"晶®基底上形成—金制，例如賊鎳合金麵層。最後， 同樣維持製程反應室内之溫度低於15(rc的環境下，進行一沈積步 驟164,用以形成一由鈦或氮化鈦所組成的頂蓋層於錄金屬層上。 相較於習知製作自對準石夕化物的方法，本發明主要提供一種新 製程以減低熱預算，並於形成自對準金屬矽化物於基底時，增進 該自對準金射化物製程在熱預算上的穩定性，除了可減低習知 馨金屬石夕化物因溫度太高或高溫處理時間稍長而發生團快化現象而 導致片電阻上升，並同時能改進後續因高溫製程中發生轉換，消 耗過夕的;^而在接面上造成尖突現象或低電阻率之⑦化錄例明 型悲會被轉變成冑電阻率的二石夕化錄⑽沿態的問題。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變倾修飾，皆蘭本發明之涵蓋細。 _ 【圖式簡單說明】 第1圖與第2圖為習知製作自對準金屬石夕化物的製程示意圖。 第3圖至第5圖為本發日月之自對準金屬石夕化物製程應用在腦電 晶體的製程示意圖。 第6圖為本發贿作_具切化金屬之電晶體元件的流程示意圖。 1297178 【主要元件符號說明】 60 基底 62 64 閘極 66 67 襯墊層 68 70 輕換雜没極結構 72 74 金屬層 76 100 基底 102 104 閘極 106 107 襯墊層 108 110 輕摻雜汲極結構 112 114 金屬層 116 118 石夕化金屬層 161〜164流程方法 閘極介電層 閘極結構 側壁子 源極/汲極區域 矽化金屬層 閘極介電層 閘極結構 侧壁子 源極/>及極區域 遮蓋層 151297178 % • NEXT DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor forest process, and more particularly to a method of making a self-aligned metal salicide. [Prior Art] In the process of a semiconductor integrated circuit, a metal-oxide-semiconductor (MOS) transistor is a very important electronic component, and Ik is becoming smaller and smaller in size, M〇 There are also many improvements in the process steps of s transistors to produce small, high quality MOS transistors. · The known MQS electricity (4) process is to form a lightly doped datum structure (LDD) in the base on opposite sides of the gate structure after forming the structure on the bottom of the semi-conductor. Then, a sidewall thin film is formed on the side of the gate structure, and the gate structure and the sidewall portion are used as a mask, and an ion implantation step is performed to form a source/polar region in the semiconductor substrate. In order to properly electrically connect the gate, source and drain of the transistor to the circuit, it is necessary to form a contact plug (c〇ntactplug) for conducting. Generally, the material of the contact plug is a metal conductor such as tungsten (w) or copper, but the direct conduction between the material such as the gate structure, the source/drain region, or the single crystal germanium is not ideal. Therefore, in order to improve the Ohmicontact between the metal plug and the gate structure and the source/drain region, a metal silicide is usually formed on the surface of the gate structure and the source/drain region. . 6 1297178 目箾大疋 uses a self-aligned metal diced compound (self_aligned welcome, sa]icide) process to form a metal bismuth; that is, after forming the source/drain region a metal layer such as titanium (Ti) or nickel (Ni) covers the source/drain region and the gate structure, and then undergoes a rapid heating and decanting process to make the metal layer and the brewing structure, source/drain region The ruthenium reaction in the formation of metal ruthenium reduces the sheet resistance of the source and the polar regions. However, the formation of metal ruthenium in this way also causes some problems, that is, when forming a metal ruthenium compound, the metal layer The metal atoms in the metal will diffuse into the base of the stone and consume the enthalpy in the source/drain region. Not only will the lattice structure in the original source region be destroyed, it will even cause the source/汲. The distance between the force pN junction and the Shi Xihua metal layer between the polar region and the Shi Xi base will react with the Shi Xi in the source polar region and destroy part of the vine / New _ partial structure, especially in the super surface (_越〇w junction,·) design, even cause metal The ceramsite is in direct contact with the substrate, which in turn causes the component to fail. Please refer to Fig. 1, and Fig. 1 and Fig. 2 show the process of making a self-aligned metal cerium compound. As shown in FIG. 1, first, a gate structure 66 composed of a gate dielectric layer 62 and a gate 64 is formed on the substrate (6), followed by an ion implantation step to form a light doping in the substrate 60. Nothing structure? Hey. A liner layer 67 and sidewall spacers (10) are then formed on the sidewalls of the gate structure 66 and another ion implantation step is performed to form a heterogeneous pure domain 72 in the sidewalls 68. Then a wet cleaning process is performed to remove 1297178 impure particles or native oxide from the gate structure 66 and the source/drain region π surface, and a degas removal step is performed to remove the wet cleaning process. Excess water vapor formed. Subsequently, a metal layer 74, such as a nickel metal layer, is sputtered onto the surface of the substrate 60 and covers the gate 64, the sidewall spacers, and the surface of the substrate 60. As shown in FIG. 2, a rapid thermal anneal (RTA) is then performed to react the portion of the metal layer 74 that is in contact with the gate 64 and the source/drain regions 72 into a deuterated metal layer 76. Finally, a selective wet etching is used to remove the metal layer 74 which has not been reacted into the metalloid compound by, for example, a mixed solution of 2 〇 2 〇 2 甩 2 〇 or H 2 S 〇 4 / H 2 〇 2 . As described above, in order to avoid the MOS short channel effect (also as ηηΜ effects) of the transistor after the transistor design is reduced due to the increase in component positivity, and improve the interconnect resistance of the integrated circuit, Therefore, it is necessary to reduce the junction depth between the source and the immersion of the transistor to fabricate a transistor containing a metal sulphide. However, while the junction depth between the source and the immersion is reduced, if the thickness of the metal bismuth on the source and the drain is thinned, excessive interconnect resistance and contact resistance may be caused. 〇ntact resistance); however, if the metal and cerium on the source and the drain are maintained at a certain thickness, the distance between the PN junction between the source/drain region 72 and the germanium substrate 60 and the germanium metal layer 76 may be caused. Too close causes the MOS transistor to induce junction leakage. Moreover, the solvent used in the wet metal cleaning process such as the wet cleaning process may also invade the liner layer between the gate and the side wall, so that when the Wei metal reaction is subsequently carried out, the Shi Xihua metal is further It is easy to access the channel area, resulting in the so-called "nickd silicide piping effect". 1297178 In addition to this, 'the thermal stability of the metal ceramsite is poor'. As-deposition is initially formed in the metal sputtering process even before the rapid thermal annealing treatment has been carried out. a metal telluride in a polycrystalline (polyCryStalline) structure, that is, when the temperature is too high, due to the higher process temperature of the PVD reaction chamber in which the plasma is generated, or because of the high temperature of the water removal step prior to metal deposition. When the high/span/dish processing time is slightly longer, the phenomenon that j is a sand compound, and the phenomenon of 4fefaggi〇merati〇n) becomes a block of unconnected mass, resulting in an increase in sheet resistance (sheetresistance). Even in the subsequent high-temperature process, switching occurs, excessive enthalpy is consumed, and spiking occurs on the shallow joint or a structure that forms a high resistivity, such as a low-resistivity stone-like nickel type. The state (about less than (9)...-(10)) is converted into a high resistivity Niscianic Ni (NiSi2) type (about 50// Ω-cm). SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide an improved self-aligning metallization process to solve the above-described problems of the prior art. In accordance with the scope of the patent application of the present invention, a self-aligned metal salicide process is disclosed. First, a substrate is provided, and the surface of the substrate comprises at least one conductive layer, and then a degas removal step is performed on the substrate, and the substrate is subjected to a cold step; then a metal layer is deposited on the surface of the substrate. And the metal layer is in contact with the surface of the tantalum conductive layer, and then a thermal process is performed to form a metal layer of the conductive layer of the conductive layer contacting the metal layer, and finally the unreacted metal layer is removed. 1297178 A self-aligned metal telluride process is also disclosed in accordance with the scope of the present invention. Firstly, the surface of the substrate comprises at least one conductive layer, and then a step is performed to form a second layer on the surface of the substrate, and the metal layer is in contact with the surface of the dream conductive layer; And forming a mask layer on the surface of the metal layer, and then heating the annealing process (RTA) to form a germanium metal layer on the surface of the germanium conductive layer contacting the metal layer. Finally, the unreacted metal layer and the covering layer are removed. The present invention mainly provides a new process to reduce the thermal budget, and enhances the thermal budget stability of the self-aligned metal lithium process when forming a self-aligned metal cerium on the substrate. It is known that the metal as a result of the temperature is too high or the high temperature treatment time is a little longer, and the phenomenon of the group is faster, which leads to an increase in the sheet resistance, and at the same time, it can improve the subsequent conversion of the temperature-reducing process towel, and the miscellaneous surface (4) The phenomenon of a sudden or low resistivity nickel-nickel (NiSi) type, which is converted into a high-resistivity Ni-Ni2 type. [Embodiment] Please refer to Figs. 3 to 5, and Fig. 3 to Fig. 5 are diagrams showing the manufacturing process of the self-aligned metal cerium compound process of the present invention. As shown in FIG. 3, a substrate 1GG, such as a mi (wafei) or a sigma (s〇I) substrate, is provided first, and the surface of the substrate 100 has at least one of a single crystal dream, a polycrystalline dream or a worm crystal. The composition of the Shixia conductive layer (not shown). Wherein, the shixi conductive layer can be configured for different product requirements and processes, and includes a structure, a source-level polar region, a word line or a resistor, and the like, in the present invention, 1297178, the third to fifth figures The preferred embodiment is illustrated with a gate structure 102 and a source/drain region 112 of a MOS transistor. As shown in FIG. 3, the gate structure 1〇2 includes a gate dielectric layer 102 and a gate 104, and the gate dielectric layer 1〇2 is composed of a dielectric material such as cerium oxide, and the gate is 104 is composed of a conductive material such as doped polysilicon. Subsequently, a lightly doped ion implantation process is performed, using the gate 104 as a mask and implanting a light impurity (not shown) into the substrate 1 on opposite sides of the gate 104 to form the substrate 100. A source/dipole extension region 110 is formed therein. Next, a liner layer 107, such as an oxygen layer, is formed on the sidewalls of the gate structure 1〇6, and then a sidewall spacer 108 composed of a nitrogen-niobium compound is formed on the liner layer 1〇7. Then, a heavily doped ion implantation is performed, and the gate 104 and the sidewall spacers 108 are used as a mask, and a heavily doped substance (not shown) is implanted into the substrate 100 to form in the substrate 100. A source/nomogram region 112 having a higher doping concentration. A high temperature tempering process is then performed to activate the dopants in the substrate 100 using a high temperature of 1000 to 1050 ° C, and simultaneously repair the crystal lattice of the surface of the substrate 100 damaged in each ion implantation process. structure. Next, a wet cleaning step is performed to remove native oxide (x) and other impurities remaining on the top of the gate 104 and the source/drain region 112. Then, after the substrate 100 is placed in a physical vapor deposition (PYJ) reaction chamber, a degas removal step is performed on the substrate 100 at a temperature of 100 ° C to 400 ° C to remove the wet cleaning. The step is residual water remaining on the surface of the substrate 1 (8). Then, a cooling step is performed, for example, using an inert gas or a crystal 11 11297178, to cool the substrate 100 to a predetermined temperature, for example, 5 (rc or less, and the most Preferably, the predetermined temperature is room temperature. Then, by in-situ deposition, the process of controlling the PVD reaction chamber is below the i5〇t, so as to splash a metal layer 114 on the substrate 100 and cover it. In the bungee pole, the 'structure 106, the side wall and the source/no-polar area us surface, as shown in Figure 3. Among them, the metal layer m is selected from the group consisting of crane, Ming, Qin, recorded, face, handle, and Or the alloy of the above metal. In addition, after the formation of the metallization of the secret part, the illusion of NiSi'g causes a great junction leakage current, so the present invention can reuse a cover layer to avoid rapid temperature annealing (RTA). The oxygen atoms in the process diffuse into and change. The material stress at the edge of the 7G isolation zone. As shown in Figure 4, the process is maintained continuously. The process temperature is lower than the shoe, and _ deposition—by Syria or nitrogen The cover layer 116 composed of titanium is on the surface of the metal layer 114 The cover layer 116 is used to suppress the oxygen content of the metal layer m during the subsequent rapid temperature-up annealing process, thereby improving the leakage current characteristic. 0, as shown in FIG. 5, then a rapid temperature annealing process (rta) is performed, and the field can also be utilized (in -situ) The temperature of the substrate is heated to about 2 〇〇 to 4 〇〇 degrees. At the same time as the heating step, any gate 104 and source surface 112 immersed in the metal layer m Will react and form the Shixi chemical metal layer ιΐ8. The silk is retreated in the fast material temperature, and then the scaly solution, such as ammonia hydrogen peroxide, hydrochloric acid, sulfuric acid, nitric acid, and acetic acid, etc., is mixed to 12 1297178. A meal step to remove the unreacted metal layer 114 and the cover layer 116. Since the present invention is to be placed in the substrate of the PVD reaction chamber, the completion of 10 (rC to 4 ° ° C water removal) After the degas step, the substrate 100 is first cooled to room temperature, and then the process temperature of the reaction chamber is maintained below 150. Under the condition of:, a layer of atoms such as nickel is sequentially deposited. Metal layer 114 and titanium or titanium nitride The cover layer 116' can thus greatly reduce the initial coating (as-(jep〇siti〇n) in the metal shovel and deposition step to form agglomeration and sheet resistance rise phenomenon" and thus reduce shallow Spiking occurs on the joint. In addition, the cooling step of the present invention after degas removal and the low-temperature sputtering process can effectively improve the temperature during the metal deposition process. Excessively high leads to leakage currents at the junction, and at the same time reduces the effects of spiking andpiping of the self-aligned metallurgical compound. For a comprehensive description of the above, please refer to FIG. 6. FIG. 6 is a schematic flow chart of fabricating a transistor having a metallization according to the present invention. As shown in Fig. 6, the salicide process of the present invention can be briefly described as the following steps: First, a wafer substrate is placed in a process chamber, such as a physical vapor deposition ( The process chamber of ρν〇) is subjected to a water removal step 161 wherein the temperature of the process chamber is between 100 C and 400 C. Then, a cooling step 162 is performed to cool the base wafer substrate to a predetermined temperature, for example, 50 ° C or lower, and the optimal predetermined temperature is a room temperature, thereby lowering the water removal step 161. Wafer temperature. Then, the temperature in the process chamber is controlled to be below 150 ° C, and a metal sputtering step 163 is performed to form a gold-made, for example, thief nickel alloy surface layer on the substrate. Finally, while maintaining the temperature in the process chamber below 15 (rc environment, a deposition step 164 is performed to form a cap layer composed of titanium or titanium nitride on the metal layer. Knowing the method of making a self-aligned lithium compound, the present invention mainly provides a new process to reduce the thermal budget and enhance the self-aligned metallization process on the thermal budget when forming a self-aligned metal lanthanide on the substrate. Stability, in addition to reducing the temperature of the well-known Xinshi Shishi compound due to too high temperature or high temperature treatment time, resulting in a group faster phenomenon, resulting in a rise in sheet resistance, and at the same time can improve the subsequent conversion due to high temperature process, the consumption of the night; ^ The problem of causing a sharp phenomenon or a low resistivity on the junction is transformed into a problem of the 二 胄 胄 ( ( ( ( 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In the preferred embodiment, the uniform variation of the invention according to the scope of the present invention is as follows. _ [Simple description of the drawings] Figs. 1 and 2 show the self-aligned metal stone. Xi'an process Intentions Fig. 3 to Fig. 5 are schematic diagrams showing the process of applying the self-aligned metallite process in the brain to the electroencephalogram. Fig. 6 is the bribery of the transistor element with a metal cutting Schematic diagram of the process. 1297178 [Description of main components] 60 Substrate 62 64 Gate 66 67 Liner layer 68 70 Light-replacement structure 72 74 Metal layer 76 100 Substrate 102 104 Gate 106 107 Liner layer 108 110 Lightly doped Pole structure 112 114 metal layer 116 118 Shi Xihua metal layer 161~164 process method gate dielectric layer gate structure sidewall sub-source/drain region metallization metal layer gate dielectric layer gate structure sidewall source Pole/> and polar region cover layer 15