TW531792B - Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing - Google Patents

Abstract

A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance nickel silicide region (56, 58). Unreacted nickel (54) is removed. A dielectric layer (60) is then deposited over the high resistance nickel silicide regions (56, 58). In a second temperature treatment, the at least one high resistance nickel silicide region (56, 58) and dielectric layer (60) are reacted at a prescribed temperature to form at least one low resistance silicide region (64, 66) and process the dielectric layer (60). Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel (54) between nickel silicide regions (56, 58) is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions (56, 58) and the dielectric layer (60) are conveniently combined into a single temperature treatment. In other embodiments, the second temperature treatment is performed prior to, and separate from, the depositing and processing of the dielectric layer (60).

Description

531792 A7

V. Description of the invention (i) [Technical scope of the invention] (Please read the precautions on the back before filling out this page) This post is about a method for forming nickel silicide using a single step rapid thermal annealing treatment and a tail end process. . [Background of the Invention] In the semiconductor process industry, the formation of self-aligned silicide is known as a method of integrating into a low-resistance material on a pre-defined area of a semiconductor structure to be processed to form a semiconductor device. In detail, the self-aligned silicide process is a method of reacting a silicon region of a semiconductor structure with a metal to form a silicide region. These self-aligned silicides can be selectively formed on their semiconductor structures, without having to pattern or etch the already-built silicides to form some low-resistance areas. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, titanium, cobalt, and nickel are metals that have been used to react with silicon materials to form self-aligned silicides on semiconductor structures. In the self-alignment method, titanium silicide can be formed on a semiconductor structure. FIG. 丨 shows an exemplary stone matrix 10 with a polycrystalline silicon region 16 formed on the silicon matrix 10. Adjacent to this polycrystalline silicon region 16, there are some spacers 14. These spacers 14 may be oxide, nitride, or other ceramic materials. The silicon substrates 10 have some active regions 12, which are doped silicon in characteristics, and can be used as the source and the anode of a transistor on the power b. In Figure 2, a layer of titanium metal or titanium alloy 18 is deposited on the semiconductor structure of Figure 1. The semiconductor structure of FIG. 2 is then subjected to a first rapid thermal annealing (RTA) in a temperature range of 550 1 to 750 ° C. FIG. 3 shows the semiconductor structure of FIG. 2 after the first rapid thermal annealing. There are certain titanium metal or titanium alloy layers 18 that will react with its polycrystalline silicon region 16. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 1 91991 531792 A7 —--- ~~-~ ___ V. Description of the invention (2) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to form a silicon resistive silicide (TiSi2) area22. In addition, some titanium layers 18 may react with the silicon of its active region 12 to form a high-resistance titanium silicide (TiSi2) region 20. During the first rapid thermal anneal, no titanium layer i8 will react with its spacer 14. Since silicides are not formed on the spacers, the high-resistance titanium silicide regions 20 and 22 are formed in a self-aligning manner because they do not need to be patterned or etched away from the spacers. To define the polysilicon regions 16 and the titanium silicide regions 20 and 22 above the active region 12. It is improper to form silicides on the spacers 14, because this will cause a bridge between their gate and source / drain regions 12. The titanium in the unreacted metal 19 in Fig. 3 is stripped using a conventional stripping technique. Fig. 4 shows the semiconductor structure of Fig. 3 after the unreacted metal layer 19 is stripped. The high-resistance titanium silicide regions 20 and 22 will be formed integrally with the semiconductor structure after wet stripping of the unreacted metal 19 described above. The semiconductor structure of FIG. 4 is then subjected to a second rapid thermal annealing in a temperature range of 750C to 900C. Figure 5 shows the semiconductor structure of Figure 4 after the second rapid thermal annealing of the semiconductor structure. Among them, the high-resistance titanium oxide regions 20 and 22 will react to form some low-resistance silicon oxide compounds (TiSh). Areas 24, 26. The low-resistance siliconized titanium regions 24 are formed on the polycrystalline silicon region 16, and the low-resistance titanium siliconized regions 26 are formed on the active region i2 of the silicon substrate 10. Titanium is used as described above. The two-step rapid thermal annealing process for forming a low-resistance titanium silicide in a self-aligned manner of a metal or titanium alloy layer has several disadvantages. With the advancement of semiconductor technology, a certain semiconductor structure size, this paper size applies to China National Standard (CNS) A4 specification (21G X 297 public love) ------ 2 91991 531792 A7

V. Description of the invention ((Please read the notes on the back before filling out this page) The Intellectual Property Bureau of the Ministry of Economic Affairs' employee consumer cooperatives hope to become smaller. For example, it is hoped that these polycrystalline silicon regions 16 and spacers 14 will be used in semiconductors. The formation on the substrate 10 can be as small as possible, thereby using this type of structure to enhance the performance of their semiconductor devices. For example, their transistors using this general semiconductor structure are designed and designed on such a small scale. Realize 'enable these transistors to execute computer instructions at a faster speed. They often need to form low-resistance titanium oxide regions on their semiconductor structures' to promote the electrical properties of the semiconductor components of a semiconductor device. These exemplary regions are the active region 12 and the polycrystalline stone region 16 in Fig. 5. Titanium is used in a two-step rapid thermal annealing process to form > titanium oxide in a self-aligning manner. Is not effective for smaller-scale semiconductor structures because the metal or silver alloy layers are not similar to their polycrystalline silicon regions 16 and 15 in Figures 1 to 5. The small surface of silicon material such as active region 12 completely reacts. The reason behind this shortcoming of titanium in a self-aligning process is that the reaction between titanium and silicon material is subject to the nucleation of the silicide, and therefore the Shixi compounds are not formed in a consistent manner. As illustrated in Figures 3 to 5, the reaction of titanium metal or titanium alloy with Shixi materials will form some scattered and inconsistent titanium silicide regions, which are not applicable. The formation of silicide regions in certain semiconductor devices such as transistors. Since not all Chin metals or Chin alloys will react on the broken materials of small semiconductor structures, the reaction between titanium and stone materials is not suitable. Reduce the resistance value of the silicon component of the semiconductor structure. Therefore, the use of titanium for relatively small semiconductor structures is not sufficient to achieve the purpose of forming silicide in a self-aligned manner. The limitation of using titanium in a self-aligned stone compound , Often referred to as the dependency of line width. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 3 91991 53179 2 A7 ----- 2Z______ V. Description of the Invention (4) (Please read the notes on the back before filling this page) Using titanium metal or titanium alloy to form Shi Xihuaqin in a semiconductor structure Yes, the temperatures encountered by these first and second rapid thermal anneals are quite high. These high temperatures limit the use of self-aligned semiconductors = design in semiconductor structures. Their high temperatures can induce stress on the semiconductor structure and can damage it. The function of its semiconductor device. Other shortcomings of forming a two-step rapid thermal annealing procedure of titanium silicide are also common. Cobalt printed by the consumer cooperative of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs can also react with silicon materials such as polycrystalline silicon or silicon substrates. A self-aligned cobalt silicide region is formed in the semiconductor structure. For example, FIG. 6 shows a semiconductor substrate ⑺ having an active region 12 and a polycrystalline silicon region 16 formed on the semiconductor substrate 10. These spacers are formed on the silicon substrate 10 and are adjacent to the polycrystalline silicon region 16. As shown in FIG. 7, a layer of cobalt metal or cobalt alloy 28 is formed on the semiconductor structure of FIG. The semiconductor structure of FIG. 7 will be subjected to a temperature range of 450. (: To 51 (Figure 8 of the first rapid thermal annealing in TC) shows the high-resistance cobalt silicide (CoSi) formed on the polycrystalline broken regions 16 and the active regions 12 and is the product of the first rapid thermal annealing process. ) Regions 30, 32. Any unreacted metallic cobalt or cobalt alloy 29 is wet-striated using conventional stripping techniques. Figure 9 shows the semiconductor structure of Figure 8 'which is stripping unreacted metal cobalt Or cobalt alloy 29, on the polycrystalline silicon region 16 and active region 12 of the above-mentioned stone matrix 10, there are high-resistance fragmentation initiation regions 30 and 32. No cobalt silicide is formed on the spacers 14; this feature is exemplified The self-aligning characteristics of their self-aligned silicides. In addition, their stripping operation will not strip any formed cobalt silicide, and it will strip only their unreacted metallic cobalt or alloys. The paper size of the figure applies to the Chinese National Standard (CNS) A4 specification (21G X 297 public love) "-4 91991 531792 A7

Semiconductor structures printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs will then be subjected to a second rapid thermal annealing in a temperature range of 760 ° C to 840 ° C. This second rapid thermal annealing can cause these high-resistance cobalt sulfide regions 30 and 32 to react to form some low-resistance cobalt silicide (coSi2) regions 34 and 36. Figure 10 shows the low-resistance cobalt silicide regions 34, 36 formed on the polycrystalline silicon region 10 of the silicon substrate 10 and the active region 12 above. There are several disadvantages to using a metal or starting alloy in semiconductor processes to react with broken materials to produce silicified #. One disadvantage is that it forms a low resistance (the two-step rapid thermal annealing process required for Co Sid, which will require quite high temperatures. These high temperatures may not be compatible with the semiconductor process of existing components of its semiconductor structure, or it Hopefully, in particular, these high temperatures can induce stress on other semiconductor components and / or diffusion materials of existing semiconductor structures. The use of nickel to form self-aligning dream compounds has established a rapid thermal annealing process using a single step. In other words, FIG. 11 shows a stone matrix 10 with an active region 12. A polycrystalline silicon region 16 is formed on the stone matrix, and the spacers 14 are formed adjacent to the polycrystalline silicon region 16. In FIG. 11 An exemplary semiconductor structure has a layer of nickel metal or nickel alloy formed on it. For example, Figure 12 shows a layer of nickel metal or nickel alloy 38 formed over the semiconductor structure on figure u. A single step rapid thermal annealing, system Performed at a temperature ranging from 350 ° to 700 ° to react the nickel metal or nickel alloy to form a silicon with a relatively low resistance For example, Figure 13 depicts the silicide regions 40, 42 formed from this single step of rapid thermal annealing. At the necessary rapid thermal annealing temperature ranging from 3500c to 700 ° force, ' The size of the silicon paper sheet formed on the active areas 12 applies the Chinese National Standard (CNS) A4 specification⑵G x 297 5 91991 --- Aw -------- t ----- I (please first Read the note on the back? Matters and then fill out this page) Line · ϋ ϋ-531792 A7 V. Description of the invention (6 Nickel and polycrystalline dream region 16 formed by the cleavage of plutonium, undesired bridging may occur. Peeling In addition to the unreacted nickel layer 4A, the structure is left. (Please read the precautions on the back before filling out this page.) The rapid thermal annealing of the above nickel silicide in one step will cause some problems. The relatively difficult-to-control reaction and excess formation of Shi Xihualu will be seen in FIG. 14 between the nickel silicide 40 formed on the polycrystalline silicon region 16 and the nickel silicide 42 formed on the active region 12 'causing the above. [Brief of the Invention] A. Self-aligning silicide process requires Low heat pre-differentiation is allowed during processing, and a controlled silicidation reaction between metal or alloy and silicon material is allowed. In addition, a self-aligned silicide process requires process steps that can be combined with the fabrication of semiconductor devices. Bureau of Intellectual Property, Ministry of Economic Affairs These and other needs for employee consumer cooperatives can be met by embodiments of the present invention, which provide a single-step temperature processing procedure and tail-end process to form some self-aligned nickel silicide in a semiconductor structure. The invention includes depositing a layer of nickel metal or nickel alloy on a silicon material. At least a portion of the nickel metal or alloy will react with at least a portion of the silicon layer at a first temperature during a first cycle to Forming at least one high-resistance nickel silicide layer. Unreacted nickel metal or nickel alloy will be removed from the semiconductor structure, leaving at least one integrated body in the high-resistance silicide layer of the semiconductor structure. Over this at least one high-resistance nickel silicide layer, a dielectric layer is then deposited. This dielectric layer and at least one high-resistance nickel silicide layer will undergo a second temperature during a second cycle to form at least one low-electricity paper. The paper is compliant with China National Standard (CNS) A4 specifications (210 X 297 male f ~ ----- 91991 531792 A7

5. Description of the invention (7) Nickel silicide blocking layer. The invention has the advantage that silicide can be produced at a relatively low temperature. Please fill in this page again. This feature reduces stress on other existing semiconductor components of a semiconductor structure. This feature also allows semiconductor processes with more complex and useful semiconductor structures. Another advantage of the present invention is that the nickel metal layers can react with the siliceous material layers in a controlled manner. This is an important and useful attribute. Covering enough nickel silicide will react so that the dependence of the line width will not become an obstacle, and between the fragmentation regions formed on the same semiconductor and structure. Will avoid bridging. In addition, the present invention has the advantage of combining the process of the high-resistance nickel silicide layer with the process of the dielectric in a single step during the second temperature for a period of the second cycle. The need to print a narrative by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics can also be met by the embodiment of the present invention, which provides a two-step temperature processing program that can form a self-aligned lithography within a semiconductor structure Nickel area. This two-step temperature treatment includes layering metal or alloy on top of the shredded material. At least a portion of the nickel metal or alloy will react with at least a portion of the silicon layer at a first temperature during a first cycle to form at least one high-resistance nickelized nickel layer. All unreacted nickel metal or nickel alloy will be removed 'from the semiconductor structure, leaving at least one high resistance dream compound layer integrated into the semiconductor structure. The at least one south resistance shredded layer will have a period of 'reaction at the first temperature' for a second period to form at least one low resistance shattered nickel layer. The invention has the advantages that it can be manufactured at a relatively low temperature; the paper size of the compound is suitable for the Chinese National Standard (CNS) A4 (210 X 297 mm)-7 91991 531792 V. Description of the invention (8) This feature can reduce the stress on other existing semiconductor components of a semiconductor structure. This feature allows semiconductor processes with more complex and useful semiconductor structures. Another advantage of the present invention is that the metal recording layers can react with the siliceous material layers in a controlled manner. This is an important and useful genus, which is covered with enough stone chemistry to react, so that the dependence of the line width will not become an obstacle and the silicide regions formed on the same semiconductor structure. This will avoid bridging. The foregoing and other features, shapes, and advantages of the present invention will be made clearer by the following detailed description in conjunction with the accompanying drawings. [Brief description of the diagram] FIG. 1 is a conventional technical diagram of a typical semiconductor structure before a silicide is formed; FIG. 2 is a semiconductor structure of FIG. F 1 on which a titanium metal is deposited A conventional technology diagram of a titanium or titanium alloy layer; FIG. 3 is a conventional technology diagram of the semiconductor structure of FIG. 2 after the first rapid thermal annealing; FIG. 4 is a removal of the semiconductor structure of FIG. 3 A schematic diagram of a conventional technique after its unreacted metal or titanium alloy; FIG. 5 is a schematic diagram of a conventional technique after the second rapid thermal annealing of the semiconductor structure of FIG. 4; and FIG. 6 is a silicidation A schematic diagram of a conventional technology of a former typical semiconductor structure; FIG. 7 is a schematic diagram of a conventional technology of the semiconductor structure of FIG. 6 on which a cobalt metal or cobalt alloy layer is deposited; The paper size applies Chinese National Standard (CNS) A4 regulations; 297) 8 ▲ 91991 531792 A7 B7 V. Description of the invention (9 Figure 8 is the semiconductor process of Figure 7 ~ a practice constructed after the first rapid thermal annealing Technical diagram; Figure 9 is of Figure 8 A schematic diagram of a conventional technique of the cage structure at the conductor after removing its unreacted cobalt metal or cobalt alloy; FIG. 10 is a conventional technique of the semiconductor structure of FIG. 9 after the second rapid thermal annealing Figure 11 is a schematic diagram of a conventional technique of a typical semiconductor structure along the line of Shi Xihuanshi 籾 籾; Figure 12 is a semiconductor structure of the l1W semiconductor on which nickel metal is deposited. Or a nickel alloy layer—a conventional technology diagram; FIG. 13 is a conventional technology diagram of the semiconducting I # Modified Broadcasting and Ding Shou forging structure of FIG. 12 after the early rapid thermal annealing; Fig. 14 is a schematic diagram of a conventional technique after the semi-conducting Xingde + # of the dry mouth is removed from its unreacted nickel metal or nickel alloy. Fig. 15 is a simplified diagram of a semiconductor structure. FIG. 16 is a schematic diagram of the semiconductor structure of FIG. 15 on which a nickel metal or nickel alloy layer is deposited; FIG. 17 is a schematic diagram of the semiconductor structure of FIG. 16 after a first temperature treatment Figure 18 is the unreacted semiconductor structure in Figure 17 when it is removed A schematic diagram of nickel metal or nickel alloy; Figure 19 is a schematic diagram of the semiconductor structure of Figure 18 after a dielectric layer is deposited; (Please read the precautions on the back before filling this page) Order --------- Line! Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

9 91991 531792 A7 B7 V. Description of the invention (: A simple picture printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. [Explanation of Symbols of Components] 10 Silicon substrate / Semiconductor substrate 12 Separator 16 Titanium metal or titanium alloy layer 19 High resistance Titanium silicide area High resistance silicide (TiSi2) area 26 Low resistance lithium oxide (TiSi2) area Drilling metal or alloy layer unreacted metal cobalt or cobalt alloy 32 High resistance lithography (CoSi) area 36 Low resistance silicidation Cobalt (CoSi2) region Nickel metal or nickel alloy 40, 42 Lithium oxide region Nickel layer 44 Silicon substrate active region 48 Separator polycrystalline silicon region 52 Nickel metal or nickel alloy Unreacted nickel metal or nickel alloy 58 High resistance nickel silicide region 60 , 62 dielectric layer, 66 silicon oxide region [detailed description of the preferred embodiment] The present invention relates to a single-step temperature treatment and tail end process for forming nickel silicide on a semiconductor structure. The procedure of the present invention includes A nickel metal or nickel alloy is deposited on a silicon layer. The nickel metal or nickel alloy and the stone layer will react at a first temperature during the first cycle to 14 18 20 22 24 28 29 30 34 38 4A 46 50 54 56 64 Active area polycrystalline silicon area unreacted metal titanium layer 10 91991 (Please read the precautions on the back before filling this page) Order --------- Line!

Forming at least one high-resistance nickel silicide layer. The unreacted nickel metal or nickel alloy is then stripped, and at least one high-resistance nickel silicide layer can be kept integrated into the semiconductor structure. Above this higher-resistance nickel silicide region, there will then be | flammability; | electrical layer. The dielectric layer and at least one high-resistance nickel silicide will undergo a second temperature during a second period to form at least a low-resistance nickel silicide region. By adopting a single-step temperature treatment and a tail-end process to replace the single-step rapid thermal annealing process used in the conversion of nickel silicide, the present invention can reduce the bridging phenomenon between petrified compounds of a semiconductor device, and the T reduction treatment The number of steps required for a conductor device. In another embodiment of the present invention, the second annealing step is performed before depositing its dielectric layer to form the low-resistance nickel silicide regions. FIG. 15 is an exemplary semiconductor structure. The semiconductor structure includes a silicon substrate 44 on which a polycrystalline silicon region 50 is formed. Adjacent to this polysilicon region 50 are spacers 48. The silicon substrate 44 may also include some active regions. These active regions can be characterized by doped silicon. The polycrystalline silicon region 50 formed on the above silicon substrate 44 can be used as a transistor #, and the active region cups can be used as the source and the drain of a transistor. The spacers 48 may be formed of an oxide, a nitride, or other ceramic materials. The functions of the spacers 48 may be to "isolate" the polycrystalline silicon region 50 from the active regions, or to isolate the gate of a transistor from the source and anode of a transistor.

Fig. 16 shows the semiconductor structure of Fig. 15 after their nickel metal or nickel alloy 52 has been deposited onto the semiconductor structure in a conventional manner.帛 Figure 17 ^ Pioneer of Gifts A This paper size applies to China National Standard (CNS) A4 specifications

0 t --------- line! (Please read the notes on the back before filling out this page) 11 531792 A7 12 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (making its nickel metal or nickel alloy 52 with these polycrystalline silicon regions 50 and active regions 46 reaction to form a high-resistance nickel silicide (three or two "region) after a first temperature treatment. This first temperature treatment is in a range of 25 ° C to 35 ° C. This temperature treatment is compared with the single-step rapid thermal annealing temperature used to establish nickel silicide used in the conventional technology, or the first rapid thermal annealing used in the conventional technology titanium titanium silicide or the conventional technology cobalt cobalt silicide. The temperature is relatively low. In addition, its first temperature treatment can be a rapid thermal annealing characterized by a rapid ramp-up and rapid ramp-down of its temperature during a relatively short period of time. They Exemplary annealing procedures that can be used for rapid thermal annealing include laser annealing procedures, electric lamp heating annealing procedures, or other radiation annealing procedures. The first temperature treatment can experience a range of-15 seconds. The first cycle time is 90 seconds, but it is preferably 30 seconds to 60 seconds. In Figure 18 and Figure 17, the semiconductor structure is stripped of its unreacted nickel metal by a conventional stripping technique. Or nickel alloy 54. Their exemplary conventional stripping techniques include the use of sulfur peroxide, hydrochloric acid, nitric acid, phosphoric acid, or a mixture of these stripping agents. The stripping of unreacted metal or metal alloy 54, The high-resistance nickel silicide regions 56, 58 formed during the first temperature treatment will not be removed. In addition, there is no: metal or nickel alloy 52 reaction on the spacers 48 because these spacers are formed by Formation of oxides or nitrided fields or other similar materials. Nickel halide—the low level used in the formation phase. ✓ Reflected in a typical generation ^ ^ What may happen during the early steps of nickel silicide formation can be avoided Uncontrolled petrified compounds are formed on the spacers 48. Yes, because the petrified nickel "this sheet size is in compliance with" National Standard 91991 "ϋ ϋ n ϋ ϋ I nn ϋ ϋ ϋ I · I ϋ n H ϋ ϋ ϋ η η «n ϋ II ϋ I ϋ I ϋ ϋ ϋ nn HI ϋ ϋ ϋ ϋ ϋ I ϋ ϋ n ϋ ϋ ϋ ϋ ϋ I I (please read the Notes on the back to fill out Page) 12 531792 A7

V. Description of the invention (13) It will not be necessary to be engraved for isolating the nickel sulfide regions 56, 58 at the desired positions above the semiconductor structure. FIG. 19 is an illustration of a dielectric layer deposited over the semiconductor structure of FIG. 18. FIG. The dielectric layer 60 is another component of the semiconductor structure, and may not be related to the formation of silicide in the semiconductor structure. The dielectric layer 60 can be used as an isolation layer before undergoing a temperature treatment process. FIG. 20 is a diagram of the semiconductor structure of FIG. 19 after a second temperature treatment according to an exemplary embodiment of the present invention. This second temperature treatment is performed at a temperature ranging from 350 ° C to 700 ° C. In addition, the second temperature treatment may be a rapid thermal annealing having a characteristic of rapid ramp-up and rapid ramp-down to a target temperature for this temperature processing. The high-resistance petrified nickel region of the embodiment of FIG. 18 will react ("transform") to form low-resistance nickel silicide regions (NiSi) 64 and 66. In addition, the second temperature treatment can also be used to The dielectric layer 60 shown in Fig. 19 is processed into the dielectric layer 62 shown in Fig. 20. The process of the lithosphere regions 56, 58 and the dielectric layer 60 is a tail-end process. This tail-end process is part of this technique. A term used to describe the processing steps performed in a subsequent step. In some preferred embodiments, the second temperature treatment described above is at a temperature in the range of about 35 ° C to about 700 ° C. In order to form the nickel silicide with the lowest resistance, and to maintain a reasonable low thermal budget, the second temperature treatment is quite low compared to the conventional technology required for other types of silicides < rapid thermal annealing temperature. The time period related to the second temperature treatment may be between 15 seconds and 15 minutes. In another embodiment, the second temperature treatment described above applies the Chinese national standard on the dielectric paper scale ( CNS) A4 size (210 X 297 mm) 91991- ----------- Sickle (Please read the note on the back? Matters before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 11111111 — — — — — — — — — — — — — — — — — — — — — — 13 14 531792 A7 ___ Β7 _____ It is stated (14) that 60 is performed before deposition, and thus its lower resistance nickel silicide can be formed separately from its associated tail end process. The present invention provides a self-aligned silicide process that allows low calculations and can form silicide regions on a small scale in a controlled reaction. The present invention can pass a single step temperature that can form high-resistance nickel silicide. And tail-end processes to process a dielectric layer and to form low-resistance nickel silicides from high-resistance silicon. In the first temperature treatment, their nickel-gold-nickel alloys will react with a stone material to form High resistance; nickel oxide, its unreacted metal or nickel alloy, will then come from the semiconductor structure. On top of these high resistance nickel silicide areas, a dielectric will be deposited. In the second temperature treatment, the Contour resistance The nickelized region will react at a temperature to form a low-resistance nickel sulfide and to simultaneously process the electrical layer. The use of two-step temperature treatment allows a controlled method and a relatively low temperature. The formation of small-scale chopping compounds can effectively form silicides, and allow a low thermal budget for a semiconductor process, while largely avoiding the bridging phenomenon that they are familiar with in the formation of petrified nickel. In addition, The present invention can combine these dielectric layers and high-resistance silicide regions in the same temperature step. Although the present invention has been described and illustrated in detail, it should be clear that f is, they are only illustrations And examples, and should not be construed as limiting, the scope of the present invention is defined by the scope of the attached patent application. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public love) 91991 (Please read the precautions on the back before filling this page) Order --------- Line! -H ϋ n ϋ n

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Claims (1)

Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 531792 C8 VI. Application for Patent Scope 1 · A semiconductor process method including the steps of: depositing nickel metal or nickel alloy (52) on at least one silicon layer (46) ); During a first cycle, at least a portion of the nickel metal or nickel alloy (52) is reacted with the silicon layer (45) at a first temperature to form at least one high-resistance nickel silicide region ( 56,58) ·· Removing unreacted nickel metal or nickel alloy (54); and during a second cycle, at a second temperature, the rubidium resistors are turned into nickel regions (56,58 ) Reaction to form at least one low-resistance lithography region (64,66). 2. If the semiconductor manufacturing method according to item 1 of the patent application scope includes: before reacting the high-resistance nickel silicide regions (56,58), at least one of the high-resistance nickel silicide regions (56,58), A dielectric layer (60) is deposited. 3. The semiconductor process method according to item 1 of the patent application range, wherein the first temperature is in a range of about 250 ° C to about 350 ° C. 4. The semiconductor process method according to the first patent application range, wherein the second temperature is in a range of about 400 ° C to about 600 ° C. 5. The semiconductor process method according to item 1 of the patent application scope, wherein the high-resistance nickel silicide region (56,58) is at least one of N "Si and Niji 'and its low-resistance crushed nickel region (64, 66) Department] sjiSi. 6. The semiconductor manufacturing method according to item 1 of the patent application range, wherein the period from the first gastric period is about 15 to about 90 seconds, and the period from the second period is about 15 to about 90 seconds. 7 .If you apply for the semiconductor manufacturing method of item 1 of the patent scope, in which the _stomach — — — — — I1IIII -Him — ^ · 11111111-(Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) A4 specification (210 X 297 mm) 15 91991 531792 A8B8C8D8 VI. During the patent application period, it is about 30 to about 60 seconds, and during the second cycle, it is about 30 to about 60 seconds. 8. If you apply The semiconductor process method of the first item in the patent scope, wherein the first and second reaction steps form a two-step rapid thermal annealing process. 9. For the semiconductor process method of the second item of the patent scope, the first reaction step and the second step Reaction steps It is a single-step rapid thermal annealing process with a tail end process. (Please read the precautions on the back before filling this page.) Printed on paper standards applicable to the Chinese National Standard (CNS) A4 specifications. (210 X 297 mm) 16 91991