WO2002046911A1 - Circuit d'elevation au carre avec dephaseur et additionneur selectionnable - Google Patents

Circuit d'elevation au carre avec dephaseur et additionneur selectionnable Download PDF

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Publication number
WO2002046911A1
WO2002046911A1 PCT/GB2001/005278 GB0105278W WO0246911A1 WO 2002046911 A1 WO2002046911 A1 WO 2002046911A1 GB 0105278 W GB0105278 W GB 0105278W WO 0246911 A1 WO0246911 A1 WO 0246911A1
Authority
WO
WIPO (PCT)
Prior art keywords
operand
shifted
bit
squaring
total
Prior art date
Application number
PCT/GB2001/005278
Other languages
English (en)
Inventor
Mel Long
Original Assignee
Ubinetics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ubinetics Limited filed Critical Ubinetics Limited
Priority to AU2002219317A priority Critical patent/AU2002219317A1/en
Publication of WO2002046911A1 publication Critical patent/WO2002046911A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/552—Powers or roots, e.g. Pythagorean sums
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/552—Indexing scheme relating to groups G06F7/552 - G06F7/5525
    • G06F2207/5523—Calculates a power, e.g. the square, of a number or a function, e.g. polynomials

Definitions

  • the invention relates to data processing involving the squaring of a number.
  • multipliers which are bespoke devices for multiplying together the values held in two operand registers. To calculate the square of number, the same operand is loaded into each of the operand registers for the multiplier.
  • the invention provides apparatus for squaring a binary operand, comprising shifting means and adding means, wherein the shifting means shifts the operand and the adding means selectably adds the shifted operand to a binary total.
  • a method of squaring a binary operand comprising shifting the operand and selectably adding the shifted operand to a binary total.
  • Multiplication performed in accordance with the invention lends itself to performance by apparatus which consumes a small (relative to conventional multiplier) amount of area in an integrated circuit.
  • the addition is performed if a selected bit of the operand is in a predetermined state.
  • the predetermined state is "logical 1".
  • the shifting procedure may produce a plurality of shifted operands, each subjected to a different shift.
  • Each of the shifted operands may have a corresponding operand bit, such that the shift of a shifted operand corresponds to the distance of the corresponding operand bit from the operand's least significant end.
  • the selectable addition of shifted operands may be performed by determining that the shifted operand is to be added to the total if the shifted operand's corresponding bit is in a predetermined state (e.g. "logical 1").
  • the shifted operands are produced sequentially, and a shifted operand is selectably added to the total before the succeeding shifted operand is produced. This feature allows the multiplication process to be performed recursively, consequentially reducing the amount of data storage that needs to be engaged for the multiplication process.
  • the invention may be exploited in the processing of digital signals.
  • the invention can be used to condition a digital signal by, for example, producing a signal which is the square or the modulus of an input signal.
  • the invention could be used in the measurement of a quantity such as the power in a digital signal, by calculating Hie squared amplitude of the digital signal.
  • the invention can be employed to condition signals in communications systems or navigation systems.
  • the invention also extends to a program causing data processing apparatus to perform a method according to the invention.
  • the invention may comprise a program which causes a digital signal processor to condition an input signal by calculating a signal which is the square of the input signal (e.g. for power estimation of the input signal).
  • FIG. 1 is a block diagram of a squaring device in an integrated circuit.
  • a binary number, Z, to be squared is input to squaring circuit 10.
  • the number Z is supplied to each of a shifter 12 and a bit selector 14.
  • the shifter 12 outputs an addend to an adder 16.
  • Selector 14 outputs a bit selected from the binary word Z to adder 16 as a control input.
  • the second addend for adder 16 is fed back from a result register 18 which stores the augend output by adder 16.
  • the squaring process is controlled by controller 20 which produces signals Si, S 2 and S 3 for controlling the operation of the shifter 12, the selector 14 and the register 18, respectively.
  • Z is a three bit number and, consequently, Z 2 is a 6 bit number.
  • Z is 101 (decimal 5).
  • Register 18 is initialised by controller 20.
  • the shifter 12 supplies an unshifted version of Z, 101, as an addend to adder 16.
  • the selector 14 transfers the least significant bit of Z as a control input to adder 16.
  • the contents of register 18 (000) are supplied to adder 16 as the other addend.
  • the adder 16 sums the addends if the control signal from the selector 14 is a logical one. Since the least significant bit of Z is one, the adder 16 sums the addends and supplies the resulting augend (101) to register 18, where it is stored.
  • controller 20 directs the shifter to supply to the adder a version of Z that has been shifted by one bit such that a zero is added to its least significant end.
  • the shifted version of Z is supplied as an addend is 1010.
  • the controller 20 directs selector 14 to select the middle bit of Z as a control input for adder 16.
  • the other addend supplied to adder 16 is the contents of register 18.
  • the control signal supplied by selector 14 is zero and so the addition is not performed and the contents of register 18 are not updated. Thus, the contents of register 18 remain as 101.
  • the controller 20 directs the shifter 12 to output a version of Z that has been shifted by two bits such that two zeros have been appended to its least significant end.
  • the shifted version of Z now presented to adder 16 is 10100.
  • the controller 20 controls the selector 14 to select the most significant bit of Z as a control input for adder 16.
  • the other addend supplied to adder 16 is the content of register 18, which is 101.
  • the control signal from selector 14 is 1 so the adder 16 sums its addends and updates register 18 with its augend, which is 11001, i.e. decimal 25.
  • the contents of register 18 represent Z 2 , there are no more bits of the operand for selector 14 to process, and the squaring operation is complete.
  • Z is a binary number
  • Z 2 is the square of Z.
  • P is the number of bits in Z.
  • Z m is a version of Z shifted by appending m zeroes to its least significant end.
  • the number of stages in the summation process is equal to the number of bits, P, in the binary word Z.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

Le circuit (10) d'élévation au carré d'un chiffre, Z, comprend un déphaseur (12) qui génère des versions déphasées de Z. Chaque version déphasée de Z est accumulée dans un registre de résultats dans le cas où un bit de Z correspondant à une version déphasée particulière de Z est fixé à un.
PCT/GB2001/005278 2000-12-05 2001-11-29 Circuit d'elevation au carre avec dephaseur et additionneur selectionnable WO2002046911A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002219317A AU2002219317A1 (en) 2000-12-05 2001-11-29 Binary squarer with shifter and selectable adder

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0029616.0 2000-12-05
GB0029616A GB2369901A (en) 2000-12-05 2000-12-05 A circuit for squaring a number using a shifter and selective addition

Publications (1)

Publication Number Publication Date
WO2002046911A1 true WO2002046911A1 (fr) 2002-06-13

Family

ID=9904462

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2001/005278 WO2002046911A1 (fr) 2000-12-05 2001-11-29 Circuit d'elevation au carre avec dephaseur et additionneur selectionnable

Country Status (3)

Country Link
AU (1) AU2002219317A1 (fr)
GB (1) GB2369901A (fr)
WO (1) WO2002046911A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4266923B2 (ja) 2004-12-27 2009-05-27 埼玉日本電気株式会社 フラットパネルスピーカ実装方法、電子機器の組立方法、ガスケット部材、振動板及びフラットパネルスピーカ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0278529A2 (fr) * 1987-02-13 1988-08-17 Nec Corporation Circuit de multiplication capable d'opérer à haute vitesse avec peu de matériel

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0278529A2 (fr) * 1987-02-13 1988-08-17 Nec Corporation Circuit de multiplication capable d'opérer à haute vitesse avec peu de matériel

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BEHROOZ PARHAMI: "Computer Arithmetic: Algorithms and Hardware Designs", 1999, OXFORD UNIVERSITY PRESS, NEW YORK, XP002189675 *
U. TIETZE CH. SCHENK: "Halbleiter-Schaltungstechnik", 1980, SPRINGER-VERLAG, NEW YORK, XP002189674 *

Also Published As

Publication number Publication date
GB2369901A8 (en) 2002-06-24
GB2369901A (en) 2002-06-12
AU2002219317A1 (en) 2002-06-18
GB0029616D0 (en) 2001-01-17

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