WO2002046887A3 - Processeur a fonctionnement multitache - Google Patents

Processeur a fonctionnement multitache Download PDF

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Publication number
WO2002046887A3
WO2002046887A3 PCT/US2001/051065 US0151065W WO0246887A3 WO 2002046887 A3 WO2002046887 A3 WO 2002046887A3 US 0151065 W US0151065 W US 0151065W WO 0246887 A3 WO0246887 A3 WO 0246887A3
Authority
WO
WIPO (PCT)
Prior art keywords
instructions
tasks
instruction
execution
concurrent
Prior art date
Application number
PCT/US2001/051065
Other languages
English (en)
Other versions
WO2002046887A2 (fr
Inventor
James E Howard
Original Assignee
Xyron Corp
James E Howard
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xyron Corp, James E Howard filed Critical Xyron Corp
Priority to AU2002241767A priority Critical patent/AU2002241767A1/en
Publication of WO2002046887A2 publication Critical patent/WO2002046887A2/fr
Publication of WO2002046887A3 publication Critical patent/WO2002046887A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne un processeur à fonctionnement multitâche destiné à un système d'exploitation en temps réel (RTOS) comprenant plusieurs unités d'exécution permettant d'exécuter simultanément plusieurs tâches et un sélecteur de tâches destiné à comparer des priorités de la pluralité de tâches et à sélectionner au moins une tâche prioritaire devant être exécutée. Un dispositif d'extraction d'instructions extrait des instructions destinées aux tâches choisies par le sélecteur de tâches et stocke les instructions relatives à chaque tâche dans au moins une file d'attente d'instructions. Une unité d'acheminement d'instructions attache des étiquettes de priorité aux instructions et envoie des instructions à partir des files d'attente d'instructions vers plusieurs unités d'exécution aux fins d'exécution.
PCT/US2001/051065 2000-10-23 2001-10-19 Processeur a fonctionnement multitache WO2002046887A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002241767A AU2002241767A1 (en) 2000-10-23 2001-10-19 Concurrent-multitasking processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US24258100P 2000-10-23 2000-10-23
US60/242,581 2000-10-23

Publications (2)

Publication Number Publication Date
WO2002046887A2 WO2002046887A2 (fr) 2002-06-13
WO2002046887A3 true WO2002046887A3 (fr) 2002-08-01

Family

ID=22915365

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/051065 WO2002046887A2 (fr) 2000-10-23 2001-10-19 Processeur a fonctionnement multitache

Country Status (2)

Country Link
AU (1) AU2002241767A1 (fr)
WO (1) WO2002046887A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8533716B2 (en) 2004-03-31 2013-09-10 Synopsys, Inc. Resource management in a multicore architecture
US9038070B2 (en) 2004-09-14 2015-05-19 Synopsys, Inc. Debug in a multicore architecture
CN101165655A (zh) * 2006-10-20 2008-04-23 国际商业机器公司 多处理器计算系统及其任务分配方法
US20080276073A1 (en) * 2007-05-02 2008-11-06 Analog Devices, Inc. Apparatus for and method of distributing instructions
WO2016186602A1 (fr) * 2015-05-15 2016-11-24 Hewlett Packard Enterprise Development Lp Priorisation de suppression
CN106095554B (zh) * 2016-06-17 2019-08-23 中国银行股份有限公司 在日间联机阶段进行批量数据处理的方法及装置
US10613987B2 (en) 2016-09-23 2020-04-07 Apple Inc. Operand cache coherence for SIMD processor supporting predication
CN110858127B (zh) * 2018-08-22 2023-09-12 慧荣科技股份有限公司 数据存储装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546593A (en) * 1992-05-18 1996-08-13 Matsushita Electric Industrial Co., Ltd. Multistream instruction processor able to reduce interlocks by having a wait state for an instruction stream
US6073159A (en) * 1996-12-31 2000-06-06 Compaq Computer Corporation Thread properties attribute vector based thread selection in multithreading processor
US6105127A (en) * 1996-08-27 2000-08-15 Matsushita Electric Industrial Co., Ltd. Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream
US6212544B1 (en) * 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
EP1148414A2 (fr) * 2000-03-30 2001-10-24 Agere Systems Guardian Corporation Méthode et appareil pour l'affectation d'unités fonctionnelles dans un processeur VLIW multifilière
US20010056456A1 (en) * 1997-07-08 2001-12-27 Erik Cota-Robles Priority based simultaneous multi-threading

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546593A (en) * 1992-05-18 1996-08-13 Matsushita Electric Industrial Co., Ltd. Multistream instruction processor able to reduce interlocks by having a wait state for an instruction stream
US6105127A (en) * 1996-08-27 2000-08-15 Matsushita Electric Industrial Co., Ltd. Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream
US6073159A (en) * 1996-12-31 2000-06-06 Compaq Computer Corporation Thread properties attribute vector based thread selection in multithreading processor
US20010056456A1 (en) * 1997-07-08 2001-12-27 Erik Cota-Robles Priority based simultaneous multi-threading
US6212544B1 (en) * 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
EP1148414A2 (fr) * 2000-03-30 2001-10-24 Agere Systems Guardian Corporation Méthode et appareil pour l'affectation d'unités fonctionnelles dans un processeur VLIW multifilière

Also Published As

Publication number Publication date
AU2002241767A1 (en) 2002-06-18
WO2002046887A2 (fr) 2002-06-13

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