WO2002035584A1

WO2002035584A1 - Method for processing a wafer of integrated circuits

Info

Publication number: WO2002035584A1
Application number: PCT/IB2001/001990
Authority: WO
Inventors: Olivier Zaleski
Original assignee: Schlumberger Systemes; Schlumberger Malco, Inc.
Priority date: 2000-10-24
Filing date: 2001-10-24
Publication date: 2002-05-02
Also published as: FR2815771A1

Abstract

A wafer (2) comprising a plurality of integrated circuits (1) is processed. In an identification step, a defective integrated circuit (1) is identified. In an engraving step, a symbol (11) is engraved on the defective integrated circuit. This allows greater detection reliability with regard to a marking by means of an ink drop.

Description

Method for processing a wafer of integrated circuits

FIELD OF THE INVENTION

The invention concerns a method for processing a wafer of integrated circuits. The integrated circuits may be used in, for example, integrated circuit cards, like bankcards, telephone cards, access cards, etc.

BACKGROUND OF THE INVENTION

Manufacturers of integrated circuit cards generally process slices of integrated circuits called wafers containing several thousand integrated circuits. These integrated circuits are subject to electrical tests so as to verify if there are any defective integrated circuits. The integrated circuits detected as defective, are marked by depositing a drop of ink. A wafer is cut by the card manufacturer in order to separate the integrated circuits. Only those not marked will be embedded in card bodies. Unmarked integrated circuits are selected automatically using an optical recognition device identifying the unmarked and marked integrated circuits.

SuTXEMΑRY OF THE INVENTION

It is an object of the invention to process a wafer of integrated circuits in a more reliable fashion.

According to an aspect of the invention, a method for processing a wafer comprising a plurality of integrated circuits comprises an identification step in which a defective integrated circuit is identified, and an engraving step in which a symbol is engraved on the defective integrated circuit.

The invention takes the followings aspects into consideration. Depositing an ink drop as effected in the prior art has several disadvantages. By depositing an ink drop, the volume of the drop must namely be sufficient for it to be detected by the optical recognition device. It is in fact difficult to constantly obtain drops of accurate volume, leading to the risk that the volume of the drop is insufficient. Furthermore, the contrast between the integrated circuits and the ink drop deposited must be relatively high to ensure reliable detection. In addition, when depositing the ink drop it is essential that the integrated circuits next to the defective integrated circuit are not splashed, to limit the risk that a good integrated circuit should be detected as defective by the optical recognition device. Another disadvantage lies in the relatively long drying time of the ink, which implies either increasing the duration of the method for processing a wafer of integrated circuits or providing special drying equipment, making the marking installation more costly.

In the invention, instead of using ink, marks are engraved on the integrated circuits. The marks are thus made without addition of material. This type of symbol allows a more reliable detection.

It is noted that the European patent application EP 0 877 413 concerns a method and apparatus that marks a wafer by means of engraving. But this document does not suggest marking defective integrated circuits individually.

Advantageously, the method for processing a wafer of integrated circuits includes a step of cutting the wafer of integrated circuits, this cutting step being carried out by the same tool which effects the engraving step.

The wafer of integrated circuits need therefore be positioned only once for the marking and cutting operations. ^'This allows to reduce the number operations carried out on the wafer. Consequently, there is less risk of damaging the wafer of integrated circuits (breakage, scratches, pollution, etc.). These and other aspects of the invention will be described in greater detail hereinafter with reference to drawings .

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a ''diagrammatic cross-section of a wafer of integrated circuits while marking one of the integrated circuits, Figure 2 is similar to figure 1, marking one of the integrated circuits and cutting the wafer being carried out simultaneously.

DETAILED DESCRIPTION

The figures illustrate a method for processing a wafer of integrated circuits in accordance with the invention. At least one defective integrated circuit 1 on a wafer 2 of integrated circuits 1 is marked. Subsequently the wafer 2 is cut to separate the integrated circuits 1.

Preferably, each of the integrated circuits undergoes electrical tests . A plan of the wafer 2 of integrated circuits 1 is created on computer on the basis of the results of these tests. The plan indicates the positions of the defective integrated circuits 1 and the good integrated circuits 1. The positions are determined with respect to "reference" integrated circuits whose positions in the wafer 2 of integrated circuits 1 is known and which can be identified visually. After these steps, the wafer 2 of integrated circuits 1 is attached in a precise way on a support film 3 and surrounded by a metal ring 4 in order to simplify the handling of the wafer 2. This assembly is then fed into a marking and cutting machine. In reference to figure 1, the marking and cutting machine includes a table 5 , a marking tool 6 and a cutting tool 7 which are mounted above the table 5 on a frame not shown so that they can be moved with respect to the table 5.

The marking tool 6 is in this case a device emitting a laser beam 8 whose power can be adjusted to engrave the top surface 9 of the integrated circuit 1.

The cutting 'tool 7 is in this case a device emitting a laser beam 10 whose power can be adjusted to cut through the thickness of the wafer 2 without attacking the support film 3.

The wafer 2 / support film 3 / ring 4 assembly is positioned and attached on the table 5. The positioning of the wafer of integrated circuits 2 on the table 5 is carried out with respect to the positions of the reference integrated circuits.

The defective integrated circuits 1 can then be identified using the plan of the wafer 2 of integrated circuits 1.

The marking tool 6 is then successively positioned above each defective integrated circuit 1 and emits the laser beam 8 on the top surface 9 to engrave a symbol 11 on it.

The marking tool 6 is in this case also used to engrave information 12 on the top surface of the metal ring 4. This information may be logistics information, possibly an alphanumeric code or a bar code.

After the passage of the marking tool 6, the wafer

2 of integrated circuits 1 is cut with the cutting tool 7.

During this cutting operation, the support film 3 remains intact, holding the separated integrated circuits in position.

The marking and cutting operations can be carried out simultaneously or successively. In addition, the tools 6 and 7 can be fastened to the same mobile carriage or independent carriages.

Figure 2 shows a variant of this system, where the marking and cutting machine has a marking and cutting tool in the form of a diamond-grinding wheel 13. The diamond- grinding wheel can be adjusted to provide a first cutting depth and a second cutting depth. In the first cutting depth, the grinding wheel simply scores the top surface 9 of an integrated circuit 1 and makes an engraving on it. In the second cutting depth, the grinding wheel cuts through the wafer 2 without attacking the support film 3.

The wafer 2 / support film 3 / ring 4 assembly is positioned and attached to the table 5 as previously.

To mark defective integrated circuits, tool 13 is adjusted to the first cutting depth.

The wafer 2 is then cut with tool 13 adjusted to the second cutting depth. The engraving and cutting are therefore carried out on the same station using the same tool . The tool used can also be a laser beam emission device equipped with means to adjust the power of the laser beam to a first power level suitable for engraving the surface of an integrated circuit and a second power level to cut through the thickness of wafer 2.

The invention is of course not limited to the method described and variants can be made without leaving the scope of the invention as defined by the claims . In particular, the method for processing a wafer of integrated circuits of the invention also applies to wafers of integrated circuits, which have an active side over which there is a silicon protective layer. The marking by engraving is then carried out on the topside of this protective layer. In this manufacturing process, the wafer is thinned after marking by, for example etching the back of the wafer. Marking by engraving offers the advantage, unlike ink drop marking, that it does not result in excess thickness on the surface of the protective layer, which can therefore be used as support surface when etching the back of the wafer. In addition, as regards the process implemented with a marking tool and a cutting tool, the tools can be identical (two diamond grinding wheels for example) or different (a diamond grinding wheel and a laser beam) .

Furthermore, the process can be used to mark other parts of the wafer (e.g. its back) or the support film 3.

The term "engraving" should be understood so that it comprises any type of local deformation.

Claims

1. A method for processing a wafer comprising a plurality of integrated circuits, the method comprising an identification step in which a defective integrated circuit is identified, characterized in that the method comprises an engraving step in which a symbol is engraved on the defective integrated circuit.

2. The method according to claim 1, characterized in that the engraving is carried out with a diamond grinding wheel .

3. The method according to claim 1, characterized in that the engraving is carried out with a laser beam.

4. The method according to claim 1, characterized in that the method comprises a cutting step in which the wafer is cut by a tool which also effects the engraving step.

5. The method according to claim 1, characterized in that, the wafer of integrated circuits is fastened to a support, the method includes an additional step of etching a symbol on the support .

6. The method according to claim 1, characterized in that the identification step comprises the following sub-steps :

- a test step in which an electrical test is carried out on an integrated circuit so as to verify whether the integrated circuit is defective or not; and

- a plan creation step in which a plan, indicating the position of a defective integrated circuit, is created.

7. A method for manufacturing an integrated circuit card comprising on the basis of a wafer comprising a plurality of integrated circuits, the method comprising:

- an identification step in which a defective integrated circuit is identified; - an engraving step in which a symbol is engraved on the defective integrated circuit;

- a cutting step in which the wafer is cut by a tool which also effects the engraving step; and

- an embedding step in which a non-engraved integrated circuits is embedded in a card body.

8. A wafer comprising a plurality of integrated circuits characterized in that a defective integrated circuit has an identifiable symbol, said symbol being engraved on the defective integrated circuit.