WO2002029824A3 - System and method for testing integrated circuit devices - Google Patents

System and method for testing integrated circuit devices Download PDF

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Publication number
WO2002029824A3
WO2002029824A3 PCT/CA2001/001365 CA0101365W WO0229824A3 WO 2002029824 A3 WO2002029824 A3 WO 2002029824A3 CA 0101365 W CA0101365 W CA 0101365W WO 0229824 A3 WO0229824 A3 WO 0229824A3
Authority
WO
WIPO (PCT)
Prior art keywords
under test
device under
integrated circuit
testing
circuit devices
Prior art date
Application number
PCT/CA2001/001365
Other languages
French (fr)
Other versions
WO2002029824A2 (en
Inventor
Bosco Lai
Original Assignee
Concord Idea Corp
Bosco Lai
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Concord Idea Corp, Bosco Lai filed Critical Concord Idea Corp
Priority to JP2002533313A priority Critical patent/JP2004510171A/en
Priority to GB0304664A priority patent/GB2382663A/en
Priority to AU2001293574A priority patent/AU2001293574A1/en
Priority to CA002419939A priority patent/CA2419939A1/en
Publication of WO2002029824A2 publication Critical patent/WO2002029824A2/en
Publication of WO2002029824A3 publication Critical patent/WO2002029824A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

The invention disclosed herein is a system and method for testing integrated circuit devices, including memory chips. The devices under test are subject to behavioural testing, in which a copy of signals in an application system is directed to the device under test, or to an electronic component connected to the device under test. This permits the device under test to be tested under the operating conditions of the application system, which is preferably similar to the actual application environment in which the device under test will ultimately be used. Conventional tests, including pattern testing and/or parametric tests, may also be performed on devices under test, if desired.
PCT/CA2001/001365 2000-10-03 2001-09-26 System and method for testing integrated circuit devices WO2002029824A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2002533313A JP2004510171A (en) 2000-10-03 2001-09-26 System and method for testing integrated circuit devices
GB0304664A GB2382663A (en) 2000-10-03 2001-09-26 System and method for testing integrated circuit devices
AU2001293574A AU2001293574A1 (en) 2000-10-03 2001-09-26 System and method for testing integrated circuit devices
CA002419939A CA2419939A1 (en) 2000-10-03 2001-09-26 System and method for testing integrated circuit devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67839700A 2000-10-03 2000-10-03
US09/678,397 2000-10-03

Publications (2)

Publication Number Publication Date
WO2002029824A2 WO2002029824A2 (en) 2002-04-11
WO2002029824A3 true WO2002029824A3 (en) 2003-05-01

Family

ID=24722608

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2001/001365 WO2002029824A2 (en) 2000-10-03 2001-09-26 System and method for testing integrated circuit devices

Country Status (6)

Country Link
JP (1) JP2004510171A (en)
AU (1) AU2001293574A1 (en)
CA (1) CA2419939A1 (en)
GB (1) GB2382663A (en)
TW (1) TW580578B (en)
WO (1) WO2002029824A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9117552B2 (en) 2012-08-28 2015-08-25 Kingtiger Technology(Canada), Inc. Systems and methods for testing memory
US9224500B2 (en) 2011-11-29 2015-12-29 Kingtiger Technology (Canada) Inc. Systems and methods for testing and assembling memory modules

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW548414B (en) 2002-01-29 2003-08-21 Via Tech Inc Automatic integrated circuit overall machine testing system, apparatus and its method
US8079015B2 (en) 2002-02-15 2011-12-13 Telefonaktiebolaget L M Ericsson (Publ) Layered architecture for mobile terminals
US7536181B2 (en) 2002-02-15 2009-05-19 Telefonaktiebolaget L M Ericsson (Publ) Platform system for mobile terminals
US7363033B2 (en) 2002-02-15 2008-04-22 Telefonaktiebolaget Lm Ericsson (Publ) Method of and system for testing equipment during manufacturing
US7415270B2 (en) 2002-02-15 2008-08-19 Telefonaktiebolaget L M Ericsson (Publ) Middleware services layer for platform system for mobile terminals
TW567329B (en) * 2002-07-30 2003-12-21 Via Tech Inc Auto system-level test apparatus and method
US7350211B2 (en) 2002-09-23 2008-03-25 Telefonaktiebolaget Lm Ericsson (Publ) Middleware application environment
US7149510B2 (en) 2002-09-23 2006-12-12 Telefonaktiebolaget Lm Ericsson (Publ) Security access manager in middleware
US7478395B2 (en) 2002-09-23 2009-01-13 Telefonaktiebolaget L M Ericsson (Publ) Middleware application message/event model
EP1574868B1 (en) * 2003-02-13 2007-10-17 Matsushita Electric Industrial Co., Ltd. Assembly for LSI test and method for the test
DE102004021267B4 (en) * 2004-04-30 2008-04-17 Infineon Technologies Ag Method for testing a memory module and test arrangement
US20070058456A1 (en) * 2005-09-09 2007-03-15 Rico Srowik Integrated circuit arrangement
US7539912B2 (en) 2005-12-15 2009-05-26 King Tiger Technology, Inc. Method and apparatus for testing a fully buffered memory module
TWI395960B (en) * 2006-11-27 2013-05-11 Hon Hai Prec Ind Co Ltd Device and method for testing data transfer rate
US7848899B2 (en) 2008-06-09 2010-12-07 Kingtiger Technology (Canada) Inc. Systems and methods for testing integrated circuit devices
JP5487770B2 (en) * 2009-07-21 2014-05-07 ソニー株式会社 Solid-state imaging device
US8356215B2 (en) 2010-01-19 2013-01-15 Kingtiger Technology (Canada) Inc. Testing apparatus and method for analyzing a memory module operating within an application system
US8918686B2 (en) 2010-08-18 2014-12-23 Kingtiger Technology (Canada) Inc. Determining data valid windows in a system and method for testing an integrated circuit device
US9003256B2 (en) 2011-09-06 2015-04-07 Kingtiger Technology (Canada) Inc. System and method for testing integrated circuits by determining the solid timing window
CN112363875B (en) * 2020-10-21 2023-04-07 海光信息技术股份有限公司 System defect detection method, device, electronic device and storage medium

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001818A (en) * 1975-10-22 1977-01-04 Storage Technology Corporation Digital circuit failure detector
US4484329A (en) * 1980-08-18 1984-11-20 Thalamus Electronics, Inc. Apparatus for the dynamic in-circuit element-to-element comparison testing of electronic digital circuit elements
US6055653A (en) * 1998-04-27 2000-04-25 Compaq Computer Corporation Method and apparatus for testing gang memory modules

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001818A (en) * 1975-10-22 1977-01-04 Storage Technology Corporation Digital circuit failure detector
US4484329A (en) * 1980-08-18 1984-11-20 Thalamus Electronics, Inc. Apparatus for the dynamic in-circuit element-to-element comparison testing of electronic digital circuit elements
US6055653A (en) * 1998-04-27 2000-04-25 Compaq Computer Corporation Method and apparatus for testing gang memory modules

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HERMANN A L: "DIAGNOSTIC DATA COMPARATOR", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 24, no. 5, 1 October 1981 (1981-10-01), pages 2591 - 2592, XP000713903, ISSN: 0018-8689 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9224500B2 (en) 2011-11-29 2015-12-29 Kingtiger Technology (Canada) Inc. Systems and methods for testing and assembling memory modules
US9117552B2 (en) 2012-08-28 2015-08-25 Kingtiger Technology(Canada), Inc. Systems and methods for testing memory

Also Published As

Publication number Publication date
GB2382663A (en) 2003-06-04
AU2001293574A1 (en) 2002-04-15
CA2419939A1 (en) 2002-04-11
WO2002029824A2 (en) 2002-04-11
GB0304664D0 (en) 2003-04-02
TW580578B (en) 2004-03-21
JP2004510171A (en) 2004-04-02

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