Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
  • G06F17/10—Complex mathematical operations
  • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
  • G06F17/10—Complex mathematical operations
  • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms

Definitions

• the present invention relates to the fields of digital signal processing. It introduces an improved method and apparatus for performing linear transformations, with reduced number of arithmetic operations, simplified circuitry, and low power consumption.
• Linear transformations are commonly used for signal or data processing.
• a linear transformation produce from an n-dimensional vector, considered as "input vector” an r-dimensional vector, considered as "output vector".
• the input vector consists of digital samples of a given signal that requires processing.
• applications of linear transformations are not restricted to any specific domain, they are essential to every field of science and technology and their efficient performance is highly desirable.
• a general linear transformation from the set of n-dimensional vectors (real, complex or from any field of scalars) to the set of r-dimensional vectors (over the same field of scalars), may be represented by a matrix of order rxn given by:
• Binary matrix are of special importance in the development and application of the present invention.
• Binary-bipolar matrix are those containing only ⁇ 1 values in their entries. Henceforth they would be called [ -matrix.
• a linear transformation represented by a [ -matrix will be called [/-transformation.
• Another type of binary matrix are those containing only 0,1 values in their entries. They would be called 0-1-matrix.
• a linear transformation represented by 0-1-matrix is called a 0-1 -transformation.
• _* ⁇ (/_ -l)/2 additions would be required, on average, for a straightforward performance of a 0-1 -transformation.
• binary transformation would consist of the two types of transformations mentioned above: [/-transformations and 0-1- transformations.
• the term [/-vector would refer to a vector having ⁇ 1 values in its components and likewise, a vector having 0,1 values in its components will be called a 0-1 -vector.
• the processing of binary transformations consist of adding and subtracting components of the input vector. They are implemented in hardware as an electronic Application Specific Integrated Circuit (ASIC), requiring elements such as adders and subtracters. The usage of these components is costly and energy consuming and their construction occupies a precious area. A hardware implementation of binary transformations with a low consumption of these resources is of increasing need in numerous fields of technology.
• PN Pseudo-random Noise
• TS-95-B second generation
• 3G third generation
• WB wide band
• Toplitz transformations which perform convolutions and are used as filters in DSP can be done efficiently by the use of the classical Fast Fourier Transform (FFT) algorithm requiring 0(n*log 2 (n)) addition and multiplication operations, where n is the dimension of the domain space.
• FFT Fast Fourier Transform
• straightforward methods require 0(n 2 ) addition and multiplication.
• a specific type of [/-transformation used in digital signal processing including CDMA technologies is the Walsh-Hadamard Transformation which is represented by a Hadamard matrix.
• a Hadamard matrix can be defined recursively as follows:
• the [ -transformation's aspect is modified by another feature of the invention to accommodate for an efficient method and apparatus for the performance of and toplitz [ -transformations.
• These transformations represents full or partial convolution with a given [/-sequence or a complex [/-sequence.
• Wireless communication applications of toplitz [ -transformations include initial time- synchronization and the searcher which use convolutions with a real or complex pseudo-random (PN) or gold, [/-sequences.
• PN pseudo-random
• a gold sequence is composed by the Z 2 sum of two PN sequences.
• Another aspect of the present invention is an efficient method and apparatus for these type of linear operations. It comprises modified versions of the [/-binary aspect of the invention with an additional processor. This additional processor uses information about the number of additions required by the said [ -binary method to discover a configuration that applies the [/-binary method in various subsections in global low rate of additions.
• Additional major applications of the invention include wireless multimedia systems personal satellite mobile systems, GPS satellite-based locating systems and more.
• wireless multimedia systems personal satellite mobile systems, GPS satellite-based locating systems and more.
• a reduction in current consumption used for linear processing is essential.
• Applications of the invention the in the mobile phone technologies can prolong the life of the battery, reduce circuitry and shorten response time.
• Fig. 1 schematically illustrates the operation of updating the contents of a memory employed by an apparatus which performs the transformation using the 0-1- binary transformation matrix, according to a preferred embodiment of the invention
• FIG. 2 schematically illustrates the operation of updating the contents of a memory employed by an apparatus which performs the transformation using the [/- transformation matrix, according to a preferred embodiment of the invention
• Fig. 3 schematically illustrates the operation of updating the contents of a memory employed by an apparatus which performs the transformation using the Toplitz transformation matrix, according to a preferred embodiment of the invention
• Fig. 4 is a block diagram of an exemplary apparatus for performing a linear transformation with a reduced number of additions, according to a preferred embodiment of the invention.
• Fig. 5 illustrates an example an implementation of a product of an rxn U-matrix A by an n-dimensional vector X according to one embodiment of the present invention.
• 0-1-MATRIX The present preferred embodiment of the invention provides an efficient method of performing a 0-1 -binary linear transformation. Henceforth it will be called also the "0-1 -method".
• the following example is an introduction to the 0-1 -method and an outline of its main ideas.
• the matrix A is first checked for equal lines. Since there are no two lines that are equal, the procedure goes to the next step.
• the output vector y is expressed as a sum of the columns with coefficients that are the respective input vector coordinates.
• the first step done by a preferred embodiment of the invention with respect to the input vector is to collect and sum coefficients of any recurring non-zero column.
• the following reduced vector equation is accomplished:
• the 0-1 -binary aspect of the invention is an efficient method and apparatus for the product of a binary 0-1-matrix A of dimensions rxn by an n- dimensional vector x.
• the matrix is given by:
• the entries of the input vector may be real or complex or belong to any field of scalars (such as Z 2 for example).
• the goal is to compute the result of the product of the matrix A by the vector x. This result will be denoted by:
• the first step is a check for equal raws. When possible this step should be done before any processing of input vectors begins, as a preliminary preparation. If it is found that the z-line is equal to they ' -line then it can be deducted that y is equal to yj. Therefore one of the two equal lines would be omitted. For the sake of clarity the line having larger index would always be the omitted one. Thus, if j > i then the /-line would be omitted.
• This initial operation is amended at the final step of the execution of the invention where yj which is known at this stage (since it is equal to yj) is inserted back to its appropriate place in the vector y. Omitting of equal lines continues until there are no two line in the matrix A that are equal. In practice this stage is skipped in many occasions. It is performed whenever there is a reasonable likelihood for equal lines. It is always performed when log 2 (r) > n since this condition ensures the existence of equal lines.
• the modified matrix resulting from this screening process will have the same name, A, as the original matrix, and the names of the dimensions rxn will also be preserved.
• A the name of the dimensions rxn will also be preserved.
• a summation process is introduced to eliminate equal columns. This procedure will reduce the number of columns in the modified matrix with a minimal cost in additions.
• Each element of this sum consists of a column vector of the matrix A, multiplied by the corresponding scalar coefficient of the vector x.
• zero columns, along with their coefficients are omitted at this stage.
• identical nonzero columns are grouped together and rearranged where each distinct column becomes a common factor, multiplied by the sum of its corresponding scalar coefficients.
• the resulting summation comprises the subsequence of all distinct nonzero columns
• Wi, ,w extracted from the original sequence of nonzero column by the omission of repeating columns.
• Each column Wj is multiplied by a coefficient tj which is a sum of the corresponding original coefficients of all columns that are equal to this column.
• m ⁇ n and the gap, n-m, is the number of repetitions in the original sequence v / , v . , , v n .
• the management aspect of this computation may be done once-per-matrix as a preliminary preparation before the arrival of input vectors.
• B be the rxm matrix whose columns are respectively wi, ,w m , and let:
• the next step is a horizontal split of the matrix B of the former stage to two or more sub-matrix, where lines are kept unbroken.
• Each sub-matrix will have a reduced number of rows and that will increase the gain of the above column-collection procedure in the next iteration.
• the lines of the matrix B would be denoted by: « / , .._•, , u r .
• the product under consideration may be then expressed by: u, -t where each line is multiplied in scalar product by the vector t.
• the two sub-matrix would have the same or almost the same number of lines.
• the split might be into more than two matrix.
• the two lower dimensional products, B]*t' and B 2 » t" would be computed separately and in the end the results, which are two r- vectors, are summed together.
• a preliminary rearrangement of the indexes of the --.-columns, Wi, ,w, convention, may enhance the effectiveness of this step.
• the vertical split would be used less frequently then the others procedures. Its main use is in the case that the number of rows substantially exceeds the number of columns, situation less common in DSP applications.
• the fundamental drawback of this step is in the need to sum up the results of the two products -3_ *t' and B *t" which consists of an additional set of r scalar additions which has no parallel in the above horizontal split.
• the vertical split might be into more than two matrix.
• the present invention increases management operations and reduces additions.
• additions are a major part of the complexity and their reduction by the use of the invention has a dominant effect.
• most of the management operations are done once per matrix before the processing of data vectors begins.
• the suggested method substantially saves power consumption and circuitry.
• the above 0- 1 -binary aspect may be particularly efficient when the given matrix has some degree of sparsity. This is often encountered when the application of this embodiment is combined with distributed arithmetic's in the computation of the product of a general real matrix by a vector as described in the real-matrix aspect of the invention.
• the matrix is given by:
• the first step in the process is to check for equivalent lines.
• line 4 is deleted from the matiix A.
• the resulting matrix A ' is given by:
• the [/-binary preferred embodiment of the invention is an efficient method for the product of a rxm [/-matrix J by an ⁇ -dimensional input vector x. It usually provides more gain than the 0-1- preferred embodiment and has more applications.
• the matrix A is given by: 7 for all l ⁇ i ⁇
• the entries of the input vector may be real or complex or belong to any field of scalars with characteristic larger then 2.
• the first step is a modification of the given matrix by the elimination of equivalent lines, a step which may be part of preliminary preparations. If it is found that the /-line is equivalent to the y-line then it can be deducted that yj is equal to
• a preferred embodiment of the first step of the invention determines that one of two equivalent lines would be omitted. For the sake of clarity the policy would be that the line having larger index would always be the omitted one. Thus, if it is supposed that j > i then the /-line would be omitted. This initial operation is reversed at the final step of the process where yj which is known at this stage is put back to its place in the vector y. This elimination process continues until there are no two line in the modified matrix that are equivalent.
• This stage is performed whenever there is a practical probability of equivalent lines. This is often the case in multi-product (another aspect of the present invention) applications of the [ -method. This stage is always performed when log 2 (r) > n since this condition ensures the existence of equivalent lines. However there are other conditions that ensures the existence of equivalent lines and should be taken into consideration. This for example, may be the case in sub-matrix of the Hadamard matrix. To avoid clumsy notation, the resulting modified matrix will have the same name, A, as the original matrix, and the names of the dimensions rxn will also be preserved.
• the next step is the elimination of equivalent columns. This will reduce the horizontal dimension (i.e the number of columns) of the modified matiix with minimal cost in additions. All the management related to this step is made, as in the 0-1 -aspect, one time per each matrix usually as preliminary preparation prior to the arrival of data vectors.
• the resulting summation comprises the subsequence of all distinct normalized column vectors Wi, ,w m (having no repetitions) extracted from the sequence of normalized column vectors by screening out repeating normalized columns.
• Each distinct normalized column wj is multiplied by a coefficient t j which is a sum of the corresponding normalized coefficients of all normalized columns that are equal to this column.
• the main computational task involved in this part of the invention is this calculation of the new coefficients t ? , ,t m as sums of the normalized original ones.
• the cost in additions is n-m.
• the product A*x is thus given by:
• the gain by the columns elimination process depends on the structure of the original matiix A. It is significant in some of the matrix that are commonly used in coding and decoding signal vectors in wireless communication, such as certain types of submatrix of the Hadamard or the cyclic PN matrix. It is substantial also when r, the number of lines in the matrix A, is small relative to the number of rows n. In particular when r
• additions are the main part of the complexity.
• s(n , r) n + s(r)
• One such technology is image processing which encompass several procedures which include the product of a [ -matrix by a vector.
• image processing which encompass several procedures which include the product of a [ -matrix by a vector.
• IS-95 and in the more advanced third generation wide band CDMA there are several processes which employ the product of a [ -matrix by a vector. These processes will be done with less energy consumption, circuitry and sometimes also running time by the use of the invention.
• 8 lines of from the Hadamard-64 comprise a [/-matrix which is multiplied by a vector whose entries are samples of a signal.
• Another application is in neighbor detection which done by a despreader.
• a product of a matiix composed of few Hadamard lines by a data vector.
• Another application is the searcher. It searches for high correlation of sequences by the computation of their mutual scalar product.
• the correlator sequences are extracted from pseudo random (PN) sequences, which are [/-sequences, and their scalar products by a data vector is the required computation.
• PN pseudo random
• each of the columns Vk + i, , v n (for some 2 ⁇ k ⁇ n) is a scalar product of the k- column, that is for k ⁇ j ⁇ n: V j -Z j V k -
• the n-dimensional vector x is replaced by the reduced / -dimensional vector: x'—(x ⁇ , 2, Xk-i ,x'i ⁇ ) where x — x +
• this process including, if necessary a change of indexes, is repeated until no two columns are equivalent. Indeed this is process is simply a generalization of the process of normalization taken place in the [/-matrix embodiment of the invention. In practice all the above equivalent-columns reductions may be done simultaneously. When this stage is done it would be considered a first iteration of the whole process. Then the matiix is split horizontally and in each split the above column elimination repeats in a recursive manner as was done in the above embodiments.
• this preferred embodiment of the invention enhances the efficiency, consider a matrix having its entries in a relatively small finite set S.
• the gain decreases with the size of S and the general rule holds that the GEM reduces the number of additions by a factor of log ⁇ s ⁇ (n), where n is the number of columns in the given tiansformation matiix.
• GEM should also be compared for efficiency with the complex and general embodiments that will later be described.
• the first step is a check for equivalent lines. No equivalent lines are found.
• the product A*x is decomposed to a sum of the -4-columns multiplied by the respective x-components.
• the coefficients: Wi, ,ws are known to the processor at this stage.
• Xp y 3 1 » X 3 + 1*X 4 + (-1)'X 5 +(-l) # X ⁇ +1 » X7 + (-l)*X 5 +l'Xp + (-1) «
• the next step is to gather complementing vectors, thus: +
• xi - (Xi +Xp( )+ -(xi -x 9 ) ⁇
• the elements of the data sequence may be real or complex or belong to any field of scalars of characteristic larger than 2.
• yi U]»x ⁇ + u 2 » x 2 + + u n » x
• y 2 U ⁇ 'X 2 + U ' X 3 + + ucut » x conveyor + ⁇
• a preferred embodiment of the invention would start by dividing the set of m sums to blocks of r consecutive sums where r ⁇ log 2 (n). All the blocks are treated in an identical way so the method may be demonstrated on the first block.
• the first r sums can be represented by a product of toplitz matiix by a vector.
• Vn+r-1 are [/-vectors. Thus the rest of the computation may be done by the [/-method. All the aspects of this modification to [/-form, except for the actual summations/subtractions: xj + ⁇ n+J , are done as a "one time job" prior to the arrival of the input vectors.
• Toplitz matrix is part of a more general class of matrix: those matrix whose entries are 0, 1 or -1. Such matrix would be called in here (0,l,-l)-matrix.
• A is (0,l,-l)-matrix of dimensions rxn and x is an r ⁇ -dimensional input vector and it is desired to compute the product: A*x.
• This product may be expressed as a sum of the A -columns multiplied by the corresponding x-component.
• v,- for every j be they column of J, then:
• V j , — ( j + wj).
• a preferred embodiment of the invention finds the vectors ui,
• the number of computational operations may be reduced for any real linear transformation by the use of distributed arithmetic's.
• the linear transformation is represented by a matrix whose entries are real numbers, not necessarily integers, having a fixed number of binary digits.
• the matiix will be decomposed to a sum of binary matrix with binary coefficients.
• the binary embodiments of the invention will be applied. To introduce this method consider the following example.
• the input, 8- dimensional vector is given by:
• A 101 000 100 001 100 111 001 010 010 111 011 001 100 101 000 011
• the first step taken by this embodiment of the invention is the construction of the binary matrix A[0J, AflJ, A[2] comprising the bits of the entries of A according to their significance.
• the preferred embodiment under consideration will be a consequence of the equality:
• A'x D'AfOJ'x + U l 'A[l] 'x + D ⁇ ⁇ [2J V
• the preferred embodiment of the invention under consideration relates to an efficient computation of a real, unrestricted, linear tiansformation.
• the rxm matiix A representing the transformation is written by: where the entries of the matrix are real numbers. It is desired to compute A*x where x is an /.-dimensional vector of real or complex scalar entries written by:
• AfmJ is the 0-1-matrix of the most significant bits (MSB)
• Af-m 2 J is the 0-1-matrix of the least significant bits (LSB).
• each of the matrix AfkJ is a 0- 1 -matrix whose entries are comprised of the k's-significant-bits of the entries of A, where each bit is placed in its corresponding entry.
• A'x D _ m2 ⁇ k ⁇ m ⁇ 2 k ⁇ fkJ*x.
• A* be the rx(m*n) 0-1-matrix composed by the horizontal lining of the binary matrix of the above sum in the order they appear in the sum.
• A* [A[-m 2 ], ⁇ fOJ .Afmj jJ
• J*x J*»x*
• the latter is a product of a rx(m*n) 0-1-matrix by a (m+l) » n-dimensional vector which is composed of shifted m replicas of the original vector.
• the computation of the product A* » x* is done with the 0-1 -binary-embodiment of invention. Since each multiplication by an integer power of 2 may be implemented by shifting the bits, very little additional complexity is added.
• This embodiment of the invention may reduce significantly the complexity of the product.
• J***x is done by the preferred embodiment of the invention for 0-1-matrix.
• the product _4** « x contains all the products: Af- m 2 J*x, ,AfOJ'x, ,AfmjJ » x.
• y U_ m2 ⁇ k ⁇ nJ ⁇ 2 ⁇ AfkJ'x
• A[-m +lJ, > AfOJ, ,AfmjJ are rather sparse. This may a consequence of the A -entries being of various sizes and having non-uniform number of binary digits beyond the point. In such cases the zero padding necessary for the above mentioned uniform digital format causes a higher level of sparsity.
• Another form of the preferred embodiment of the invention, based on [ -binary distributed arithmetic's, will be described by the next text. This form of the invention has the advantage of being more adaptive to matrix having entries of both signs and of being based on the faster [ -method. In practice it is more efficient then the above 0-1- version when there is some uniformity in size and accuracy of the entries of the matrix.
• A . m2 . 1 ⁇ k ⁇ mrl 2k-AfkJ+ (2 m X T ⁇ -j-Afm ⁇ .
• each of the matrix AfkJ is a rxn [-matrix.
• This matiix is composed as a one time task per each matrix before the arrival of incoming data vectors.
• A*x A*»x*
• This is a product of a rx((m+l)m) [ -matrix by a ( +i Erasmus.-dimensional vector. The computation of this product is done by application of the [/-matrix embodiment of the invention.
• C(A) is defined to be the number of additions required by the above [/-embodiment to compute A » x. In greater generality, it holds that:
• Linear transformations are commonly used in every fields of technology and science.
• Applications of the real matiix aspect of the invention in communication technology include products of multi-user detector (MUD) matiix (such as decorrelators or minimum mean square error (MMSE) matrix) by a output vector of a despreader. It is also applicable in the calculations of least squares.
• FIR Finite Impulse Response
• DFT Discrete Fourier Transform
• Discrete cosine transform DCT is another type of linear transformation whose computation may be improved by the invention. This is so especially when it is only partially calculated or when its size is not too large so that higher dimension fast algorithms are not very efficient.
• One of the vectors may represent taps of a FIR filter which operates on a second vector, representing an input that should be filtered.
• Filtering operation consisting of partial convolution is represented by the product of a Toplits matrix by a vector. This is done efficiently by the real matrix aspect of the invention.
• these sums are computed in by the GEM. Due to the small sizes of this example the gain is marginal in this case compared to the conventional way, but it is substantial in larger dimensions. When the dimensions are small, as in this example, other more conventional methods of computation may also be applied after the phase rotation step. Finally the result of each sum is multiplied by (1-j) to obtain the desired result. Note that multiplication by j or (-1) are "organizational" operations requiring modest amount of time and energy. The second option of preferred embodiment is called the complex- [/-method.
• B is an rxn [ -matrix and z-B*x.
• the product z -B » x is computed of by the GEM.
• z-B*x is computed by application of the GEM, or perhaps, when the dimension is low, by more conventional methods.
• IS-95 Searcher The IS-95 CDMA system allows a number of different base stations in a small geographic location to simultaneously use the same segment of spectrum for transmitting data to mobile receivers.
• the manner in which the data from different bases can be differentiated is by way of the PN sequence which is used to spread the transmitted data. Each base transmits at a different phase of the PN sequence.
• the task of the searcher mechanism in the mobile receiver is to identify the different pilot signals transmitted by the surrounding bases by aligning with their PN phase. It is also applied to differentiate between several multipath signals (meaning echoes) arriving from the same base. A similar process is applied in the initial synchronization procedure.
• a searcher is required to test a number of hypotheses, by partial correlation of the received signal, for each hypothesis, with a locally generated PN sequence. The sequence is then shifted for each hypothesis, and the correlation is performed for a fix number of signal elements (chips). Normally the searcher is required to search all the hypotheses in a given window where at each time the sequence is shifted by 1.
• Another preferred embodiment of the invention relates to a situation where partial sums of the [/-matrix by vector product are desired. This may occur in CDMA communication applications when several codes with different rates (spreading factors) are tested simultaneously. Studying this embodiment is more fruitful for readers who have already accomplished substantial command of the previous aspects of the invention. It will be introduced by the following example which gives first idea of this rather involved method without the abundance of details. However no example of reasonable size can describe all the aspects of this embodiment. The reader may also referred to the summery of the invention, item 6. Example: Consider the following 5x8 [/-matrix:
• the spreading factor of lines 1 and 2 is 2 and the spreading factor of lines 3 and 4 is 4 and the spreading factor of line 5 is 8.
• the spreading factor is non decreasing, that is the spreading factor of each lines is equal or more to the spreading factor of the previous line. This terminology will later be precisely defined. It is implied by the above that the following sums should be computed: Xj + X 2 , -Xj + X 4 , X - X,j , -X ⁇ - X ⁇
• the environment of current aspect of the invention includes a [/-matrix that might be of large dimensions where at each line sub-sums of equal intervals are required as in the above example.
• the input vector is real or complex.
• the matrix may be sub- divided by lines to several sub-matrix wherein each of them is computed by the method used in the above example separately and independently.
• a method is integrated that finds near-best subdivision in term of saving additions and hence reducing complexity.
• the tool for it is an additional processor or apparatus based on dynamic programming, which analyze the various subdivisions by the use of the table, bound and regressive formula of the complexity, s(n,r), of the U- method. Very precise formulation is required for the development of this embodiment. Several new definitions will be needed as preliminary material.
• v (v j ,v 2 , ,V be a vector andp a positive integer that divides n (in short: p ⁇ n).
• v[p] to be the vector of vectors that is formed by subdividing v to sections of lengfh ⁇
• J ((vi, V 2> > ' ( v p+l> v p+2> > v 2p)> >( v n - p +b v n - p +
• multi- vector is a structure akin to the structure of a matrix.
• multi-scalar-product of multi- vectors is a cross between matrix product and the usual scalar product.
• vw[p] (v[p, IJ'wfp, 1], v[p, 2]'w[p, 2J, ,v[p, n/pj'w[p, n/pj) where the internal products: v[p,lj'w[p,l v[p,2J*w[p,2J are usual scalar products. Note that the result of this product is a n/p-dimensional vector.
• A'xfpJ (Aj'x[pjJ, A 2 'x[pJ, ,A r 'x[p r ])
• the current embodiment of the invention will improve the computation of such products in a setup that will be described henceforth.
• z stored as a table
• the M-l -method is by no mean efficient when r is large relative to p j . It is largely a stepping stone for a smarter method will be developed on its foundations. This stronger method works by horizontally subdividing the matrix and applying the M-l -method to each sub-matrix separately. To find with fewer calculations a subdivision structure bearing a smaller total number of additions it will be useful to have the following shorter version of the above formula. So define:
• r is a tool to create a subdivision of/? to a vector of vectors p[r], in the following manner:
• p[r, 1] (p r(1 ), ,Pr(2)-l)
• p[r, 2] (p r(2) , ,P r (3)-l)
• the M-method for a given subdivision is the main step in the formation of a mechanism that finds a low complexity sub-division, mechanism that is central for this embodiment.
• a line-subdivision of the matrix and perform the M-l -method on each sub-matrix separately. The goal would be to estimate the total number of additions so that a subdivision of fewer additions will be found in the next stage.
• the next goal will be to develop an efficient method that finds the subdivision which minimizes this term. It will be more efficient to do the calculations without computing at each stage the repetitive additive sub-term: 1/p ⁇ + + l/p m and the /.-factor.
• n ,p (pj,p 2 , ,p r )> A,x,z) and integers k , m where 1 ⁇ k ⁇ m ⁇ n.
• h(k,m) min ⁇ C(n, m-k+1, p(k,m), z) , min ⁇ h(k,q-l) + h(q,m): for all k ⁇ q ⁇
• h*(k,m) min ⁇ C*(n, m-k+1, p(k,m) ,z) min ⁇ h*(k,q-l) + h*(q,m):for all k ⁇ q ⁇
• a dynamic programming inventive code that finds the optimal subdivision.
• Optimal Subdivision Tables (n,r,p,z) for b going from 0 to r-1 do for k going from 1 to r-b do m: k+b h*(k,m) ⁇ - — C*(n , m-k+1 , p(k,m),z ) q(k,m) ⁇ k for q going from k+1 to m do d ⁇ h*(k,q-l) + h*(q,m) if d ⁇ h*(k,m) then h*(k,m) ⁇ d and q(k,m) ⁇ q return the tables h* and q.
• the following preferred embodiments of the invention provide inventive algorithms which are detailed implementations of the above methods. They enable additional reduction in memory and energy resources required to perform the above methods. They have the dual goal of enhancing the above methods and of providing the instructions required to build the apparatus.
• One underlining assumption regarding these implementations is that the transformation matrix is generic and may be considered as arbitrarily chosen from the set of matrix having a given set of entries. Another is that the number of rows is small enough when compared with the number of columns such that the above mentioned fundamental bound number ofrows ⁇ log(number of columns) is satisfied. Hence some of the steps that are suitable in other circumstances such a check for equivalent lines are redundant here.
• the mappings described in the text that follows channelize the flow of data from one location to the next.
• Each location is assigned with a binary address corresponding to a column of the matrix at a given iteration.
• U-matrix a (-1) -component of the column, corresponds to 1 in the address, and likewise a 7 -component of the column, corresponds to 0 in the address.
• a similar correspondence is defined for [/ / - matrix.
• the implementations that would be described include a first step where the incoming x -signals are added to preset destinations determined by their corresponding columns, where each x may be multiplied by a sign and/or power of 2. In the proceeding iterations, whenever a column is split with accordance to the invention, the assigned address of each of the two splits is lesser or equal to the address of the given column.
• a finite set of numbers, S, that includes the number 1 is considered, and in this context a matrix of r lines is termed a complete S-r-matrix if it consist of all the possible nonzero configurations of normalized r-dimensional column-vectors whose components belong to the set S, where each configuration appear exactly once and the normalization convention is that the bottom-most nonzero element should be 1. Observe the following low dimensional examples.
• the matiix
• the ordered manner in which the columns appear in the matiix of the above examples reflect another feature of the address settings of these implementations. That is of an addressing based on a consistent rule of translating the columns to an
• Example 1 0-1-Binary-Matrix
• the following sequence of steps describes an implementation of the 0-1 -matrix aspect of the invention.
• the columns of the matrix A are denoted by v_. ,v special.].
• the allocated read and write memory contains 2 r -1 addresses labeled from 1 to 2 r -l, representing the columns participating in the process at each iteration.
• ⁇ (v) ⁇ o ⁇ 3 ⁇ r 2 l V j .
• every address Yi contains the value of the output component y t , for all
• An elementary step in the present terminology is reading a number from one location of the memory, called source, and adding it to a number placed in another location of the memory, called destination.
• Fig. 1 schematically illustrates the operation of updating the contents of a memory employed by an apparatus which performs the main part of the above code, implementing thus in a preferred fashion the 0-7-binary aspect of the invention, with a 0-7-binary matiix 5 comprising 4 rows.
• a column of each matiix at each iteration is represented by an address in the memory, in a binary way.
• the bottom (0 or 7) component (the extreme right hand component in a horizontal presentation) is the MSB and the top (0 or 1) component (the extreme left hand component in a horizontal presentation) is the LSB.
• the addresses Y m 2 m , 0-m-3, contain at the end of the process the components of the
• Example 2 tZ-Matrix
• the following sequence of steps describes an implementation of the [/-matrix aspect of invention.
• the columns of the matrix A would be denoted by o, .Wn-y-
• each location contains one real or complex number, depending on the vector x.
• the allocated read and write memory contains 2 r + r-1 addresses labeled from 0 to 2 r'! + r - 2.
• the following definitions and those of the previous example are required for the description of the present preferred embodiment of the invention.
• initialization Put zero in every address from 0 to 2 r ⁇ +r-2.
• every address Y t contains now the value of y h for all 0-i ⁇ r.
• Fig. 2 schematically illustrates the operation of updating the contents of a memory employed by an apparatus which performs the main part of the above code, implementing thus in a preferred fashion, the [/-binary aspect of the invention, with a [/-binary matrix comprising 4 rows.
• a column of each matrix at each iteration is represented by a binary address in the memory where (-1) -component of the column, corresponds to 1 in the address, and a 7 -component of the column, corresponds to 0 in the address.
• a binary interpretation is applied, where the bottom component (the extreme right hand component in a horizontal presentation) is the MSB and the top component (the extreme left hand component in a horizontal presentation) is the LSB.
• the arrows signify the act of taking the content of one address multiplying it by sign which is 7 or -7 and sending the result to be added to the content of another address.
• One spear arrow signifies that the sign is 7 and double spear arrow signify that the sign is -7. This is done with accordance to the order of the iterations and the (increasing) order of the addresses participating in each iteration.
• Example 3 U ⁇ _- Matrix
• the following sequence of steps describes an unplementation of the GEM method in the case where the entries of the tiansformation matrix belong to the set [ / ⁇ I, -I, j, -j ⁇ . This one of the subcases of the GEM which appear often in applications.
• the columns of the matiix are denoted by wo, ,w n .].
• the allocated read and write memory contains 4 r + r-1 addresses labeled from 0 to 4 r ⁇
• initialization Put zero in every address from 0 to 4 r'1 +r-2.
• Every address Yj contains now the value ofyi, for all 0-i ⁇ r.
• the following sequence of steps describes an implementation of the Toplitz matiix aspect of the invention with [/-coefficients.
• the code Only the first stage differs from that of the [ -matrix example, therefore it is necessary to introduce only this stage
• Fig. 3 schematically illustrates the operation of sending the incoming data to appropriate memory locations, employed by an apparatus which performs the initial part of the above code, with a Toplitz matiix comprising 4 rows. Except for this initial part every other aspect is identical to that of the [/-matrix implementation and o apparatus, and the description there is applicable here.
• spear arrow signify that the sign is 7
• double spear arrow signify that the sign is -7.
• Example 5 Topiltz C / -matrix
• the following preferred embodiment of the invention is an implementation of the Toplitz matiix aspect of the invention with [/ -coefficients.
• the data consists of a [/_- sequence to, -_ and an input complex vector X-(XQ, ,x n +r- 2 ).
• an rx(n+r-l) Toplitz-matiix A ⁇ (ai j ⁇ t t . j : 0-i ⁇ r, Oj- -n+r-2), is formed, where t k ⁇ 0 for all k ⁇ 0 or k—n.
• Example 6 Real Matrix, binary 0-1 representation.
• the following preferred embodiment of the invention is an implementation of the real matrix aspect of the invention with binary 0-7-representation of the matrix-entries.
• Example 7 Real Matrix, binary t -representation.
• the following preferred embodiment of the invention is an implementation of the real matrix aspect of the invention with binary [ -representation of the matrix-entries.
• ⁇ y ⁇ ,n 2 -l ⁇ k ⁇ m j -1 H ⁇ k + ⁇ (2 ⁇ - T m ⁇ )
• main part It is proceed as in the ./-matrix implementation algorithm's main part for r rows and the output is stored in the same addresses at the end of the computational process.
• Fig. 4 is a block diagram of an exemplary apparatus for performing a linear tiansformation with a reduced number of additions, according to a preferred embodiment of the invention.
• the apparatus 500 consists of a multiplier 10 with two inputs and one output, a multiplexer (MUX) 9 for selecting one of its inputs to be transferred to its output, an adder 11 with two inputs and one output, followed by a Dual Port Random Access Memory (DPRAM) 13, having two address bus lines, "add_a” and “add_b” and two outputs, "data_a” and “data_b”.
• the MUX activity is controlled by an address generator 501, which also enables the access to memory addresses in the DPRAM 13.
• the address generator activity is controlled by a counter 3.
• the output of the multiplier 10 is connected to one input, "C", of the MUX 9.
• the output of the MUX 9 is connected to one input "A” of the adder 11.
• the output of the adder 11 is connected to the input of the DPRAM 13.
• One output, “data_a”, of the DPRAM 13 is connected to the input "B” of the adder 11.
• the other output, “data_b”, of the DPRAM 13 is connected to the input "E” of a multiplier 12.
• the other input “F” of the multiplier 12 is connected to the output "sign” of the address generator 501.
• the output of the multiplier 12 is connected to the other input "D” of the MUX 9.
• the counter 3 is connected to two inputs of the address generator 501.
• the output “H” of the generator 501 is connected to the "sign" input of the multiplier 12.
• the output “G” of the generator 501 is connected to the control input "S” of the MUX 9.
• the output "J” of the generator 501 is connected to the first address input "add_a" of the
• the other output "I" of the generator 501 is connected to the second address input "add__b" of the DPRAM 13.
• the transformation matiix may be stored in an optional RAM/ROM 1, which feeds the address generator 501 with the series of codes (a row of bits in the matrix), Do, Di,..., D s , and the multiplier 10, with the most significant bit Do.
• the input vector may be stored in another optional RAM/ROM 2, wliich feeds the multiplier 10 with samples of the input signal.
• the storage memories 1 and 2 can be eliminated if elements of the input vector and their corresponding elements in the transformation matrix are provides in synchronization into the apparatus 500. For example, these elements may be provided by an ADC or a sequence generator. All the components of apparatus 500, are controlled by a common clock via "clock_in" inputs. Using the same input set , [ i X2 Xn the same U matrix,
• the operation of the apparatus 500 may be divided into two stages: the first stage, indicated as "Stage 1", during which the input data (i.e., the samples [xi X2 (is received and the products of each component and its corresponding element of the transformation matrix is calculated and stored in the DPRAM 13; and the second stage, indicated as" Stage 2", during which the received data is processed, while blocking further input data from entering the adder 9.
• the counter 3 counts the accumulated number of operations and the count (the output of the counter) is used to distinguish between the two stages.
• the number of operations of "Stage 1" is the length n of the input vector. Operations beyond this number are associated with "Stage 2".
• the address generator 501 comprises a comparator 4, which is linked to the output of the counter 3.
• the comparator reads the current output of the counter 3, compares it with the length n of the input vector, and provides a corresponding signal, indicating whether the current operation is carried out in "Stage 1" or in "Stage 2". This signal is used to control the input "S" of the MUX 9, so as to switch between the inputs ""C" and "D".
• the address generator 501 also comprises an asynchronous memory 5 (e.g., a ROM), which stores preprogrammed values, and is used as a Look-Up-Table (LUT), for determining addresses in the DPRAM 13 via the input addresses "add_a” and "add_b", for processing their contents.
• the Size of the LUT is (C- ⁇ )x(l+2r), and its contents comprises three fields, a "Source” filed, a "Sign” field and a "Destination” field. For each operation (i.e., each clock cycle, counted by the counter 3), there are three corresponding source sign and destination values.
• the source field comprises information related to each column of the transformation matrix that has been split (divided), as well as an indication related to normalizing of the two parts of that specific column.
• the source field determines the value of the input "add_b" on the DPRAM 13.
• the sign field represents the lower component in each split column or sub-column.
• the destination field determines the value of the input "add_a” on the DPRAM 13, according to which the content of the corresponding address is selected for processing.
• the output of each inverter is connected to one input of a corresponding MUX from a set of s multiplexers, 7 l5 7 2 ...,l s .
• the series of bits Di,..., D s are also fed into the other input of a corresponding MUX from a set of s multiplexers, 7 ls 7 2 ...,l s .
• each MUX from the set 7 ⁇ ,7 2 ...,l s is controlled by the value of the most significant bit Do, so as to enable the transfer of the set Di,..., D s unchanged, or inverted (i.e., Dj,..., D'j) to the input "address_a" of the DPRAM 13.
• the set E>,,..., D s (or Dj,..., D' s ) is input into one input of a corresponding set, 8_,8 2 ...,8,j of s multiplexers, with an additional multiplexer S r which is fed by the MSB (the r-th bit) of "add_a" arriving from the LUT.
• the output of the comparator 4 enables the selection of "add_a” to arrive from the set 7 1 ,7 2 ...,7, s or from the LUT.
• the input “add_a” i.e., the destination
• the input “add_b” taken from the LUT (i.e., the source) controls the second output "data_b” of the DPRAM 13, which is fed into input " ⁇ ” of the multiplier 12, which multiplies each value of "data_b” by a corresponding "sign” value, extracted from the LUT and feeds the product into the input "D” of the multiplier 12.
• the "write” operation in the DPRAM 13 is synchronous, i.e., the contents of each cell is overwritten according to the clock rate (e.g., when the clock signal rises).
• the "read” operation in the DPRAM 13 is asynchronous, i.e., each output is changed at the moment when the address input is changed, regardless the clock. Operation at Stage 1 : At this stage, the counter 3 starts to count the first symbol time (n clock cycles), during which stage 1 is performed.
• the MUX 9 enables data flow from its input "C” to flow to its output and into input "A” of the adder 11, while blocking input “D”.
• the input symbol [xi X2 Xn] is provided into one input of the multiplier 10.
• the MSB E> 0 of the code is provided into the other input of the multiplier 10.
• the destination (output" data_a") that is determined by the input "add_a” is extracted from DPRAM 13 and added to the components [xi X2 Xn] of the input vector, multiplied by the
• the counter 3 which has been counted the current symbol time, provides an indication to the address generator comparator 4 and to the ROM 5 that the current symbol time has been terminated, and the comparator 4 switches the input selection of the MUX 9 from input "C" to the other input "D". Similarly, the comparator 4 drives multiplexers 8 ls 8 2 ...,S S to select data from the LUT, rather from the RAM 1. Operation at Stage 2:
• the counter 3 starts to count the next symbol time, during which stage 2 is performed.
• the MUX 9 enables data flow from its input “D” to flow to its output and into input "A” of the adder 11, while blocking input “C”.
• a selected address in the DPRAM 13 is accessed via "add_b” which represents the source.
• the source data is fed from the second output “data_b” of the DPRAM 13 into the input " ⁇ " of the multiplier 12, in which it is multiplied by the corresponding "sign” value, extracted from the LUT.
• This product is fed into the input "D” of the MUX 9, thereby appearing in the input "A” of the adder 11.
• the content of the current destination value appears in the input "B" of the adder 11.
• the two values are added by the adder 11, and the result is stored at the same address in the DPRAM 13 (which corresponds to the previous destination vaue).
• the corresponding r transformation points O / 's) are stored in the DPRAM 13 at addresses #0 and #2" "7 to (2 r"; +r-2). This process is continued consequently, until the clock provides an indication that stage 2 is terminated (according to a predetermined count) after all the tiansformation points (y . 's) have been calculated and stored in different addresses in the DPRAM 13.
• Figure 5 illustrates an implementation of a product of an rxn U- matrix A by an n-dimensional vector X.
• the representation of the matrix contain 0 or 1 where 0 corresponds to 1, and 1 corresponds to -1.
• the vector is real and v bits are dedicated to each component.
• the matrix A is stored in element 1 (RAM or ROM) and the vector X is stored in element 2 (RAM or ROM).
• the matrix and the vector may be generated from any internal or external device such as memory device or synchronized source, like ADC or some sequences generators, etc.
• a clock that control modules 1,2,3,13 synchronizes the whole system.
• Module 3 is a counter that counts from 0 to C, where C is defined as follows:
• stage 1 the incoming signals from elements 1 &2 are inserted into element 13 with accordance to addresses that are coming from element 3, where each address contains the log 2 n list significant bits.
• the counter is used as an address generator of an asynchronous ROM (element 5 ) of the size of (C-n)x(l + r + r). All the bits of the counter go into element 4 which is a comparator that check if the current count is greater then n.
• the data buses go from element 1 bits-Dl-Ds into elements 6_l-6_s (which are inverters) respectively.
• Element 8_r select between "0" to the r bit (add_a MSB) of element 5.
• the output from 8__l-8_r used as the first address bus of element 13 , which is a dual port RAM at size of (2 " +r-l)x(V+log 2 n). This address defines data_a bus which is an output from element 13 and also the destination of the data_in bus which is an input to element 13.
• Add_b (which is output of element 5 (the Source field)) is the second address bus of element 13 (This address controls data_b bus which is an output from element 13).
• Sign is a single bit output from element 13 which multiply data_b at element 12 (which is a multiplier).
• the data_in bus which is an input with respect to element 13 arrived from element 11, which is an adder that sums together data_a and the output of element 9.
• the data_in goes to add_a destination in a synchronous way, while the read .operation of data_a and data_b is asynchronous.
• Element 9 Prior to the action of element 13 it is initiated by insertion of zeros. Element 9 selects between the outputs of element 10, and element 12. Element 10 multiplies the data bus from element 2 with the LSB of element 1. After C cycles the resulting vector is stored at element 13 at address 0 and addresses 2 r" to (2 r" +r-2).

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