WO2002027782A2 - Fault detection method and apparatus using multiple dimension measurements - Google Patents

Abstract

A method for identifying faults includes processing a plurality of manufacturedd items (210) in a process flow (10); measuring a first dimension of a feature (300, 360) formed on the manufactured items (210) at a first position; measuring at least a second dimension of the feature (300, 360) at a second position proximate the first position; calculating a dimension metric based on the first and second measured dimensions; and comparing dimension metrics for a set of the manufactured items (210) to identify a drift condition. A manufacturing system includes a plurality of tools (30-80, 220) for processing manufactured items (210) to identify a drift condition. A manufacturing system includes a plurality of tools (30-80, 220) for processing manufactured items (210) in a process flow (10), a metrology tool (220), and a fault monitor (130). The metrology tool (220) is adapted to measure a first dimension of a feature (300, 360) formed on the manufactured items (210) at a first position and measure at least a second dimension of a feature (300, 360) formed on the manufactured items (210) at a first position and measure at least a second dimension of the feature (300, 360) at a second position proximate the first position. The fault monitor (130) is adapted to calculate a dimension metric based on the first and second measured dimension and compare dimension metrics for a set of the manufactured items (210) to identify a drift condition.

Description

FAULT DETECTION METHOD AND APPARATUS USING MULTIPLE DIMENSION MEASUREMENTS

TECHNICAL FIELD This invention relates generally to semiconductor device manufacturing and, more particularly, to a fault detection method and apparatus using multiple dimension measurements.

BACKGROUND ART Semiconductor integrated circuit devices are employed in numerous applications, including microprocessors. Generally, the performance of a semiconductor device is dependent on both the density and the speed of the devices formed therein. A common element of a semiconductor device that has a great impact on its performance is a transistor. Design features, such as gate length and channel length, are being steadily decreased in order to achieve higher package densities and to improve device performance. The rapid advance of field effect transistor design has affected a large variety of activities in the field of electronics. in which the transistors are operated in a binary switching mode. In particular, complex digital circuits, such as microprocessors and the like, demand fast-switching transistors. Accordingly, the distance between the drain region and the source region of a field effect transistor, commonly referred to as the channel length or gate length dimension, has been reduced to accelerate the formation of a conductive channel between a source and a drain electrode as soon as a switching gate voltage is applied and, moreover, to reduce the electrical resistance of the channel.

A transistor structure has been created where the longitudinal dimension of the transistor, commonly referred to as the width dimension, extends up to 20 μm, whereas the distance between the drain and source, i.e., the gate length, may be reduced down to 0.2 μm or less. As the gate length of the channel has been reduced to obtain the desired switching characteristic of the source-drain line, the length of the gate electrode is also reduced. Since the gate electrode is typically contacted at one end of its structure, the electrical charges have to be transported along the entire width of the gate electrode, i.e., up to 20 μm, to uniformly build up the transverse electric field that is necessary for forming the channel between the source and drain regions. Due to the small length of the gate electrode, which usually consists of a doped polycrystalline silicon, the electrical resistance of the gate electrode is relatively high, and it may cause high RC-delay time constants. Hence, the transverse electrical field necessary for fully opening the channel is delayed, thereby further deteriorating the switching time of the transistor line. As a consequence, the rise and fall times of the electrical signals are increased, and the operating frequency, i.e., the clock frequency, has to be selected so as to take into account the aforementioned signal performance.

In view of the foregoing, the control of the critical dimensions of the gate electrode is an increasingly important element of the fabrication process. If a gate electrode is formed overly large, its switching speed may be compromised. On the other hand, if the gate electrode is formed too small, based on the design characteristics of the adjacent dielectric materials, the transistor will exhibit a higher leakage current than expected, thus causing excessive power usage and heat generation. Hence, its is important to control critical dimensions of a gate electrode such that the variation around a target gate electrode value is minimized.

One technique for reducing the gate electrode critical dimension variation is to perform post-etch metrology to determine the actual dimensions of the gate electrode after they are formed (i.e., typically by an anisotropic etching process). A scanning electron microscope is one tool suitable for gathering the metrology data. Based on the metrology information, the tools responsible for performing the previous steps in the fabrication process may be fine tuned to bring the actual dimensions closer to the target critical dimensions. For example, a photolithography stepper or an etch tool may be adjusted.

The metrology tools (e.g., scanning electron microscope) used to perform the critical dimension metrology are extremely sensitive. Accordingly, these tools are calibrated frequently, as much as several times per day. Even with such oversight, it is possible for the metrology tool to drift, thus resulting in a drift in the critical dimension measurements. This "metrology drift" causes perceived variations in the critical dimensions of the gate electrode. Another source of drift in the fabrication process is caused by changes in the processing tools or operating recipes of the processing tools used to form the features on the semiconductor devices. Such a drift is referred to as a "process drift." Process drifts are typically corrected by performing a maintenance procedure on an affected processing tool or by changing the operating recipes of one or more processing tools to attempt to bring the critical dimensions back in line with target values. It is possible for a metrology drift to be incorrectly characterized as a process drift, and the processing tools in the process flow prior to the metrology tool may be errantly adjusted to attempt to correct the drift.

Typically, during the fabrication of a semiconductor wafer, a metrology event immediately follows a process event to monitor the performance of the process. Multiple metrology tools may be employed to measure several metrics related to the process performance. After such metrology measurements, adjustments to the operating parameters of process may be made to control the process output in light of a target value. Certain metrology tests, such as electrical performance tests (e.g., effective gate length and drive current), are not performed until many processing steps have been performed (i.e., typically after the first metal layer is formed). It is only at this point that the success of certain previous process events is evident. Although the electrical tests may identify a performance drift, the temporal displacement between the numerous process events and the metrology event makes it difficult to identify the source of the drift or readily adjust the process to account for the drift. Another condition that exacerbates the difficulty in identifying the source of a fault is the number of processing and metrology tools in the process flow. Typically, more than one tool for performing a particular process or metrology step is provided in the manufacturing facility. Each particular lot of wafers may pass through an entirely different set of tools during its production.

Adjusting the process based on errant deviations caused by metrology drifts may actually increase the variation in the gate electrode critical dimensions. For example, the errant metrology tool may improperly indicate that the gate electrodes are too large. The process may be adjusted to further reduce the gate electrode length, resulting in the formation of gate electrodes that are actually too small. When the devices reach the point where they can be electrically tested, they may have excessive leakage and perform poorly, depending on the magnitude of the errant length reduction.

There are various ways for identifying drift conditions. Generally, metrology data (i.e., performance or process) is gathered and evaluated against various rules to determine if an error condition has occurred. Although, various rules may be used, many companies have adopted the "Western Electric Rules," originally developed by the Western Electric Company. The rules specify that an error occurs if:

Rule 1: One measurement exceeds three standard deviations from the target (i.e., l>3σ ); Rule 2: Two out of three consecutive measurements exceed two standard deviations from the target on one side of the target (i.e., 2/3>2σ ); Rule 3: Four out of Five consecutive measurements exceed one standard deviation from the target on one side of the target (i.e., 4/5>σ ); and Rule 4: Eight consecutive points on one side of the target.

Rule 1 and 2 violations are typically associated with process faults or equipment failures. Rule 3 and 4 violations are most often useful for identifying process drifts. Process drifts may result in shifts in feature dimensions, such as oxide thickness or gate electrode length, for example. Such drifts may result in degraded performance of the final product or may cause difficulty for subsequent processing steps. Some drifts may also be the result of errant metrology tools. For example, if the calibration on a metrology tool used to measure a dimension of a feature is out of specification, the metrology information it provides to the manufacturing control system may be inaccurate. Because there are many sources of process variation, it is difficult to identify the actual source and take appropriate corrective actions. If the source of the process variation is misidentified, the corrective actions may serve to increase the process variation rather than compensate for it.

The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.

DISCLOSURE OF INVENTION

One aspect of the present invention is seen in a method for identifying faults. The method includes processing a plurality of manufactured items in a process flow; measuring a first dimension of a feature formed on the manufactured items at a first position; measuring at least a second dimension of the feature at a second position proximate the first position; calculating a dimension metric based on the first and second measured dimensions; and comparing dimension metrics for a set of the manufactured items to identify a drift condition.

Another aspect of the present invention is seen in a manufacturing system including a plurality of tools for processing manufactured items in a process flow, a metrology tool, and a fault monitor. The metrology tool is adapted to measure a first dimension of a feature formed on the manufactured items at a first position and measure at least a second dimension of the feature at a second position proximate the first position. The fault monitor is adapted to calculate a dimension metric based on the first and second measured dimensions and compare dimension metrics for a set of the manufactured items to identify a drift condition. BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

Figure 1 is a simplified block diagram of a manufacturing system in accordance with one illustrative embodiment of the present invention; Figure 2 is a simplified block diagram of a portion of the manufacturing system of Figure 1 illustrating the interfacing between a processing tool, a metrology tool, and a fault monitor;

Figure 3 A is a cross-section view of adjacent gate electrodes measured in accordance with the present invention;

Figure 3B is a top view of a contact opening feature measured in accordance with the present invention; Figure 4 is a control chart illustrating dimension metrics calculated by the fault monitor of Figures 1 and

2; and

Figure 5 is a simplified flow diagram of a method for identifying faults using multiple dimension measurements in accordance with another illustrative embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

MODE(S) FOR CARRYING OUT THE INVENTION Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

Referring to Figure 1, a simplified block diagram of an illustrative manufacturing system 10 is provided.

^' In the illustrated embodiment, the manufacturing system 10 is adapted to fabricate semiconductor devices.

Although the invention is described as it may be implemented in a semiconductor fabrication facility, the invention is not so limited and may be applied to other manufacturing environments. The techniques described herein may be applied to a variety of manufactured items including, but not limited to microprocessors, memory devices, digital signal processors, application specific integrated circuits (ASICs), liquid crystal displays, flat panel displays, micro machines, optical gratings, or other such devices. The techniques may also be applied to manufactured items other than semiconductor devices for which grade estimates may be generated during the fabrication of such items.

A network 20 interconnects various components of the manufacturing system 10, allowing them to exchange information. The illustrative manufacturing system 10 includes a plurality of tools 30-80. Each of the tools 30-80 may be coupled to a computer (not shown) for interfacing with the network 20. The tools 30-80 are grouped into sets of like tools, as denoted by lettered suffixes. For example, the set of tools 30A-30C represent tools of a certain type, such as a photolithography stepper. A particular wafer or lot of wafers progresses through the tools 30-80 as it is being manufactured, with each tool 30-80 performing a specific function in the process flow. Exemplary processing tools for a semiconductor device fabrication environment, include metrology tools, photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, implantation tools, etc. The tools 30-80 are illustrated in a rank and file grouping for illustrative purposes only. In an actual implementation, the tools may be arranged in any order of grouping. Additionally, the connections between the tools in a particular grouping are meant to represent only connections to the network 20, rather than interconnections between the tools.

A process control server 90 directs the high level operation of the manufacturing system 10. The process control server 90 monitors the status of the various entities in the manufacturing system 10 and controls the flow of articles of manufacture (e.g., lots of semiconductor wafers) through the process flow. Typically, the path a particular wafer or lot passes through the process flow varies. Certain tools may be out-of-service for maintenance or otherwise occupied processing other lots. The process control server 90 routes the individual lots through the process flow depending on the steps that need to be performed and the availabilities of the tools 30-80. A particular lot of wafers may pass through the same tool 30-80 more than once in its production (e.g., a particular stepper may be used for more than one masking operation).

A database server 100 is provided for storing data related to the status of the various entities and articles of manufacture in the process flow. The database server 100 may store information in one or more data stores 110. The data may include pre-process and post-process metrology data, tool states, lot priorities, etc. The distribution of the processing and data storage functions amongst the different computers is generally conducted to provide independence and a central information store. Of course, a different number of computers may be used.

An exemplary information exchange and process control framework suitable for use in the manufacturing system 10 is an Advanced Process Control (APC) framework, such as may be implemented using the Catalyst system offered by KLA-Tencor, Inc. The Catalyst system uses Semiconductor Equipment and Materials International (SEMI) Computer Integrated Manufacturing (CIM) Framework compliant system technologies and is based the Advanced Process Control (APC) Framework. CIM (SEMI E81-0699 - Provisional Specification for CIM Framework Domain Architecture) and APC (SEMI E93-0999 - Provisional Specification for CIM Framework Advanced Process Control Component) specifications are publicly available from SEMI. Portions of the invention and corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the ones by which those of ordinary skill in the art effectively convey the substance of their work to others of ordinary skill in the art. An algorithm, as the term is used here, and as it is used generally, is conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, or as is apparent from the discussion, terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

The process control server 90 stores information related to the particular tools 30-80 used to process each lot of wafers in the data store 110. As metrology data is collected related to the lot, the metrology data and a tool identifier indicating the identity of the metrology tool recording the measurements is also stored in the data store 110. The metrology data may include feature measurements, process layer thicknesses, electrical performance, surface profiles, etc.

The manufacturing system 10 includes a statistical process control (SPC) client computer 120 adapted to execute a fault monitoring application program to identify the existence and sources of drifts. Collectively, the SPC client computer 120 executing the fault monitoring application program may be referred to as a fault monitor 130.

Turning to Figure 2, a simplified block diagram of a portion of the manufacturing system 10 of Figure 1 illustrating the interface between a particular processing tool 200 used to process wafers 210 in the process flow, a particular metrology tool 220, and the fault monitor 130 is provided. The processing tool 200 and the metrology tool 220 may represent individual ones of the tools 30-80 shown in Figure 1. The particular relative placements of the processing tool 200 and the metrology tool 220 may vary. For example, the processing tool 200 may be an etch tool used to form gate electrodes, an etch tool used to form a trench, a deposition tool used to form a conductive line, a deposition tool used to form a process layer, an etch tool used to form a contact opening, etc. An exemplary metrology tool 220 for measuring the dimensions described herein is a scanning electron microscope, such as a KLA 8100 scanning electron microscope offered by KLA-Tencor Corporation or an Opal 7830si offered by Applied Materials, Inc. Another suitable metrology tool 220 is a model-based, optical metrology system, such as the Profile Application Server scatterometry system offered by Timbre Technologies.

The metrology tool 220 is adapted to conduct at least two distinct measurements of critical dimensions of the features formed on the wafers 210 in essentially the same position. The metrology tool 220 supplies the results of the critical dimension measurements to the fault monitor 130. In an actual implementation, the metrology tool 220 may store its results directly in the data store 110, and the fault monitor 130 may periodically access the data store 110 to retrieve the metrology data. However, for clarity and ease of illustration, this intermediate step is not illustrated.

Figures 3A and 3B illustrate exemplary semiconductor device features on which the distinct measurements may be taken by the metrology tool 220. Figure 3A is a cross-section view of adjacent, partially- formed transistors 300 after the gate electrodes have been formed. Possible pairs of measurements to be taken by the metrology tool 220 are the top width measurement 310 and the bottom width measurement 320 of the same transistor 300; the top width measurement 310 and the middle width measurement 330 of the transistor 300; the middle width measurement 330 and the bottom width measurement 320 of the transistor; the transistor width measurement 340 (e.g., top, middle, bottom, average, etc.) and the pitch measurement 350 (i.e., distance between transistors 300). Figure 3B is a top view of a contact opening 360 formed in a layer of insulative material 365. The metrology tool 220 may be adapted to take a vertical diameter measurement 370 and a horizontal diameter measurement 380. Other measurement pairs may be used on features different than those illustrated in Figures 3A and 3B. For example, the metrology tool 220 may measure some combination of the top, bottom, and middle widths of a conductive line or trench.

The fault monitor 130 calculates a dimension metric based on the particular measurement pair selected. In general, the dimension metric is some algebraic combination of the measurements. For example, the fault monitor 130 may calculate the difference between the two measurements (i.e., delta metric), or the fault monitor 130 may calculate the ratio of the two measurements (i.e., ratio metric). The specific construct of the dimension metric is implementation specific and depends on the particular feature dimensions being measured. Again, more than two measurements may be taken and the dimension metric may incorporate all of the measurements or multiple dimension metrics may be determined from the plurality of measurements.

In the example of the transistor gate electrode, the transistor gate electrode is expected to have a sloped profile. One process control goal is to maintain the consistency of the profile. Hence, the difference between the top and bottom width measurements would ideally be a constant. For such a case, the delta metric may be selected. In the case of the contact opening 360, the opening is expected to have a generally round cross-section, and the horizontal and vertical width measurements should be approximately the same. Thus, a ratio metric may be employed.

After calculating the dimension metrics for the measurements conducted by the metrology tool 220, the fault monitor 230 tracks the values of the dimension metrics over time to identify statistically significant deviations. The particular techniques employed to detect the deviations are well known to those of ordinary skill in the art using conventional statistical process control techniques, such as control charting. Exemplary deviation detection techniques include determining if a sudden change or trend occurs either in the magnitude of the dimension metrics themselves or in the standard deviations of the dimension metrics.

The sampling frequency at which the metrology tool 220 takes the distinct measurements and the fault monitor 130 calculates the dimension metrics may vary. For example, the metrology tool 220 may take measurements on one wafer per lot or on a sample of wafers in the lot. If more than one measurement is taken per lot, the fault monitor 130 may calculate an average dimension metric value to be compared to the dimension metric values of other lots. Typically, control in a semiconductor fabrication facility is performed on a lot-by-lot basis.

However, in more advanced fabrication facilities, control is shifting to a wafer-by-wafer basis. Accordingly, the measurements and dimension metrics may also be calculated for each wafer being processed. Once the drift is identified based on the analysis of the dimension metrics, the drift may be characterized as either a process drift or a metrology drift. For example, for a metrology drift, the metrology tool may be out of focus, the gate width measurement may change (e.g., increase) but the pitch measurement may stay the same, resulting in a change in the delta metric value. A process drift might cause both the width measurement and the pitch measurement to change. The type of measurements used to form the metric might be useful in characterizing the drift. For example, a contact opening should have a circular cross-section due to the nature of the etch process used to form the opening. If the ratio metric calculated from the horizontal and vertical diameter measurements indicates a drift, the most likely source of the drift is the metrology tool.

Another technique for distinguishing between the possible sources for the drift includes analyzing the processing histories of the lots wafers involved to determine commonalities amongst the lots. For example, the lots involved with the drift may have all been processed by a common processing tool or a common metrology tool. If the nature of the dimension metrics is not sufficient to suggest the source of the drift, such an analysis may be useful in identifying the specific source of the drift.

Referring to Figure 4, a control chart 400 illustrating a plurality of dimension metrics 410 plotted over time is shown. For clarity and ease of illustration, the control chart 400 is simplified to show only dimension metrics 410 associated with a particular processing tool. The dimension metrics represent delta metrics for measurements of the bottom width and the top width of a transistor gate electrode. A line 420 is shown representing an expected delta value corresponding to the target profile for the transistor gate electrode.

Possible profiles for features, such as transistor gate electrodes, include a positive profile (i.e., where the bottom is larger than the top and the sidewall is sloped), a reentrant profile (i.e., where the bottom is smaller than the top and the sidewall is sloped), and a t-top profile (i.e., where the top is larger in a localized region and the sidewalls are not evenly sloped. In the illustrated embodiment, the target profile is positive. Positive profiles can vary from the target profile if the top dimension becomes smaller (i.e., referred to as an overetch profile) or if the bottom dimension becomes larger (i.e., referred to as a footing profile).

The target profile for the transistor gate electrode represented by the line 420 is a positive profile with a (top - bottom) delta of about -1 to -3 nanometers, for example. Note that the dimension metrics 410 surrounded by an ellipse 430 are significantly different than the surrounding dimension metrics. The dimension metrics indicated by the ellipse 430 have a reentrant profile with a (top - bottom) delta of about +2 nanometers. The specific delta values are provided for illustrative purposes only. The actual values will vary depending on the dimensions of the particular feature being formed and its expected profile. Initially, the drift condition was identified in a chart showing dimension metrics associated with many processing tools. Using a common thread analysis technique, such as those described above, the source of the drift was determined to be the processing tool 200 associated with the dimension metrics 410 in the control chart 400. Through the use of the present invention, identification of the drift condition and isolation of the problem are possible earlier as compared to typical fault detection techniques. Conventionally, faults are identified during wafer electrical tests performed many process steps after the formation of the features represented by the dimension metrics 410. Early fault detection corresponds to earlier troubleshooting and corrective action, resulting in less faulty devices being fabricated after the fault.

In response to identifying a drift condition, the fault monitor 130 may take a variety of automatic actions. For example, if the drift is determined to be associated with a particular tool (e.g., process tool 200 or metrology tool 220), the fault monitor 130 may send a message to a centralized process control server (i.e., system responsible for overall process flow) to log the errant tool 200, 220 out of service . The fault monitor 130 may also send an alert to an operator of the appropriate tool 200, 220. In the case where a process drift not isolable to a particular tool 200, 220 has occurred, the fault monitor 130 may send a message to the centralized process control server to cease production on the affected portion of the manufacturing system 10 until further investigations may be performed and/or until corrective actions may be completed. Alternatively, automatic messages may also be provided to individuals responsible for overall operation of the process to inform them of the process drift.

After identification of the fault, the raw measurements used in calculating the dimension metrics may also be used in characterizing the problem with the features being measured. For example, if the delta metric has increased, but either the top or the bottom measurement has remained constant a shift to a footing profile or a overetch profile may have occurred, respectively. Similarly, a shift to a reentrant or t-top profile may also be discerned.

Turning now to Figure 5, a flow diagram of a method for identifying faults using multiple dimension measurements in accordance with an illustrative embodiment of the present invention is provided. In block 500, a plurality of manufactured items are processed in a process flow. In block 510, a first dimension of a feature formed on the manufactured items is measured at a first position. In block 520, a second dimension of the feature is measured at a second position proximate the first position. .In block 530, a dimension metric is calculated based on the first and second measured dimensions. In block 540, dimension metrics for a set of the manufactured items are compared to identify a drift condition.

Identifying drifts in the critical dimensions of semiconductor device features, such as transistors, as described above, provides process owners and tool operators with automatic and timely information for correcting metrology problems or process problems that affect the performance of the semiconductor device. Such oversight allows drift problems to be identified and corrected more quickly, thus reducing the critical dimension variation seen on the final product and increasing the throughput of the processing line. Increased throughput and reduced variation lead directly to increased profitability.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.

Claims

1. A method for identifying faults, comprising: processing a plurality of manufactured items (210) in a process flow (10); measuring a first dimension of a feature (300, 360) formed on the manufactured items (210) at a first position; measuring at least a second dimension of the feature (300, 360) at a second position proximate the first position; calculating a dimension mefric based on the first and second measured dimensions; and comparing dimension metrics for a set of the manufactured items (210) to identify a drift condition.

2. The method of claim 1, wherein calculating the dimension metric comprises algebraically combining the first measurement and the second measurement.

3. The method of claim 1, wherein the feature (300, 360) comprises a transistor gate electrode (300), measuring the first dimension comprises measuring a first width dimension (310, 320, 330) of the transistor gate electrode (300), and measuring the second dimension comprises measuring a second width dimension (310, 320, 330) of the transistor gate electrode (300).

4. The method of claim 1, wherein the feature (300, 360) comprises a transistor gate electrode (300), measuring the first dimension comprises measuring a width dimension (310, 320, 330) of the transistor gate electrode (300), and measuring the second dimension comprises measuring a pitch dimension (350) between the transistor gate electrode (300) and an adjacent transistor gate electrode (300).

5. The method of claim 1, wherein the feature (300, 360) comprises a contact opening (360) defined in a layer (365) of a semiconductor device, measurmg the first dimension comprises measuring a vertical diameter dimension (370) of the contact opening (360), and measuring the second dimension comprises measuring horizontal diameter dimension (380) of the contact opening (360).

6. A manufacturing system, comprising: a plurality of tools (30-80, 200) for processing manufactured items (210) in a process flow (10); a metrology tool (220) adapted to measure a first dimension of a feature (300, 360) formed on the manufactured items (210) at a first position and measure at least a second dimension of the feature (300, 360) at a second position proximate the first position; and a fault monitor (130) adapted to calculate a dimension metric based on the first and second measured dimensions and compare dimension metrics for a set of the manufactured items to identify a drift condition.

7. The system of claim 6, wherein the fault monitor (130) is adapted to algebraically combine the first measurement and the second measurement to generate the dimension metric.

8. The system of claim 6, wherein the feature (300, 360) comprises a transistor gate electrode (300), and the metrology tool (220) is adapted to measure a first width dimension (310, 320, 330) of the transistor gate electrode (300) to generate the first dimension and measure a second width dimension (310, 320, 330) of the transistor gate electrode (300) to generate the second dimension.

9. The system of claim 6, wherein the feature (300, 360) comprises a transistor gate electrode (300), and the metrology tool (220) is adapted to measure a width dimension (310, 320, 330) of the transistor gate electrode to generate the first dimension and measure a pitch dimension (350) between the transistor gate electrode (300) and an adjacent transistor gate electrode (300) to generate the second dimension.

10. The system of claim 6, wherein the feature (300, 360) comprises a contact opening (300) defined in a layer (365) of a semiconductor device (210), and the metrology tool (220) is adapted to measure a vertical diameter dimension (370) of the contact opening (360) to generate the first dimension, and measure the horizontal diameter dimension (380) of the contact opening (360) to generate the second dimension.