WO2002027777A3 - Silicon oxide patterning using cvd photoresist - Google Patents

Silicon oxide patterning using cvd photoresist Download PDF

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Publication number
WO2002027777A3
WO2002027777A3 PCT/US2001/026999 US0126999W WO0227777A3 WO 2002027777 A3 WO2002027777 A3 WO 2002027777A3 US 0126999 W US0126999 W US 0126999W WO 0227777 A3 WO0227777 A3 WO 0227777A3
Authority
WO
WIPO (PCT)
Prior art keywords
silicon oxide
photoresist
layer
substrate
cvd
Prior art date
Application number
PCT/US2001/026999
Other languages
French (fr)
Other versions
WO2002027777A2 (en
Inventor
Gill Lee
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Priority to KR1020037004357A priority Critical patent/KR100564170B1/en
Priority to EP01964510A priority patent/EP1320877A2/en
Publication of WO2002027777A2 publication Critical patent/WO2002027777A2/en
Publication of WO2002027777A3 publication Critical patent/WO2002027777A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers

Abstract

An integrated circuit, and method of forming thereof, in which a CVD photoresist (e.g., PPMS) is formed on a substrate (e.g., silicon 200), patterned and converted into silicon oxide, and is left on the substrate to function as a silicon oxide layer (e.g., PPMSO 204). A high quality cap layer (e.g., PECVD silicon oxide 206) may then be formed over the lower quality silicon oxide layer utilizing a maskless etch process. A high quality silicon oxide layer may be formed on the substrate prior to formation of the CVD photoresist layer to provide a buffer underneath the lower quality silicon oxide. Because etch selectivity is generally not required for the photoresist layer, a thinner photoresist may be used than that of prior art techniques, permitting a larger lithographic process window, increased depth of focus, and a more robust process.
PCT/US2001/026999 2000-09-27 2001-08-30 Silicon oxide patterning using cvd photoresist WO2002027777A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020037004357A KR100564170B1 (en) 2000-09-27 2001-08-30 Silicon oxide patterning using cvd photoresist
EP01964510A EP1320877A2 (en) 2000-09-27 2001-08-30 Silicon oxide patterning using cvd photoresist

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67074300A 2000-09-27 2000-09-27
US09/670,743 2000-09-27

Publications (2)

Publication Number Publication Date
WO2002027777A2 WO2002027777A2 (en) 2002-04-04
WO2002027777A3 true WO2002027777A3 (en) 2002-08-29

Family

ID=24691685

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/026999 WO2002027777A2 (en) 2000-09-27 2001-08-30 Silicon oxide patterning using cvd photoresist

Country Status (3)

Country Link
EP (1) EP1320877A2 (en)
KR (1) KR100564170B1 (en)
WO (1) WO2002027777A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001747A (en) * 1998-07-22 1999-12-14 Vlsi Technology, Inc. Process to improve adhesion of cap layers in integrated circuits
US6114259A (en) * 1999-07-27 2000-09-05 Lsi Logic Corporation Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001747A (en) * 1998-07-22 1999-12-14 Vlsi Technology, Inc. Process to improve adhesion of cap layers in integrated circuits
US6114259A (en) * 1999-07-27 2000-09-05 Lsi Logic Corporation Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
WEIDMAN T W ET AL: "APPLICATIONS OF PLASMA POLYMERIZED METHYLSILANE AS A RESIST AND SILICON DIOXIDE PRECURSOR FOR 193 AND 248 NM LITHOGRAPHY", PROCEEDINGS OF THE SPIE, SPIE, BELLINGHAM, VA, US, no. 2438, 20 February 1995 (1995-02-20), pages 496 - 503, XP008002431 *
YEH C-F ET AL: "NOVEL SIDEWALL CAPPING FOR DEGRADATION-FREE DAMASCENE TRENCHES OF LOW-PERMITTIVITY METHYLSILSESQUIOXANE", JAPANESE JOURNAL OF APPLIED PHYSICS, PUBLICATION OFFICE JAPANESE JOURNAL OF APPLIED PHYSICS. TOKYO, JP, vol. 39, no. 4B, PART 2, 15 April 2000 (2000-04-15), pages L354 - L356, XP000992093, ISSN: 0021-4922 *

Also Published As

Publication number Publication date
WO2002027777A2 (en) 2002-04-04
EP1320877A2 (en) 2003-06-25
KR100564170B1 (en) 2006-03-27
KR20030067670A (en) 2003-08-14

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