WO2002027335A2

WO2002027335A2 - A method and an apparatus for testing electronic devices

Info

Publication number: WO2002027335A2
Application number: PCT/US2001/030364
Authority: WO
Inventors: Tark Wooi Fong; Chu Aun Lim; Kok Hong Chan
Original assignee: Intel Corporation
Priority date: 2000-09-29
Filing date: 2001-09-26
Publication date: 2002-04-04
Also published as: AU2001296373A1; WO2002027335A3

Abstract

An apparatus comprising a body having a first signal line through a first plane of the body and a second signal line through a second plane of the body. A first set of contact elements extend through the body and are coupled to the first signal line. A second set of contact elements extend through the body and are coupled to the second signal lines. The first set of contact elements and the second set of contact elements correspond to a portion of external contact points of an integrated circuit.

Description

A METHOD AND AN APPARATUS FOR TESTING ELECTRONIC DEVICES

BACKGROUND

FIELD OF THE INVENTION

This invention relates generally to testing electronic devices and, more specifically, to a device for testing semiconductor devices.

BACKGROUND Once an electronic device is manufactured, the electronic device is generally tested to ensure that it is working properly. Figure 1 illustrates a conventional apparatus 100 used to test the performance of an electronic device 120 such as an integrated circuit chip. In particular, Figure 1 illustrates handler 110, electronic device 120, test contactor 130, loadboard 160, and tester 170. Tester 170 supports loadboard 160 and test contactor 130 in order to test electronic device 120. Loadboard 160 serves to electrically couple plurality of pins 150 to tester 170. Handler 110 carries electronic device 120 from an area such as a final test location in a manufacturing area (not shown) arid holds electronic device 120 in place while set of contact points 125, such as an array of solder balls at the bottom surface of electronic device 120 contact a corresponding plurality of pins 150 that protrude from test contactor 130.

Plurality of pins 150 includes a set of power pins, a set of ground pins, and signal pins. Power pins provide voltage from a power source (not shown) to set of contact points 125 for testing the performance of electronic device 120. Ground pins have ground zero potential to carry the current to ground and prevent the voltage in the power pins from overheating test contactor 130. To prevent a short circuit, power pins are isolated from ground pins.

Figure 2 illustrates a schematic top view of test contactor 130 on loadboard 160 of the prior art. Test contactor 130 includes test contactor housing 210 that surrounds plurality of pins 150. In testing contact points 125 by plurality of pins

150, pins may be addressed individually at fast transient times. The nature of the quick addressing of plurality of pins 150 (e.g., power pins coupled to power rails) causes voltage noise that is generally attributable to variations in the power source (not shown). Outside of test contactor housing 210 a plurality of capacitor pads 280 that include a plurality of capacitors (e.g., eight capacitors) are placed on loadboard 160 for minimizing variations in the external power source.

Figure 3 illustrates a cross-sectional view of a portion of prior art test contactor 130. Test contactor 130 includes test contactor housing 210 that supports elements of test contactor 130, namely plurality of pins 150. Test contactor housing 210 includes a bottom plate typically made of a polymeric or plastic material such as VESPEL® commercially available from E.I. Dupont de Nemours of Wilmington, Delaware. Test interface unit 270, a combination of test contactor 130 and loadboard 160, interfaces with set of contact points 125 of electronic device 120.

Conventional test contactors have been unable to adequately resolve several problems associated with testing of the performance of electronic devices. Conventional test contactors typically have high frequency noise and voltage drops in power delivery systems due, in part, to fast switching transients (e.g., pin to pin) and the current consumption associated with electronic device testing. To address the noise considerations, capacitors are added to loadboards. Unfortunately, there is a very limited and a relatively ineffective decoupling area on test loadboards for a comprehensive test tooling decoupling solution (e.g., suitable capacitance to reduce noise). Yet another problem relates to dissipation of the heat generated from plurality of pins 150.

In order to reduce the effects from these problems, modifications have been made to conventional test contactors that affect the cost and quality of test contactors. First, the length of each pin of plurality of pins 150 in test contactor 130 has been reduced. However, by reducing the length of each pin, plurality of pins 150 tend to be less reliable and the cost of test contactor 130 is increased. Second, conventional test systems use a large quantity of decoupling capacitors such as eight capacitors e.g., on loadboards that is already fully populated with pin contacts. The larger number of decoupling capacitors increases the cost of the conventional test systems.

Third, conventional test systems increase the time period in which to test the performance of an electronic device such as an integrated circuit due to factors such as excessive noise. By increasing this time period, the time to produce a functional integrated circuit is also increased. This in turn affects the overall cost of producing integrated circuits. It is therefore desirable to have an apparatus and a method for overcoming these disadvantages in the art.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:

Figure 1 illustrates a cross-sectional view of an electronic device to be tested by an apparatus of the prior art;

Figure 2 illustrates a schematic top view of a test contactor of the prior art; Figure 3 illustrates a cross-sectional view of a portion of a test contactor in the prior art;

Figure 4 illustrates a partial cross-sectional view of a test contactor in accordance with one embodiment of the invention;

Figure 5 illustrates a top perspective view of a test contactor in accordance with one embodiment of the invention;

Figure 6 illustrates a top perspective view of a test contactor in accordance with one embodiment of the invention; Figure 7 illustrates a cross-sectional view of a ground pin above a ground plane in accordance with one embodiment of the invention;

Figure 8 illustrates a cross-sectional view of a ground pin coupled to a ground plane in accordance with one embodiment of the invention;

Figure 9 illustrates a cross-sectional view of a ground pin coupled to a power plane in accordance with one embodiment of the invention; Figure 10 illustrates a top view of a printed circuit board in accordance with one embodiment of the invention;

Figure 11 illustrates a top schematic view of a printed circuit board in accordance with one embodiment of the invention; Figure 12 illustrates a cross-sectional view of capacitors located on a capacitor pad on a PCB in accordance with one embodiment of the invention;

Figure 13 illustrates a flow diagram for forming a test contactor on a printed circuit board in accordance with one embodiment of the invention;

Figure 14 illustrates a flow diagram for forming a test contactor on a printed circuit board in accordance with one embodiment of the invention; and

Figure 15 illustrates a flow diagram for using a test contactor on a printed circuit board according to one embodiment of the invention.

DETAILED DESCRIPTION The invention involves testing the performance of electronic devices such as semiconductor devices. In one embodiment, a test contactor includes a first signal line (e.g., power signal line) through a first plane of the test contactor and a second signal line (e.g., ground signal line) through a second plane of the test contactor. A first set of contact elements (e.g., power pins) extend through the test contactor body and are coupled to the first signal line. A second set of contact elements (e.g., ground pins) extend through the test contactor body and are coupled to the second signal line. Collectively, the first set of contact elements and the second set of contact elements correspond to a portion of external contact points of an integrated circuit. Another embodiment of the invention involves a printed circuit board (PCB) containing the power and ground planes and capacitor(s) in which the power and ground planes are embedded in the test contactor.

In one aspect, the claimed invention decreases the cost and time it takes to test electronic devices and increases the quality of testing an electronic device. For example, decoupling performance is improved by the contribution from a power plane and a ground plane in the test contactor rather than externally located, e.g., on a loadboard. Configured in this manner, the voltage drop associated with pin addressing is also reduced.

Referring to testing aspects, decoupling performance is also improved by placing one or more capacitors, such as surface mount technology (SMT) capacitors, onto a test contactor body comprising a PCB that results in increased physical closeness between the capacitor(s) and the electronic device to be tested. This allows the power distribution loop area to be decreased which reduces the impedance and thus the bypass noise. Additionally, the capacitor response time is also reduced against a sudden demand of the current.

The enhanced decoupling capability due to the placement of capacitor(s) on the test contactor also decreases the number of decoupling capacitors in the test interface unit. By having fewer decoupling capacitors, the cost of the test tools such as a test interface unit and a test contactor is reduced. This also allows the test interface unit to have a greater amount of space to place additional elements in the test interface unit.

By incorporating a power plane and a ground plane into the body of a test contactor and possibly incorporating capacitors into the test contactors, voltage drops in pin addressing may be reduced. Longer pins may be used that generally have greater reliability and an extended lifetime than current state-of-the-art reduced-size pins. By using these longer pins, the cost of the test contactor may also be reduced. The reduced voltage drop also tends to speed device testing. In the following description, numerous specific details such as specific materials, processing parameters, processing steps, etc., are set forth in order to provide a thorough understanding of the invention. One skilled in the art will recognize that these details need not be specifically adhered in order to practice the claimed invention. In other instances, well known processing steps, materials, etc., are not set forth in order not to obscure the invention.

Figure 4 illustrates a partial cross-sectional view of testing system 300 in accordance with one embodiment of the invention. Testing system 300 includes test contactor 305 supported by test contactor housing 310. Test contactor housing 310 includes printed circuit board (PCB) 320 shown in ghost lines that may be made of a polymeric or plastic material. In this example, PCB 320 includes at least one power plane 360 and at least one ground plane 370 extending laterally (in an x-direction) through test contactor housing 310. It is appreciated, however, that PCB 320 may include a plurality of power and ground planes to form a multi-layer PCB 320.

Apertures located in PCB 320 are configured to receive plurality of pins 155 that include power pins, ground pins, and signal pins. An aperture is slightly larger in diameter than the diameter of a pin in plurality of pins 155. Plurality of pins 155 generally may be longer, cheaper, and more reliable than the state-of-the- art short pins recommended for prior art test contactors. Plurality of pins 155 are coupled to power plane 360 and ground plane 370. Power plane 360 receives power from a power source (not shown) external to test contactor 305. Figure 5 and Figure 6 illustrate top perspective views of test contactor 400 in accordance with one embodiment of the invention. Ground pins 340 are disposed through PCB 320 in one embodiment and coupled to ground plane 370. One way this is accomplished is by coupling ground pin 340 to ground plane 370 as illustrated in Figure 7 and Figure 8. In Figure 7, ground pin 340 includes lip 162 and beveled distal tip 164. Lip 162 of ground pin 340 is a conductive material coupled to or integrally formed to ground pin 340, having an outside diameter greater than aperture 372 such that it fits securely in aperture 372 thus establishing an electrical connection with ground plane 370. Ground pin 340 is shown above aperture 372 in ground plane 370 prior to inserting ground pin 340 into ground plane 370. Figure 8 shows ground pin 340 electrically coupled to ground plane 370 through lip 162.

While all ground pins 340 are electrically connected to ground plane 370, ground pins 340 are not electrically connected to power plane 360. Referring to Figure 5, ground pins 340 are placed through apertures in power plane 360. The apertures in power plane 360 for ground pins 340 have power plane anti-pads 520 that prevent ground pins 340.from contacting power plane 360. One example of an anti-pad is anti-pad 379 illustrated in Figure 9. Anti-pad 379 is an opening or via (formed, for instance, by an etching process during the fabrication of PCB 320) of a diameter larger than the outside diameter of ground pin 340 but smaller than the diameter of an opening in power plane 360 such that the clearance in power plane 370 prevents ground pin 340 from connecting with power plane 360. Another embodiment of an anti-pad is, for example, in an opening of a diameter of PCB 320 and power plane 360 larger than the outside diameter of ground pin 340, in which a dielectric material such as a polyimide is selectively introduced along the edges of the aperture such that pin 340 is not electrically connected to power plane 360. The amount of dielectric material may be that amount that prevents ground pin 340 from connecting with power plane 360 but still allows a sufficient diameter for ground pin 340 to be inserted. Figure 5 shows power pin 350 extending through and not contacting ground plane 370 through the use of an anti-pad.

Figure 6 illustrates a top perspective view of test contactor 400 in accordance with one embodiment of the invention. Power pins 350 are electrically connected to power plane 360. Power pins 350, however, are not electrically connected to ground plane 370. Power pins 350 are inserted into ground plane anti-pads 510 preventing power pins 350 from contacting ground plane 370. Anti-pads in apertures of ground plane 370 have the same or similar qualities and dimensions as anti-pads in power plane 360. Additionally, though not shown, signal pins have anti pads formed for both power plane 360 and ground plane 370. Figure 10 illustrates a top view of PCB 320 in accordance with one embodiment of the invention. As illustrated, ground pins 340 are surrounded by power plane anti-pads 520 located in power plane 360. Similarly, power pins 350 are surrounded by ground plane anti-pads 510 located in ground plane 370. In Figure 10, ghost lines used in anti-pads 510 represent anti-pads 510 as not being located on the same plane as anti-pads 520. Figure 11 illustrates a top schematic view of PCB 420 in which four capacitors pads 610 that may hold capacitors, e.g., surface mount technology (SMT) capacitors, placed on the periphery of PCB 420. Each capacitor pad may hold a plurality of SMT capacitors, e.g., twenty SMT capacitors. SMT capacitors are coupled to power plane 360.

Figure 12 illustrates a cross-sectional view of capacitors located on PCB 420 in accordance with one embodiment of the invention. First capacitor 630 extends from capacitor pad 610 through power plane 360 and ground plane 370 whereas second capacitor 640 extends from capacitor pad 610 through power plane 360. In this configuration, first capacitor 630 and second capacitor 640 reduce the variations that occur from an external power source.

Figure 13 illustrates a flow diagram in accordance with one embodiment of the invention. At block 700, PCB, defined by power plane and the ground plane, is embedded into a test contactor housing or body. At block 710, capacitors such as SMT capacitor(s) are placed on a capacitor pad located on the surface of the PCB. The SMT capacitor(s) are placed at the periphery of the PCB in order to enhance the decoupling performance due to capacitance contribution between the power plane and the ground plane. At block 720, the power pins are not electrically connected to the ground plane because the power pins are inserted into apertures, configured to receive the power pins, that are surrounded by anti- pads located in the ground plane. The power pins, however, are electrically connected to the power plane. Additionally, at block 730, ground pins are electrically connected to the ground plane of the PCB; however, the ground pins are inserted into apertures, configured to receive ground pins, that are surrounded by anti-pads in the power plane which prevents the ground pins from being electrically connected to the power plane. Anti-pads are also used for signal pins located both in the power plane and the ground plane of the PCB.

Figure 14 Illustrates a flow diagram to manufacture a test contactor according to one embodiment of the invention. At block 800, a power plane and a ground plane are formed by typical plating techniques applied to a polymer material such as polyimide.

At block 810, a PCB is formed from at least one power plane and one ground plane. In another embodiment, the PCB is formed from a plurality of power and ground planes forming a multi-layer PCB. At block 820, a test contactor body has a plurality of apertures formed therein, for example, by typical drilling techniques. The apertures have a diameter large enough to accommodate the body of a pin. Apertures are surrounded by anti-pads that also have a larger diameter than the body of the pin. At block 830, a first set of anti-pads are formed in a first plane such as a power plane. At block 840, a second set of anti-pads are formed in a second plane such as a ground plane. At block 850, a first set of electrical connectors such as ground pins are coupled to a first set of anti-pads. At block 860, a second set of electrical connectors such as power pins are coupled to a second set of anti-pads. Studies have been performed that show that the test contactor has improved performance over conventional test contactors. For example, in one study, the test contactor achieved higher capacitance than conventional test contactors as illustrated in Table 1. Higher capacitance is desirable for both the power and ground pin configurations so there is sufficient voltage for each pin when signaled. In this study, a three dimensional parameter extractor commercially available from Ansoft Corporation located in Pittsburgh, Pennsylvania was used to extract inductive resistance capacitance (IRC) parasitic (mutual coupling from neighboring pins) of the test contactor in comparison with a conventional test contactor. Extractions were performed for two different power-ground pin configurations of each type of test contactor consisting of eight power pins and eight ground pins. The field solver extraction provided 8X8 IRC matrices for each power pin and ground pin configuration. Table 1 provides the results of this study.

Referring to Table 1, the capacitance of the test contactor is much higher compared to conventional test contactors. For example, the test contactor of the claimed invention has 8.7xl0"¹³ farads (F) compared to the capacitance 5.3xl0-¹³ F of the conventional test contactor.

Table 1 - Equivalent Per Pin IRC Parasitic of A Conventional Test Contactor and A Test Contactor

Figure 15 illustrates a flow diagram for using a test contactor according to one embodiment of the invention. At block 900, the integrated circuit having a set of contact points is positioned above a test contactor. At block 910, the loadboard contacts both the tester and the plurality of pins (e.g., ground pins, power pins, and signal pins) of the test contactor. Embedded into the test contactor are the power and ground planes of the PCB. Additionally, SMT capacitors are located on the periphery of the PCB. At block 920, the plurality of pins of the test contactor contact the set of contact points of the electronic device. At block 930, the integrated circuit is tested using the test contactor.

In the foregoing specification, the invention is described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMS:What is claimed is:

1. An apparatus comprising: a body; a first signal line through a first plane of the body; a second signal line through a second plane of the body; a first set of contact elements extending through the body and coupled to the first signal line; a second set of contact elements extending through the body and coupled to the second signal line, wherein collectively the first set of contact elements and the second set of contact elements correspond to a portion of external contact points of an integrated circuit.

2. The apparatus of claim 1, wherein the printed circuit board is defined by the first plane and the second plane.

3. The apparatus of claim 2, further comprising a capacitor coupled to the body and the first signal line.

4. The apparatus of claim 1, wherein the first signal line is a power plane.

5. The apparatus of claim 1, wherein the second signal line is a ground plane.

6. The apparatus of claim 1, wherein a first set of anti-pads are located between the first set of contact elements and the first signal line.

7. The apparatus of claim 1, wherein a second set of anti-pads are located between the second set of contact elements and the second signal line.

8. An apparatus comprising: a body having a first set of electrical connectors and a second set of electrical connectors disposed therethrough; the body comprises a first conductive plane and a second conductive plane; the first conductive plane has a first set of apertures in which a portion of the first set of apertures include anti-pads for the first set of electrical connectors; and the second conductive plane has a second set of apertures in which a portion of the second set of apertures include anti-pads for the second set of electrical connectors.-

9. The apparatus of claim 8, wherein the printed circuit board is defined by the first plane and the second plane.

10. The apparatus of claim 9, wherein at least one surface mount technology capacitor is placed at a periphery of the printed circuit board.

11. The apparatus of claim 8, wherein the first plane is a power plane.

12. The apparatus of claim 8, wherein the second plane is a ground plane.

13. The apparatus of claim 8, wherein the portion of the first set of apertures in the first plane which have anti-pads configured to receive a set of ground pins.

14. The apparatus of claim 8, wherein the portion of the second set of apertures in the second plane which have anti-pads configured to receive a set of power pins.

15. An apparatus comprising: a tester; a test contactor comprising a body having a first set of electrical connectors and a second set of electrical connectors disposed therethrough; the body comprises a first conductive plane and a second conductive plane; the first plane has a first set of apertures in which a portion of the first set of apertures include anti-pads for the first set of electrical connectors; the second plane has a second set of apertures in which a portion of the second set of apertures include anti-pads for the second set of electrical connectors; and a loadboard electrically coupling the first set of electrical connectors and the second set of electrical connectors to the tester.

16. The apparatus of claim 15, wherein a plurality of surface mount technology capacitors are placed on the first plane.

17. The apparatus of claim 15, wherein the portion of the first set of apertures in the first plane include anti-pads configured to receive a set of ground pins.

18. The apparatus of claim 15, wherein the portion of the second set of apertures in the second plane includes anti-pads configured to receive a set of power pins.

19. A method comprising: providing a body having a first set of electrical connectors and a second set of electrical connectors, the body includes a first plane having a first set of apertures and a second plane having a second set of apertures; placing anti-pads into a portion of the first set of apertures; inserting a first set of electrical connectors into the first set of apertures; • placing anti-pads into a portion of the second set of apertures; and inserting a second set of electrical connectors into the second set of apertures.

20. The method of claim 19, further comprising: defining a printed circuit board with the first plane and a second plane.

21. The method of claim 19, wherein the first plane if a power plane.

22. The method of claim 19, wherein the second plane is a ground plane.

23. The method of claim 19, wherein the portion of the first set of apertures have anti-pads configured to receive a set of ground pins.

24. The method of claim 19, wherein the portion of the second set of apertures have anti-pads configured to receive a set of power pins.