WO2002008964A3 - Integrated circuit - Google Patents

Integrated circuit Download PDF

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Publication number
WO2002008964A3
WO2002008964A3 PCT/EP2001/008534 EP0108534W WO0208964A3 WO 2002008964 A3 WO2002008964 A3 WO 2002008964A3 EP 0108534 W EP0108534 W EP 0108534W WO 0208964 A3 WO0208964 A3 WO 0208964A3
Authority
WO
WIPO (PCT)
Prior art keywords
cells
integrated circuit
connections
cell
types
Prior art date
Application number
PCT/EP2001/008534
Other languages
German (de)
French (fr)
Other versions
WO2002008964A2 (en
Inventor
Martin Vorbach
Armin Nueckel
Volker Baumgarte
Gerd Ehlers
Original Assignee
Pact Informationstechnolgie Gm
Martin Vorbach
Armin Nueckel
Volker Baumgarte
Gerd Ehlers
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10036627A external-priority patent/DE10036627A1/en
Priority claimed from PCT/EP2001/006703 external-priority patent/WO2002013000A2/en
Priority to AU2001289737A priority Critical patent/AU2001289737A1/en
Priority to EP01969493A priority patent/EP1377919A2/en
Application filed by Pact Informationstechnolgie Gm, Martin Vorbach, Armin Nueckel, Volker Baumgarte, Gerd Ehlers filed Critical Pact Informationstechnolgie Gm
Publication of WO2002008964A2 publication Critical patent/WO2002008964A2/en
Priority to EP02712937A priority patent/EP1454258A2/en
Priority to EP02727358A priority patent/EP1540507B1/en
Priority to PCT/EP2002/002402 priority patent/WO2002071196A2/en
Priority to US10/471,061 priority patent/US7581076B2/en
Priority to AU2002257615A priority patent/AU2002257615A1/en
Priority to US10/469,910 priority patent/US20070299993A1/en
Priority to AU2002254921A priority patent/AU2002254921A1/en
Priority to JP2002570052A priority patent/JP4011488B2/en
Priority to PCT/EP2002/002398 priority patent/WO2002071248A2/en
Priority to JP2002570103A priority patent/JP2004535613A/en
Priority to PCT/EP2002/002403 priority patent/WO2002071249A2/en
Priority to EP02724198.3A priority patent/EP1386220B1/en
Priority to JP2002570104A priority patent/JP2004536373A/en
Priority claimed from DE10129237A external-priority patent/DE10129237A1/en
Publication of WO2002008964A3 publication Critical patent/WO2002008964A3/en
Priority to JP2008249112A priority patent/JP2009020909A/en
Priority to JP2008249115A priority patent/JP2009043275A/en
Priority to JP2008249116A priority patent/JP2009043276A/en
Priority to JP2008249106A priority patent/JP2009054170A/en
Priority to JP2008249099A priority patent/JP2009032281A/en
Priority to US12/496,012 priority patent/US20090300262A1/en
Priority to US12/944,068 priority patent/US9037807B2/en
Priority to US13/043,102 priority patent/US20110173389A1/en
Priority to US13/653,639 priority patent/US9075605B2/en
Priority to US14/219,945 priority patent/US9552047B2/en
Priority to US14/231,358 priority patent/US9436631B2/en
Priority to US14/318,211 priority patent/US9250908B2/en
Priority to US14/500,618 priority patent/US9141390B2/en
Priority to US15/225,638 priority patent/US10152320B2/en
Priority to US15/408,358 priority patent/US10331194B2/en
Priority to US16/190,931 priority patent/US20190102173A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to an integrated circuit comprising several adjacent cells, whereby at least two types of cells, which have connections, are provided. According to said method, the cells are of a sufficient size for integrating a large number of logic elements. At least one logic element can be programmed in at least some of the cells and the connections are provided in positions, which at least substantially correspond in the cell, in order to permit a mixture of cell types in the adjacent assembly of cells.
PCT/EP2001/008534 2000-07-24 2001-07-24 Integrated circuit WO2002008964A2 (en)

Priority Applications (31)

Application Number Priority Date Filing Date Title
AU2001289737A AU2001289737A1 (en) 2000-07-24 2001-07-24 Integrated circuit
EP01969493A EP1377919A2 (en) 2000-07-24 2001-07-24 Integrated circuit
PCT/EP2002/002403 WO2002071249A2 (en) 2001-03-05 2002-03-05 Method and devices for treating and/or processing data
JP2002570104A JP2004536373A (en) 2001-03-05 2002-03-05 Data processing method and data processing device
EP02724198.3A EP1386220B1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
AU2002257615A AU2002257615A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
JP2002570052A JP4011488B2 (en) 2001-03-05 2002-03-05 Data processing and / or data processing method and apparatus
PCT/EP2002/002402 WO2002071196A2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
US10/471,061 US7581076B2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
EP02712937A EP1454258A2 (en) 2001-03-05 2002-03-05 Method and devices for treating and/or processing data
US10/469,910 US20070299993A1 (en) 2001-03-05 2002-03-05 Method and Device for Treating and Processing Data
AU2002254921A AU2002254921A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
EP02727358A EP1540507B1 (en) 2001-03-05 2002-03-05 Device for processing data with an array of reconfigurable elements
PCT/EP2002/002398 WO2002071248A2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
JP2002570103A JP2004535613A (en) 2001-03-05 2002-03-05 Data processing method and data processing device
JP2008249116A JP2009043276A (en) 2001-03-05 2008-09-26 Fifo storage method
JP2008249106A JP2009054170A (en) 2001-03-05 2008-09-26 Management method for data flow
JP2008249112A JP2009020909A (en) 2001-03-05 2008-09-26 Method for partitioning graph
JP2008249099A JP2009032281A (en) 2001-03-05 2008-09-26 Method for data transmission
JP2008249115A JP2009043275A (en) 2001-03-05 2008-09-26 Method of forming sequence
US12/496,012 US20090300262A1 (en) 2001-03-05 2009-07-01 Methods and devices for treating and/or processing data
US12/944,068 US9037807B2 (en) 2001-03-05 2010-11-11 Processor arrangement on a chip including data processing, memory, and interface elements
US13/043,102 US20110173389A1 (en) 2001-03-05 2011-03-08 Methods and devices for treating and/or processing data
US13/653,639 US9075605B2 (en) 2001-03-05 2012-10-17 Methods and devices for treating and processing data
US14/219,945 US9552047B2 (en) 2001-03-05 2014-03-19 Multiprocessor having runtime adjustable clock and clock dependent power supply
US14/231,358 US9436631B2 (en) 2001-03-05 2014-03-31 Chip including memory element storing higher level memory data on a page by page basis
US14/318,211 US9250908B2 (en) 2001-03-05 2014-06-27 Multi-processor bus and cache interconnection system
US14/500,618 US9141390B2 (en) 2001-03-05 2014-09-29 Method of processing data with an array of data processors according to application ID
US15/225,638 US10152320B2 (en) 2001-03-05 2016-08-01 Method of transferring data between external devices and an array processor
US15/408,358 US10331194B2 (en) 2001-03-05 2017-01-17 Methods and devices for treating and processing data
US16/190,931 US20190102173A1 (en) 2001-03-05 2018-11-14 Methods and systems for transferring data between a processing device and external devices

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
DE10036221.4 2000-07-24
DE10036221 2000-07-24
DE10036627A DE10036627A1 (en) 2000-07-24 2000-07-27 Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
DE10036627.9 2000-07-27
EPPCT/EP00/10516 2000-10-09
EPPCT/EP00/10516 2000-10-09
EP01102674 2001-02-07
EP01102674.7 2001-02-07
DE10110530 2001-03-05
DE10110530.4 2001-03-05
DE10111014.6 2001-03-07
DE10111014 2001-03-07
EPPCT/EP01/06703 2001-06-13
PCT/EP2001/006703 WO2002013000A2 (en) 2000-06-13 2001-06-13 Pipeline configuration unit protocols and communication
DE10129237.6 2001-06-20
DE10129237A DE10129237A1 (en) 2000-10-09 2002-06-20 Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit

Publications (2)

Publication Number Publication Date
WO2002008964A2 WO2002008964A2 (en) 2002-01-31
WO2002008964A3 true WO2002008964A3 (en) 2003-10-23

Family

ID=56290174

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/008534 WO2002008964A2 (en) 2000-07-24 2001-07-24 Integrated circuit

Country Status (3)

Country Link
EP (1) EP1377919A2 (en)
AU (1) AU2001289737A1 (en)
WO (1) WO2002008964A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003071432A2 (en) 2002-02-18 2003-08-28 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
FR2838208B1 (en) * 2002-04-03 2005-03-11 Centre Nat Rech Scient LOGICAL CALCULATION ARCHITECTURE COMPRISING MULTIPLE CONFIGURATION MODES

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994014123A1 (en) * 1992-12-11 1994-06-23 National Technology, Inc. Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means
DE19654595A1 (en) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
DE19654846A1 (en) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
EP0858168A1 (en) * 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor array
WO1999040522A2 (en) * 1998-02-05 1999-08-12 Sheng, George, S. Digital signal processor using a reconfigurable array of macrocells

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0688659A3 (en) * 1994-06-23 1997-10-08 Illig Maschinenbau Adolf Forming and punching tool for producing thermoplastic containers
US5636368A (en) * 1994-12-23 1997-06-03 Xilinx, Inc. Method for programming complex PLD having more than one function block type
GB9611994D0 (en) * 1996-06-07 1996-08-07 Systolix Ltd A field programmable processor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994014123A1 (en) * 1992-12-11 1994-06-23 National Technology, Inc. Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means
DE19654595A1 (en) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
DE19654846A1 (en) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
EP0858168A1 (en) * 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor array
WO1999040522A2 (en) * 1998-02-05 1999-08-12 Sheng, George, S. Digital signal processor using a reconfigurable array of macrocells

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1377919A2 *

Also Published As

Publication number Publication date
EP1377919A2 (en) 2004-01-07
AU2001289737A1 (en) 2002-02-05
WO2002008964A2 (en) 2002-01-31

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