WO2002003423A8 - Capacitor and capacitor contact process for stack capacitor drams - Google Patents

Capacitor and capacitor contact process for stack capacitor drams

Info

Publication number
WO2002003423A8
WO2002003423A8 PCT/US2001/021164 US0121164W WO0203423A8 WO 2002003423 A8 WO2002003423 A8 WO 2002003423A8 US 0121164 W US0121164 W US 0121164W WO 0203423 A8 WO0203423 A8 WO 0203423A8
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
drams
stack
contact process
stacked
Prior art date
Application number
PCT/US2001/021164
Other languages
French (fr)
Other versions
WO2002003423A2 (en
WO2002003423A3 (en
Inventor
Thomas W Dyer
Gerhard Kunkel
Louis L Hsu
Heon Lee
David Kotecki
Young Limb
Carl J Radens
Young Jin Park
Original Assignee
Infineon Technologies Corp
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp, Ibm filed Critical Infineon Technologies Corp
Publication of WO2002003423A2 publication Critical patent/WO2002003423A2/en
Publication of WO2002003423A8 publication Critical patent/WO2002003423A8/en
Publication of WO2002003423A3 publication Critical patent/WO2002003423A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.
PCT/US2001/021164 2000-06-30 2001-07-02 Capacitor and capacitor contact process for stack capacitor drams WO2002003423A2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US60854000A 2000-06-30 2000-06-30
US60947200A 2000-06-30 2000-06-30
US09/609,472 2000-06-30

Publications (3)

Publication Number Publication Date
WO2002003423A2 WO2002003423A2 (en) 2002-01-10
WO2002003423A8 true WO2002003423A8 (en) 2002-04-11
WO2002003423A3 WO2002003423A3 (en) 2002-08-08

Family

ID=27085797

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/021164 WO2002003423A2 (en) 2000-06-30 2001-07-02 Capacitor and capacitor contact process for stack capacitor drams

Country Status (1)

Country Link
WO (1) WO2002003423A2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950012554B1 (en) * 1992-06-24 1995-10-18 현대전자산업주식회사 Method of manufacturing a storage node of vlsi semiconductor device
US6025221A (en) * 1997-08-22 2000-02-15 Micron Technology, Inc. Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks
US5895239A (en) * 1998-09-14 1999-04-20 Vanguard International Semiconductor Corporation Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts
FR2785720B1 (en) * 1998-11-05 2003-01-03 St Microelectronics Sa MANUFACTURE OF DRAM MEMORY AND MOS TRANSISTORS

Also Published As

Publication number Publication date
WO2002003423A2 (en) 2002-01-10
WO2002003423A3 (en) 2002-08-08

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