WO2002003423A3 - Capacitor and capacitor contact process for stack capacitor drams - Google Patents

Capacitor and capacitor contact process for stack capacitor drams Download PDF

Info

Publication number
WO2002003423A3
WO2002003423A3 PCT/US2001/021164 US0121164W WO0203423A3 WO 2002003423 A3 WO2002003423 A3 WO 2002003423A3 US 0121164 W US0121164 W US 0121164W WO 0203423 A3 WO0203423 A3 WO 0203423A3
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
drams
stack
stacked
electrical contacts
Prior art date
Application number
PCT/US2001/021164
Other languages
French (fr)
Other versions
WO2002003423A8 (en
WO2002003423A2 (en
Inventor
Thomas W Dyer
Gerhard Kunkel
Louis L Hsu
Heon Lee
David Kotecki
Young Limb
Carl J Radens
Young Jin Park
Original Assignee
Infineon Technologies Corp
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US60854000A priority Critical
Priority to US60947200A priority
Priority to US09/609,472 priority
Application filed by Infineon Technologies Corp, Ibm filed Critical Infineon Technologies Corp
Publication of WO2002003423A2 publication Critical patent/WO2002003423A2/en
Publication of WO2002003423A8 publication Critical patent/WO2002003423A8/en
Publication of WO2002003423A3 publication Critical patent/WO2002003423A3/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5283Cross-sectional geometry
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.
PCT/US2001/021164 2000-06-30 2001-07-02 Capacitor and capacitor contact process for stack capacitor drams WO2002003423A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US60854000A true 2000-06-30 2000-06-30
US60947200A true 2000-06-30 2000-06-30
US09/609,472 2000-06-30

Publications (3)

Publication Number Publication Date
WO2002003423A2 WO2002003423A2 (en) 2002-01-10
WO2002003423A8 WO2002003423A8 (en) 2002-04-11
WO2002003423A3 true WO2002003423A3 (en) 2002-08-08

Family

ID=27085797

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/021164 WO2002003423A2 (en) 2000-06-30 2001-07-02 Capacitor and capacitor contact process for stack capacitor drams

Country Status (1)

Country Link
WO (1) WO2002003423A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5332685A (en) * 1992-06-24 1994-07-26 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a DRAM cell
US5895239A (en) * 1998-09-14 1999-04-20 Vanguard International Semiconductor Corporation Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts
US6025221A (en) * 1997-08-22 2000-02-15 Micron Technology, Inc. Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks
EP0999585A1 (en) * 1998-11-05 2000-05-10 France Telecom DRAM memory and MOS transistor fabrication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5332685A (en) * 1992-06-24 1994-07-26 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a DRAM cell
US6025221A (en) * 1997-08-22 2000-02-15 Micron Technology, Inc. Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks
US5895239A (en) * 1998-09-14 1999-04-20 Vanguard International Semiconductor Corporation Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts
EP0999585A1 (en) * 1998-11-05 2000-05-10 France Telecom DRAM memory and MOS transistor fabrication

Also Published As

Publication number Publication date
WO2002003423A8 (en) 2002-04-11
WO2002003423A2 (en) 2002-01-10

Similar Documents

Publication Publication Date Title
US5170233A (en) Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor
JP2501065B2 (en) Method for manufacturing a highly integrated semiconductor device having a high volume capacitor
NL1014455C2 (en) DRAM cell capacitor and manufacturing method thereof.
US7101783B2 (en) Method for forming bit-line of semiconductor device
TW375795B (en) Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array
KR0126623B1 (en) Method for fabricating capacitors of semiconductor device
US5604146A (en) Method to fabricate a semiconductor memory device having an E-shaped storage node
US6373084B2 (en) Shared length cell for improved capacitance
TW396602B (en) Highly integrated memory cell and method of manufacturing thereof
US5155056A (en) Process for formation of cells having self-aligned capacitor contacts, and structure thereof
TW384543B (en) Self-aligned diffused source vertical transistors with stack capacitors in a 4f-square memory cell array
JP3172321B2 (en) The method of manufacturing a semiconductor memory device
GB2324408A (en) Forming DRAM cells
TW448543B (en) High performance DRAM and method of manufacture
JPH02133953A (en) Sidewall electrostatic capacitance body dram cell
WO2007001853A2 (en) Method of forming stacked capacitor dram cells
JPH11289069A (en) Trench storage dram cell containing step travel element and its formation method
EP0858109A3 (en) Semiconductor memory device and method for manufacturing thereof
WO2001095378A3 (en) Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
JPH0439964A (en) Dram cell, laminated-type capacitor of dram cell, and its manufacturing method
JPH03173470A (en) Semiconductor storage device
US5427974A (en) Method for forming a capacitor in a DRAM cell using a rough overlayer of tungsten
TW554344B (en) Semiconductor memory device
US5482885A (en) Method for forming most capacitor using poly spacer technique
KR930010081B1 (en) Double stack capacitor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
CFP Corrected version of a pamphlet front page
CR1 Correction of entry in section i

Free format text: PAT. BUL. 02/2002 UNDER (30) REPLACE "09/608540" BY "09/609472"

AK Designated states

Kind code of ref document: C1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: C1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase in:

Ref country code: JP