WO2002001570A1

WO2002001570A1 - Call out memory with reduced surface

Info

Publication number: WO2002001570A1
Application number: PCT/IL2000/000327
Authority: WO
Inventors: Yves Emmanuel Villaret; Shmuel Prokopets
Original assignee: Memcall Inc.
Priority date: 2000-06-07
Filing date: 2000-06-07
Publication date: 2002-01-03
Also published as: AU5098900A; EP1295296A1; CN1375102A; IL147999A0; JP2004502265A

Abstract

A memory system and method that enables locating memory cells that contain a searched data using a limited number of lines and thus reducing the necessary memory surface while at the same time accelerating the search process by limiting the search to cells having a predefined characteristic. The memory system comprises an address bus and a data bus, a row selector and a column selector and a two dimensional array of memory cells, each memory cell comprising a masking circuit, a comparator circuit, a memory bit for storing the comparison results and in some embodiments the cell also comprises a range circuit. The memory may be operated in a read and write mode or it may be operated in a novel, fast search mode.

Description

Call Out Memory with Reduced Surface

Field of the Invention

The present invention relates to memories with a Call Out function or Call Out Memories (COM). In the framework of the present application a Call Out function is defined as a function of searching a memory wherein: 1) among the total of memory cells a number of cells is selected on which a search can be performed 2) a value to be searched is presented on a bus 3) the memory returns on a bus the address of one memory cell having matching data, that memory cell being the one with the highest address in a predefined direction among all the selected cells. The Call Out function eliminates the need to scan all the memory cells in order to locate those containing the requested data, whereby operation time is considerably reduced. Examples of memories with a Call Out function have been described in Patent Application PCT/IL 00/00121 to MemCall. The Call Out Memory of PCT/IL 00/00121 has a parallel organization wherein each cell is independently connected to an Address bus, a Data Bus and an Origin Bus. As a result, response time becomes independent of memory size, of the position of the searched data or the number of logic gates necessary to implement the "Call Out" function.

The Call Out Memory of PCT/IL 00/00121 is characterized in that the data to be searched is set on the address bus. When the device operates in the "Call Out" mode, each memory cell performs a comparison between Data conveyed to the cell by the Address lines and Data stored in the cell. In case that the Comparison results in a "Match" condition for several cells, then the Address of a single Matching Cell is set on the Data Bus. That particular cell must verify the condition of having 1)_ an Address Value smaller in a predefined direction than a preset, so called Origin Value, and 2)_ having the closest Address Value to this Origin Value among all cells with Matching Data and verifying condition 1). The cycle may then be repeated with the Matching Cell that has been set on the Data Bus as the new Origin and the process can be repeated again and again until all matching cells are found. A "Call Out" device as described in PCT/IL 00/00121 may also be operated in a so called Normal mode, wherein its function is similar to a standard Memory of one of the known types.

It will be understood by those versed in the art that the Call Out Memory device of PCT/IL 00/00121 requires a considerable number of lines in order to enable the Call Out function.

In a the Call Out device of PCT/IL 00/00121 each individual cell performs a comparison of the Data set on the Address Bus and the data stored into that cell. It is thus required that each memory cell be connected to a number of Address lines.

Further, each memory cell performs a comparison of its own Address with the Origin Address value, whereby if the Cell Address is inferior to the Origin Address in a predefined direction, then and only then a Priority Mask circuit within the cell is enabled. This function requires that an additional number of lines be used and connected to each memory cell, in order to convey the Origin Address value to each cell.

The Priority Mask circuit then selects the bits to be output to the Data Bus by a process wherein all set bits of all memory cells storing the searched data and fulfilling the requirement of the cell address being smaller than the "Origin" address are combined in an "OR" function to set the correspondent bit of the Data Bus. The overall function of the "Bit Mask" circuit is to mask the bit outputs that would cause a change in the bits of a higher address in case that they were output on the Data Bus together with that higher address. As a result, the final data seen on the Data Bus will be equal to the Address of the cell with the highest address but smaller than Origin and containing the data that match the data applied on the Address Bus.

It is therefore necessary, in order to enable the Call Out function in a system designed according to Patent PCT/IL 00/00121, that several Address Lines and several Origin Lines be connected to each of the Memory Cells respectively.

In case that a COM device is implemented in the form of a chip, each memory cell will have to be given a sufficient surface S 1 in order to provide routing space for all Address and Origin lines. In order to implement the logic functions of each memory cell, another minimum space S2 is required. Where S2 is larger than SI, it may be possible to connect the above address and origin lines to each Memory Cell, without any increase of the surface requirement. However if SI is larger than S2, then the routing of the Address lines and Origin lines will require a space for each memory cell that exceeds the space that would have been sufficient for performing the logic functions of the cell.

It will be understood that such additional space requirement will reduce the total number of cells that can be installed on one chip, thus reducing COM capacity. Also cost per memory cell will be increased.

It is therefore desirable to design a memory with a Call Out function wherein the number of lines connected to each memory cell is reduced.

It is known to arrange memoiy cells in a two dimensional array, such that each cell is selected by one Row and one Column, (see "Introduction to nMos and CMOS VLSI System Design", Amar Murkherjee, Prentice-Hall, Chapter 8.3). This method allows the addressing of one memory cell by means of two lines only, one Row and one Column. The logical function used to select the cell is very simple, being a simple AND function of Row and Column set state. This simplified select function reduces the surface needed for each cell, since only a simple logical AND function is needed at each Memory Cell.

It would be desirable to use a similar method and design in a Memory with a Call Out function, thus reducing the number of logical gates required and enabling the implementation of Call Out devices, for example chips, with an increased number of Memory Cells without an increase in the size of the Memory device.

Summary of the Invention

The present invention relates to a system and method of implementation of a Call Out memoiy that enables reduction of the memory cell surface, thereby increasing the number of memory cells for a device of a given surface.

The reduction of memory surface is achieved by reducing the number of lines that need to be connected to each memory cell. Each of the memory cells of the inventive Call Out system comprises a Priority Mask circuit similar to that described in Patent PCT/IL 00/00121, but the memory is constructed in accordance with a novel design wherein the Address Lines are neither routed nor connected to each memory cell separately. Instead, only one "Row" and one "Column" are routed to each memory cell, in accordance with a two dimensional array often applied in conventional memories.

In the inventive Call Out system the same "Row" and "Column" can also be used to implement the Range function. Using the said Row and Column, each memory cell performs the function of comparing its own address value with the Origin Address, and selectively enables the Priority Mask for that cell according to the result of that comparison. Due to the inventive design, the need for routing of the Origin lines to each memory cell is eliminated, and further reduction of Cell Surface is achieved.

The inventive method may be exemplified by three preferred embodiments. All embodiments are Call Out devices with a reduced number of lines routed to each memory cell. In the first two preferred embodiments the Searched Data is presented on the Data Bus, the Origin Address Value is presented on the Address Bus, and the comparison result of each memory cell is stored in a dedicated one-bit memoiy cell added to each Memory Cell of the device.

In the first embodiment, a Call Out memory is implemented wherein the Address lines are not connected to the Memory Cells, and the Cells are arranged in Rows and Columns as known for certain standard memoiy devices while the system still enables the device to carry out the Call Out functions.

In a second embodiment, a further improvement is implemented, according to which neither the Address lines nor the Origin Lines are comiected to the memory cells. In this second embodiment the Range function of the Call Out device is assisted by selective setting of the said Columns and Rows in accordance with a predefined relationship with the origin address.

In a third embodiment, the range circuit is not used such that a further reduction of surface is achieved. Instead, a memory bit within the cell is used to select the cells according to the needs of the memory and disable them for a subsequent call out search or the cells may be disabled by a designated line. Brief Description of the Drawings.

Fig 1 is a schematic drawing of a Call Out memory in which Address Lines are not routed to each memory cell.

Fig 2 is a block diagram of a circuitiy with a memory cell according to the embodiment of Fig. 1

Fig 3 is a schematic drawing of a Call Out memoiy in which Origin Lines are not routed to each memory cell.

Fig 4 is a block diagram of a circuitry with a memory cell according to the embodiment of Fig. 3.

Fig 5 is a diagram of a Range Circuit in a cell within a Call Out Memory according to the embodiment of Fig. 3.

Fig 6 is a schematic drawing of a cell within a Call Out memory implemented without a Range circuit

Fig 7 is a diagram of a Bit Mask circuit for the embodiment of Figs. 1 and 2

Fig 8 is a diagram of a Bit Mask circuit for the embodiment of Figs. 3 and 4

Fig. 9 shows a detailed example of a Priority Mask circuit

Detailed Description of the Preferred Embodiments

The purpose of the present invention is to provide a method and system for a memory whereby the Call Out function may be performed with a reduced number of logical gates and a reduced number of connection lines. The term Call Out function is used to designate a method of searching for data in a memory or part of it wherein among the total of memory cells a number of cells is selected on which a search can be performed; a value to be searched is presented on a Bus, for each selected memory cell a comparison is performed between the said value and the Data stored in the cell; in case that the Comparison results in a "Match" condition for several cells, then the address of a single Matching Cell with the highest address among all the selected cells is set on a Bus and the cycle may be repeated again and again until all matching cells are found. In a first embodiment of the inventive system, shown in Fig 1 , Memory Cells are arranged in a two-dimensional array, i.e. in rows and columns. Each Memory cell is then connected to several Data Bus lines, to several Origin Lines, and to one Column Line and one Row Line. Additional control lines, such as a Read/Write line, are also connected to each cell. Each Memory Cell comprises a Data Storage Circuit, a Comparator, an added bit of memory that will be referred to hereinbelow as Comparison Result Storage Bit, a Range Circuit and a Bit Mask Circuit.

It is known from standard memories that in such a two dimensional array the column lines need not necessarily be connected to each of the memory cells of the column. A further variation of the first preferred embodiment is therefore suggested wherein the column lines are used to connect the bit lines of the Data Bus to the memory cells of the column by means of transistor switches rather than the column lines being connected to each individual memory cell of the column (see "Introduction to nMos and CMOS VLSI System Design", Amar Murkherjee, Prentice-Hall, Chapter 8.3).

The above described methods and any other similar method, used in the art to selectively activate cells within a Row or a Column will be further referred to as Row Select or Column Select whereas a Row or a Column selected by the said methods will be referred to as Selected Row or Selected Column.

The inventive system can be operated in two modes, Normal mode and Call Out mode.

In the Normal Mode, Data can be transferred to or from a Memory Cell as for standard memories, i.e. an address set on the address bus is processed, and one column and one row are selected. The memory cell selected by these Row and Column is then selected for the Data transfer to or from the memory, according to the state ofthe R/W line.

In the Call Out mode, a Data search operation is performed in two steps:

During the first step, the system is placed in the Call Out mode and Write cycle. During this first step the Origin Address value is set on the Address Bus, while the Searched Data is set on the Data Bus. The Origin Address value is stored in a dedicated register, Origin Address Register. Also during that first step, each memory cell is activated to perform a comparison between the Data set on the Data Bus and the data stored in that cell by means of a Comparator The result of the comparison is then stored in the Comparison Result Storage bit.

During the second step, the system is placed in the Call Out mode and Read mode. In this mode the Range Circuit and the Comparison Result Storage bit selectively enable the Bit Mask circuit to output the Cell Address to the Data Bus.

It is the advantage of the invention according to the first embodiment that a large number of lines is eliminated whereby the design of Call Out memories with an increased amount of memory cells is made feasible. It is another advantage of the invention that the size of a Call Out memory device may be reduced without reducing the number of memory cells within the device.

In a second embodiment, Memory Cells are also arranged in rows and columns. However no Origin Address lines are connected to them. The same first and second steps are used in the Call Out mode, as in the case of the first embodiment. However the implementation of the Range function is now assisted by the Row and Column lines as shown in Fig. 5.

Each Memory Cell, at Line r and Column c, receives as input two Rows r and r+1, and one Column c. A circuit common to all the cells of the device will select the Rows and Columns in the following way: If Origin Address is the address of Memory Cell at Row rO and Column cO, then all Rows r with r < rO will be set to logic state 1, and all Columns c with c < cO will be selected. All other lines will remain unselected.

The Range Circuit within the individual cell then outputs an enabling signal to the Comparator if the Rows and Columns input of the cell satisfies the following conditions: Row r+1 is selected, Or, r+ 1 is not selected but r and c are both selected.

In this second embodiment, Origin lines do not need to be routed to each memory cell. Instead, each memory cell is additionally selected by the next Row line r+1. This does not create difficulties in the routing, since the r+1 Row is a neighboring Row. Also the Range function is implemented in a very simple way, thus reducing the number of logic gates in each Memory Cell. In a third embodiment, the Range function is eliminated, whereby the memory surface is further reduced. Instead, a memory bit is used to select the cells and disable them for subsequent search. In accordance with one design envisaged for this embodiment, the memory bit that is used to select the cells and/or disable them for subsequent search is the Comparison Result Storage bit.

The inventive method and device have the advantage of reducing the cell surface for a Call Out memory device. As the Call Out memory considerably reduces operation time by eliminating the need to scan the whole memoiy in order to find the searched data, the device and method of the invention have the double advantage of being both time and space saving.

The inventive device has the further advantage of saving costs by reducing the amount of lines and gates necessary for implementing the Call Out function whereby manufacture is simplified and manufacture time is reduced.

The invention will now be described in detail in respect of the preferred embodiments and with reference to the drawings. It will be understood however that many modifications and applications of the invention may be envisaged that still remain within the scope of the specification and the claims.

In reference to Fig 1, a first embodiment is shown. In that first embodiment, Memory Cells are arranged in Rows and Columns. Two modules, namely a Row Selector and a Column Selector, are used to select Rows or Columns. The Row Selector and Column Selector are commonly used in Memory devices (see "Introduction to nMos and CMOS VLSI System Design", Amar Murkherjee, Prentice-Hall, Chapter 8.3). Data Bus Lines are also connected to each Memory Cell.

A dedicated storage section, Origin Register, is defined and used to store an Origin Address value. A set of Lines, called Origin Lines, is connected to each Memory Cell. These Origin Lines are also connected to the Origin Register, so that the Origin Address Value may be set on the Origin Lines. The ensemble of Address Bus, Data Bus and Control Lines will be referred to as Bus System. The Control Lines comprise a Read/Write Line that is used to define a Read or Write cycle for the Bus System as known for conventional memories.

Referring now to Fig. 2, the Call Out memory of the first embodiment comprises three modules: Row Selector, Column Selector and Origin Register that provide an interface to the System Bus.

These modules are comprised in the Common Circuitry of the device. It will be understood that a memory device comprises a large number of Memory Cell circuits although Fig. 2 only shows the Common Circuitry, and one Memory Cell at a given Row r and Column c.

Each Memory Cell comprises the following elements:

A Data Storage Circuit. This circuit is used to store the Data, and it is similar to equivalent circuits in memory cells commonly used in the art.

A Comparator circuit. The Comparator checks whether Data set on Data Bus and Data in the Data Storage Circuit verify a given relationship. This given relationship may be of any kind, for example Bigger than, Smaller than, Equal or any other relationship. The given relationship may be predefined, or set by some control lines, or set by a specific Bus Cycle operation. If the given relationship is verified, then a Match Signal is output to a Comparison Result Storage circuit. This circuit is a one bit memory, storing the result of the comparison.

As shown in Fig. 2, the cell circuit further comprises a Bit Mask Circuit. This circuit is similar to that described in PCT/IL 00/00121 and it is shown in detail in Fig 6. The role of the Bit Mask Circuit is to output, when enabled, the Cell Address on the Data Bus. Since several Memory Cells contain matching data, an inventive feedback system is used in order to output on the Data Bus only one Address, that Address being the highest in a predefined direction, among all matching Memory Cells.

As seen in Fig. 2, the Bit Mask circuit comprises a Range circuit and a Priority Mask circuit. The Range circuit compares the Origin Address value with the Memory Cell Address value. If the Memory Cell Address value is "Lower", in a predefined direction, to the Origin Address value, then an enabling output is issued to the Priority Mask. "Lower" here is one of the following predefined relationships: "Smaller", "Smaller or Equal", "Bigger", "Bigger or Equal".

In the event of an enabling output by the Range Circuit, the Priority Mask circuit selects the bits to be output to the Data Bus by a process wherein all set bits of all memory cells storing the searched data and fulfilling the requirement of the cell address being smaller than the Origin address are combined in an "OR" function to set the correspondent bit of the "Data Bus" and finally only the bits selected by the Priority Mask circuit are passed through to the Data Bus. The resulting data seen on the Data Bus will then be equal to the Address of the cell with the highest Address but smaller than Origin and containing the Data that match the data applied on the Address Bus.

The Call Out Memory device can be placed in two modes, Normal mode and Call Out mode. In the preferred embodiment, a dedicated line CO is used for that purpose as shown in Fig. 2. It will be understood however, that any of the various methods or techniques known in the art can be used to set the operating mode of the Call Out memory.

In the normal mode, the function of the memory is similar to that of the various types of existing memories wherein the Address is set on the Address Bus, and the Data is set on the Data Bus. The Address is decoded by the Row Selector and Column Selector into one Column select and one Row select. The Memory Cell that is connected to both selected Row and Column is activated for Data Transfer to or from Data Bus, in the usual way known for memories.

In the Call Out mode, in a first step, the memory is placed in the Call Out mode and Write Cycle. In that first step, the Origin Address Value is set on the Address Bus, and the Data to be searched is set on the Data Bus.

During that first step, the Origin Address is stored in the Origin Register, the said Origin Register being activated to store the Address set on the Address Lines by the Call Out mode (CO) and the Read/Write line in the Write state. Also during that first step, the Data to be searched is set on the Data Bus. In each Memory Cell, the Comparator is enabled by the Call Out mode (CO) and the Read/Write line in the Write state. The Data stored in the Cell is compared to the Data on the Data Bus and in the event that there is a match, the Result Storage bit of that Cell is set to logic state 1 and stored. Otherwise the Result Storage bit is reset and stored.

In a second step of the Call Out mode, the Bus system is set to a Read cycle. Then the Range Circuit is activated to compare the Origin Address with the Memory Cell Address. If the Memory Cell Address is lower (or lower or equal) than the Origin Address, in a predefined direction, then the Range Circuit outputs an enabling signal to the Priority Mask. In case of a match the Priority Mask receives another Enabling signal from the Result Storage bit. The Priority Mask is enabled only if both Enabling signals are set.

Finally, as explained before, the address of the Memory Cell having a) matching data, and b) Address inferior (or inferior of equal) to the Origin Address, and having the highest address in a predefined direction among all Memory Cells verifying a) and b), will be output on the Data Bus.

In reference to Fig 3, a second embodiment is shown wherein the size of the memory device is further reduced by the Origin Lines not being connected to each memory cell. The device designed in accordance with the second embodiment has a similar function to that of first embodiment. The only difference is in the implementation of the range function that is now performed according to the state of the Row Lines and Column Lines. As shown in Fig 4, each Memory Cell Range circuit at Row r and Column c, receives as input two Rows r and r+1, and one Column c.

The Row Selector and Column Selector now have a function in the Call Out mode and Write Cycle, as explained in the following:

When both Call Out and Write cycle are set, an Origin Address value is set on the Address Bus. In Normal mode, that Address would be encoded as one Row rO and one Column cO being selected (set). In Call Out mode, all Rows r with r <= rO, and all Columns c with c <= cO are selected (set). While in the preferred embodiment r smaller or equal to rO and c smaller or equal to cO were chosen by way of example, it will be understood that any ordering relation can be chosen, such as smaller, bigger, bigger or equal, or other.

The Range Circuit then performs a simple logical function to output an Enabling signal. In this preferred embodiment the Enabling signal will be output if Row r+1 is selected, or if both Row Line r and Column Line c are selected.

Fig 5 demonstrates the inventive method of the second embodiment by showing the Range Circuit for nine Memory Cells, for Row Lines r, r-1 and r-2, and for Columns c+1, c and c-1. In this example, the Origin Address value is encoded as r and c, so that Rows r, r-1 and r-2 and Columns c and c-1 are selected (weighted in Fig 5). In accordance with the inventive method, the Range Circuit outputs an Enabling signal for eight Memory cells of Fig 5 (weighted cells). It is obvious that for the Range Circuit function, the roles of Rows and Columns may be reversed.

In this second embodiment, the Origin Address need not be stored. Instead, the Range function is partly performed during the first step of the Call Out mode, by the selection of memory cells that fulfil the condition of having an address that is lower than the Origin Address value as defined by the Row Line and the Column line of the said Origin Address. Where the cell is enabled by the Range Circuit, the enabling output signal is connected to the Comparator circuit. If the Range circuit enables the Comparator, and the Memory Cell has matching Data, then the Result Storage bit will be set, and the Priority Mask will be enabled at the next step, making that Memory Cell a candidate to Output its Address on the Data Bus.

As described for the first embodiment, the Priority Mask circuit selects the bits to be output to the Data Bus by a process wherein all set bits of all memory cells storing the searched data and fulfilling the requirement of the cell address being smaller than the Origin address are combined in an "OR" function to set the correspondent bit of the "Data Bus" and finally only the bits selected by the Priority Mask circuit will be passed through to the Data Bus. The resulting data seen on the Data Bus will then be equal to the Address of the cell with the highest Address but smaller than Origin in a predefined direction and containing the Data that match the data applied on the Address Bus. This second embodiment further demonstrates the advantages of the inventive system and method, achieving an even stronger reduction in the size of a memory device that is capable of performing a Call Out function.

In a third embodiment, shown in Fig. 6, the Call Out Memory device does not comprise a Range Circuit. Instead the Comparison Result Storage is used to inhibit the comparator in case that a match has already been found in a previous Call Out cycle.

In this embodiment, the Comparison Result Storage Bit is not reset at each Call Out Cycle instead it is reset upon specific events, these events being defined according to application requirements. Thus for example, an address that has already been searched may be disabled, upon request, for subsequent searches.

The Comparison Result Storage Bit may be provided with standard reading or writing means, depending on application requirements. Thus for example writing a new data to the particular cell may reset the Comparison Result Storage bit of that cell or a designated line may be used to reset all Comparison Result Storage bits of the memory device or any part of them.

It will be understood that many ways known in the art exist for setting a specific signal for each cell. Such signal may then be used to disable or enable the comparing function of the cell, thus providing means to skip specific cells during the Call Out cycle.

In Fig. 7, a Bit Mask Circuit for a Memory Cell of the first preferred embodiment is shown with a Range Circuit connected to an Origin Address Line, an OR logical circuit comiected to a Data Bus and a Priority Mask Circuit, also connected to the said Data Bus.

As explained before, the Range Circuit performs a comparison between the Address of the specific cell with the Origin Address. If the Origin Address is bigger in the predefined direction, then this circuit outputs an enabling signal. Another Enabling signal El is issued when the device is placed in the Call Out and Read mode.

A third Enabling signal E2 is issued from the Comparison Storage bit.

An And function gathers these three enabling signals, and outputs a final Enabling signal to the Priority Mask. This ensures that the Priority Mask will be enabled if and only if the three following conditions are fulfilled: a)The device is placed in the Call Out and Write mode b) The cell Address is smaller than Origin Address (in predefined direction) c)The data presented on Data Bus during previous Call Out and Write cycle was found matching the data stored in the Cell.

Referring now to Fig. 8, a Bit Mask circuit for a Memory Cell of the second preferred embodiment is shown, with an OR logical circuit connected to a Data Bus and a Priority Mask Circuit, also connected to the said Data Bus. In this embodiment an enabling signal is produced if the device is put in Call Out and Read mode and the Comparison Result Storge bit is set. The enabling signal is then applied to the Priority Mask.

In Figs. 7, 8 and 9, the cell Address is represented by N. N can then be written in the form:

K

k=0

Where u(N,k) represents the set digits of the binary presentation of N and may take the values 0 to W - 1 (W being the number of bits used to represent the cell address); k+1 is the number of set bits for the specific address value N and B[U] represents the value (0 or 1) of bit u of the Data Bus.

The operation of the Priority Mask Circuit when enabled is as follows:

As shown in both Figs. 7 and 8, all P[M,u(N.k)] lines, from all memory cells (M) having bit u(N,k) set, are input to the said OR logical circuit, and the output of that circuit is set on the Data Bus as bit u(N,k). M is a generic that represents the addresses of all the cells of the device having bit u(N,k) set. At the beginning of a Call Out Cycle, the Data Bus lines B[0] to B[w-1] are in an inactive (Logical 0) initial state. For example, if we use negative logic, all lines are "Pulled Up" by a resistor to the plus system power supply. In a first step the priority mask senses all these lines as inactive, and outputs the P[N,u(N,k)]. In that first step, many other cells may also set the Data Bus line by means of the OR circuit. This new state of the Data Bus will then be sensed by each of the cell Priority Mask Circuits respectively and some of the P[N,u(N,k)] lines will be deactivated, according to the rules of the priority mask. Finally, bits P[N,u(N,k)] that are not set in the address of the highest cell storing the searched data will be reset, and the Data Bus will be set to that highest cell address.

As a result of the above process, the "Priority Mask" will reset all P[N,u(N,k)] lines to zero logical state if one of the following conditions is not satisfied:

_ The Cell Address is higher or equal to the Origin address.

_ The Data Stored in Cell is equal to data presented on the Data Bus.

_ The device is not in the "Call Out" mode.

This process is asynchronous; the time needed for the lines to stabilize to their steady value is of the same order as the rising time of the electronic components of the circuit. As a result, the time required to search one data is of the same order as a normal read or write cycle.

Referring now to Fig. 9, the "Priority Mask" circuit is shown in detail. The "Priority Mask" circuit of Fig. 9 outputs bit P[N,u(N,k)] if the following conditions are satisfied:

For the highest bit set: u(N,K) a)_if the "E" signal is active. b)_AND if all bits of the Data Bus higher than u(N,K) are not set.

If there is no higher bit, i.e. if the highest bit is bit W-l (where W designates the number of bits used to represent the cell address), then this bit is directly set by the "E" signal. For other bits: u(N,k), k<K a)_the higher bit u(N,k+l) is set b)_AND all bits of the internal bus B[u(N,k)] between present bit u(N,k) and higher bit u(N,k+l) are not set.

This ensures that if another cell with a higher address has output its address on the Data bus, at bits that are not set ib the present cell, then bits k and lower of the present cell address are not output. Finally only bits that are set in the highest matching memory will be output.

It will be understood that the above is described for a downward search and where the system is defined to conduct an upward search it is the lowest matching memory that will be output on the Data Bus.

The inventive memory system and method have the advantage of being compatible with commonly used computer devices and therefore applicable in a wide variety of electronic systems such as computer systems, communication systems, and many other systems wherein it may be used together with or in replacement of standard memory devices of different types.

Claims

Claims:

1. A memory system comprising an address bus and a data busand a two dimensional array of memory cells arranged in rows and columns such that each memory cell can be selected by at least one row and one column, each of the said memory cells being connected to a plurality of data bus lines and each of the said memory cells comprising a comparator circuit, a masking circuit and a plurality of memory bits whereby the said memory system may be operated in a read and write mode or it may be operated in a search mode wherein:

(a) each of the memory cells performs a comparing function whereby data set on the data bus are compared with the data stored in the cell and the result is stored in a memory bit that is set when the result is a match;

(b) each of the said memory cells performs a function that limits the search to cells having a predefined characteristic by selectively sending an enabling signal to either the said masking circuit or the said comparator circuit when the said characteristic is verified;

(c) the said masking circuit performs a masking function that results in the cell that is highest in a preset direction and verifies the said predefined common characteristic being selected for its address to be put on the data bus;

(d) the said process may be repeated until several matching cells have put their addresses on the said data bus.

2. A memory system according to claim 1 hereinabove wherein each of the memory cells further comprises a range circuit, the said predefined characteristic is a predefined relationship with a preset origin address and in the said search mode:

(a) The said range circuit performs a range function that verifies the said predefined relationship with the said preset origin address and selectively sends the said enabling signal to the said masking circuit;

(b) The said masking circuit performs a masking function that results in the cell that is highest in a preset direction and verifies the said predefined relationship with the origin address being selected for its address to be put on the data bus;

(c) the said process may be repeated with a different origin address until several matching cells have put their addresses on the said data bus.

3. A memory system according to claim 2 wherein the said memory system also comprises a designated register and each of the said memory cells is further connected to an origin line and in the said search mode:

(a) In a first step the said origin address value is put on the address bus and stored in the said designated register and the data to be searched is conveyed to the memory cells by the said data bus lines for performing the said comparing function;

(b) in a second step: i. The said range function is performed by a designated range circuit that directly performs the comparison between the origin address received through the origin lines and the cell address to verify the said predefined relationship; ii. in the event that the information stored in the said memory bit is a match condition and the range circuit verifies the said predefined relationship, the said masking circuit is enabled and performs a logic function comparing the cell address to the addresses of other matching cells with the result that the address that is highest in a preset direction and verifying a predefined relationship with a preset origin address is put on the data bus;

4. A memory system according to claim 2 wherein the said memory cells are not connected to any origin lines and each memory cell receives as input two adjacent rows and one column and in the said search mode: a. in a first step: i. the data to be searched are conveyed to the memory cells by the said data bus lines for performing the said comparing function and an origin address value ro;co is put on the address bus; ii. the said origin address value is encoded such that all rows equal to or lower than the origin address row (r<=ro) or all rows lower than the origin address row (r<ro) in a predefined direction and all columns equal to or lower than the origin address column (c<=co) in a second predefined direction or all columns lower than the origin address column c<co are selected; b. in a second step: i. the said range circuit within each of the matching cells performs a range function to verify a predefined relationship of the cell address with the said previously set rows and columns such that a cell r;c will be enabled only where the row that is adjacent to the cell row and exceeding the cell value by one order in a predefined direction is selected or if both row r and column c are selected or the column that is adjacent to the cell column and exceeding the cell value by one order in a second predefined direction is selected; ii. the address of the enabled cell is set on the said data bus; c. the said process may be repeated with a different origin address until several matching cells are found.

5. A memory system according to any of the preceding claims wherein the said memory bit storing the comparison results remains unchanged after it was set in a first cycle and in a second cycle a logical combination of the said memory bit with the comparator enabling signal will disable the comparator for that cycle, whereby any address that was already searched may be disabled for subsequent searches without the need for a range function.

6. A memory system according to claim 1 hereinabove wherein the said memory bit storing the comparison results is provided with standard reading or writing means, whereby the search may be limited to cells having a predefined characteristic by writing new data to a particular cell to reset the said memory bit of the said cell such that the said memory bit sends an enabling signal to the said masking circuit.

7. A memory system according to any of the preceding claims wherein a designated line is used to reset a multiplicity of the said memory bits that store the comparison results whereby the search will include all the cells connected to the said designated line.

8. A memoiy cell within a two dimensional array of memory cells, the said cell receiving a Data Bus Line, an Origin Bus line, one or more Control lines, a Row and a Column and comprising a memory circuit with a Comparator, a comparison result storage bit, a Range Circuit and a Priority Mask circuit, wherein the data to be searched is conveyed to the memory cells by the said Data Bus and compared with the cell data by the said Comparator, the result is stored in the said Comparison storage bit and the said Range Circuit checks a predefined relationship between the cell address and an Origin Address whereby in the event that the information stored in the said Memory Bit is a match condition and the said Range Circuit verifies the said predefined relationship, the said Masking Circuit is enabled to perform a logic function comparing the cell address to addresses of other matching cells with the result that the address of the cell that is highest in a preset direction and verifying a predefined relationship with a preset origin address is put on the said Data Bus.

9. A memory cell within a two dimensional array of memory cells, the said cell receiving a Data Bus Line, one or more Control lines, a Row and two Columns and comprising a memory circuit with a Comparator, a comparison result storage bit, a Range Circuit and a Priority Mask circuit, wherein the data to be searched is conveyed to the memory cells by the said Data Bus and compared with the cell data by the said Comparator, the result is stored in the said Comparison storage bit and the said Range Circuit checks a predefined relationship between the cell address and an Origin Address that is conveyed to the cell by the states of the said Row and Columns and the said Control lines whereby in the event that the information stored in the said Memory Bit is a match condition and the said Range Circuit verifies the said predefined relationship, the said Masking Circuit is enabled to perform a logic function comparing the cell address to addresses of other matching cells with the result that the address that is highest in a preset direction and verifying a predefined relationship with a preset origin address is put on the said Data Bus.

10. A memory cell according to Claim 5 wherein the said memory cell is connected to a single Column and two Rows.

11. A memory cell according to any of claims 7-9 that does not have a range circuit and that may be selectively disabled by data written to the Comparison Storage bit.

12. A memory cell according to claim 10 that is disabled for a second cycle after it has been searched during a first cycle by a logical combination of the said Comparison Storage bit and the comparator enabling signal.

13. A method for searching memory cells in a memory system comprising an address bus and a data bus, a row selector and a column selector and a two dimensional array of memory cells, each memory cell being connected to at least one row and one column and a plurality of data bus lines whereby the said memory system may be operated in a read and write mode or it may be operated in a search mode comprising the following steps: a. each of the memory cells performs a comparing function whereby data set on the data bus are compared with the data stored in the cell and the result is stored in a memory bit that is set when the result is a match; b. each of the said memory cells performs a range function that limits the search to cells having a predefined characteristic by selectively producing an enabling signal when the said characterisic is verified; c. each of the said memoiy cells performs a masking function that results in the cell that is highest in a preset direction and verifies the said predefined relationship with the origin address being selected to put its address on the data bus; d. the said process may be repeated until several matching cells have put their addresses on the said data bus.

14. A method for searching memory cells in a memory system according to claim 2 hereinabove wherein the said predefined relationship is a predefined relationship with a preset origin address and the search comprises a range function according to the following steps: a. each of the said memory cells performs a range function that verifies the said predefined relationship with the said preset origin address and selectively generates an enabling signal; b. each of the said memory cells performs a maslcing function that results in the cell that is highest in a preset direction and verifies the said predefined relationship with the said origin address being selected to put its address on the data bus; c. the said process may be repeated with a different origin address until all matching cells have put their addresses on the said data bus.

15. A method for searching memory cells in a memory system according to claim 3 comprising the following steps: a. In a first step an origin address value is put on the address bus and stored in a designated register and the data to be searched is conveyed to the memory cells by the said data bus lines for performing the said comparing function; b. in a second step: i. The said range function is performed by a designated range circuit that directly performs the comparison between the origin address received through the origin lines and the cell address to verify the said predefined relationship; ii. in the event that the information stored in the said memory bit is a match condition and the range circuit verifies the said predefined relationship, a masking circuit is enabled that performs a logic function comparing the cell to other matching cells with the result that the address that is highest in a preset direction and verifying a predefined relationship with a preset origin address is put on the data bus; c. the said process may be repeated with a different origin address until several matching cells have put their addresses on the said data bus.

16. A method for searching memory cells containing a searched data in a memory system according to claim 3 wherein the said memory cells are not connected to any origin lines and each memory cell receives as input two adjacent rows and one column whereby during the said second process: a. in a first step: i. the data to be searched are conveyed to the memory cells by the said data bus lines for performing the said comparing function and an origin address value r0;c0 is put on the address bus; ii. the said origin address value is encoded such that all rows equal to or lower than the origin address row (r<=r0) or all rows lower than the origin address row (r<r0) in a predefined direction and all columns equal to or lower than the origin address column (c<=c0) in a second predefined direction or all columns lower than the origin address column c<c0 are set;

b. in a second step: i. the said range circuit within each of the matching cells performs a range function to verify a predefined relationship of the cell address with the said previously selected rows and columns such that a cell r;c will be enabled only where the row that is adjacent to the cell row and exceeding the cell value by one order in a predefined direction is selected or if both row r and column c are selected or the column that is adjacent to the cell column and exceeding the cell value by one order in a second predefined direction is selected; ii. the address of the enabled cell is set on the said data bus; c. the said process may be repeated with a different origin address until all the matching cells are found.

17. A method for searching memory cells containing the searched data in a memory system according to claim 1 wherein the search is limited to cells that haven't been searched in a first cycle by the memory bit within the cells that stores the comparison results remaining unchanged after it was set in the said first cycle, and in a second cycle a logical combination of the said memory bit with the comparator enabling signal disabling the comparator for that cycle, whereby any address that has already been searched may be disabled for subsequent searches without the need for a range function.

18. A method for searching memory cells containing the searched data in a memory system according to claim 1 wherein the search is limited to cells having a predefined characteristic by providing the said memory bit that stores the comparison results with standard reading or writing means, and writing new data to a particular cell to reset the said memory bit of the said cell such that the said memory bit sends an enabling signal to the said masking circuit.

19. A method for searching memory cells containing the searched data in a memory system according to any of the preceding claims wherein a designated line is used to reset a multiplicity of the said memory bits that store the comparison results of a previous search whereby the search will include all the cells connected to the said designated line.