WO2001099139A1

WO2001099139A1 - Method for measuring wall charge and wall voltage on plasma display panel

Info

Publication number: WO2001099139A1
Application number: PCT/KR2001/001074
Authority: WO
Inventors: Min Soo Kim; Young Woo Seo; Byung Guk Kim
Original assignee: Orion Electric Co., Ltd.
Priority date: 2000-06-23
Filing date: 2001-06-22
Publication date: 2001-12-27
Also published as: KR20020003907A

Abstract

The invention relates to a method for measuring wall charge and wall voltage on a plasma display panel. According to the invention, after a plasma display panel is electrically connected to an external capacitor in serial manner, the power supply voltage is applied to the plasma display panel and the external capacitor. Then, the voltage between the both ends of the plasma display panel and the voltage between the both ends of the external capacitor are measured respectively. Thereafter, the wall voltage and the wall charge of the plasma display panel are measured using the measured voltage between the both ends of the plasma display panel and the measured voltage between the both ends of the external capacitor. Here, the wall voltage is presumed to be a dependent voltage of the power supply voltage.

Description

METHOD FOR MEASURING WALL CHARGE AND WALL VOLTAGE ON PLASMA DISPLAY PANEL

Technical Field

The present invention relates to a plasma display panel. In particular, the present invention relates to a method for measuring wall charge and wall voltage on the ■ plasma display panel. The wall voltage, which is a discharge control element of an AC plasma display panel with the surface discharge electrode structure, is redefined and thus the exact measurement of wall charge and wall voltage is made possible.

Background Art

The plasma display panel ("PDP") is a device that displays characters or graphics using the light from plasma generated upon gas discharge. Recently, more and more plasma display panels are used for wall-type super large television sets and for high definition medium or large monitors.

The panel structure of an AC PDP with the general surface discharge electrode structure is illustrated in Fig. 1. The PDP shown in Fig. 1 comprises the display side front glass substrate 10 and the back glass substrate 20 sealed together. Discharge gas is injected in the internal space between the glass substrates 10, 20. On the surface of the glass substrate 10, a SiO₂ layer 11 is formed. Upon the layer 11 for each cell are placed X and Y electrodes 13, 14 with certain distance from each other for the purpose of the maintaining discharging. The dielectric layer 15 is placed upon the X and Y electrodes 13, 14, and a protection layer of MgO material 17 is deposited upon the dielectric layer 15. Here, the X electrode 13 is composed of the sustain electrode 131 which is a transparent electrode of ITO material and the bus electrode 133 to compensate for the resistance of the sustain electrode 131. The Y electrode 14 is composed of the sustain electrode 141 which is a transparent electrode of ITO material and the bus electrode 143 to compensate for the resistance of the sustain electrode 141. Reference numeral 19 illustrates black stripes.

On the other hand, the address electrodes 21 are placed upon the glass substrate

20 for the data recording. Upon the address electrodes 21, the dielectric layer 23 is placed. Upon the dielectric layer 23, the separating walls 25 are placed in the form of stripes in order to prevent the optical cross-talk. The fluorescent layer 27 is formed upon the sides of the separating walls 25 and on the surface of the dielectric layer 23.

In the PDP with the above-described structure, when the pulse power is applied to the X and Y electrodes 13, 14 and the power is applied to the address electrode 21, the discharge gas is discharged in the discharge space of the relevant cell shown as dotted lines and thus the ultraviolet rays 1 are generated. Accordingly, the fluorescent layer 27 emits the light 3, and the visible rays 5 are outputted through the glass board 10.

As a method to control discharge in the PDP of the above-described structure, the method of using the wall charge cumulated upon the dielectric layer surface of a cell's discharge space has been widely used. In other words, the memory effect of the wall charge has been utilized. The amount of the wall charge changes when there is discharge caused by pulses supplied to the relevant cell. The changed amount of the wall charge remains on the surface of the dielectric layer. The wall charge, which has remained inside the cell from the initial state prior to the discharge, reacts with the pulses supplied subsequently and thus affects the discharge.

In the above-described PDP, the exact and correct information regarding wall charge and wall voltage must be obtained in order to effectively perform the discharge. However, no clear definition of the wall charge and wall voltage has been presented so far. Furthermore, neither any measuring method nor the value of wall charge or wall voltage has been suggested so far. As an example, Mitsubishi Electric Corporation introduced a method to measure wall voltage of a surface discharge AC PDP in a PDP's cell illustrated in Fig. 2 in "T.IEE. Japan, Vol. 118-A, No. 5. '98" and "T.IEE. Japan, Vol. 119-A, No. 1. '99." The cell's equivalent circuits prior to and after the discharge are as illustrated in Fig. 3 and Fig. 4. The Lissajous diagram is implemented through the discharge current measured therefrom and the wall voltage N is defined as follows.

v ^w = M 2C

Also, Mitsubishi Electric Corporation first suggested in "IDW '97 PDP 2-4" that the changes in the amount of the wall charge caused by the changes in the voltage of the address electrodes may be observed during the X and Y's sustain discharge periods, if a capacitor is electrically connected to the address electrode and the voltage at the both ends of the panel is measured.

Additionally, Mitsubishi Electric Corporation suggested in "IDW '97 PDP p-3" the wall voltage calculation method using the waveform, which is similar to Weber's experiment previously announced in 1986. The method is to apply a pulse in a setup phase first and then an erase pulse. Then, a testing pulse is applied inducing the change in the wall voltage. Thereafter, the wall voltage is measured upon the sustain pulse. Plasma Inc. introduced, in "L.F. Weber, Measurement of Wall Charge and Capacitance Variation for a Single Cell in AC Plasma Display Panel, IEEE Trans. Electron Devices Vol. ED 24, No. 7, pp. 864-869, 1977," a method by which a capacitor is electrically connected to the outside of a panel for the measurement of the change in the internal wall charge. In this method, the voltage difference in displacement-current component and discharge current component is measured by the amount of light. Thus, the relative amount of the wall charge may be measured. Then, the capacitance at the discharge gap is measured. Thereafter, through the calculation with the two values, the relative change in wall voltage is detected and resultantly the wall voltage is measured. Moreover, in "L.F. Weber, Quantitative Wall Voltage Characteristics of AC

Plasma Displays, Proc. SID. Vol. 27/3, 1986," Plasmaco Inc. controlled the value of wall voltage by regulating the applied voltage of the setup phase and attempted to apply the wall voltage to certain waveform to be tested and then to measure the changes in the output wall voltage. In this method, a threshold value determining the on or off state at a determinant phase of a certain waveform is set. Then, Ndc offset is controlled to measure the changes in the output wall voltage of the applied waveform. Thus, the relative values of 'Nwout' relating to the particular waveform are compared and as a result, the WNIO curve may be obtained.

Furthermore, in "L.F. Weber, Plasma Display Device Challenges, ASIA DISPLAY '98. 3. 2 page 15," Plasmaco Inc. provides the detailed explanations of WNIO curves and the design standard of the_. ramp waves. However, Plasmaco Inc. fails to provide any method for directly measuring wall voltage.

In "T.S. Cho, et al, Influence of Driving Frequency on the Electrical Characteristics in Surface Discharge AC-PDPs, IDW' 99, PDPp2-7 page 728," wall voltage Vw of a PDP is defined as follows.

c o

" Chapter 2 of the book on the theme, ' Plasma Display' which published by the Japanese Public Publishing Coφoration in Oct. 11, 1983 " provides a model of a PDP's cell as illustrated in Fig. 5. The equivalent circuits of the cell prior to and after discharge are as illustrated in Fig. 6. Where Vs(t) is sustain voltage and Vw(t) is wall voltage, the wall voltage Vw(t) may be expressed as follows.

Here, as illustrated in the equivalent circuit of Fig. 6, Is(t) equals Ic(t)+Iw(t). Thus, the wall voltage Vw(t) may be expressed as follows.

Vw(t) = \ Ic(t)dt+ Iw(t)dt

KCo L J

Here, it is assumed that Cc « Co and Ic(t) « Iw(t). Thus, disregarding Ic(t), the wall voltage Vw(t) may be expressed as follows.

^VwW - A j^Iwmdt

The voltage Vc(t), measured from the outside, equals the sum of the voltage applied from the outside and the voltage caused by the cumulated charge. Therefore, Vc(t) may be expressed as follows.

Vc(t) = Vs(t) + - L- (iw(t)dt = Vs(t) + Vw(t As explained above, each research institution defines the PDP wall voltage differently. Research institutions still suggest various different methods to define wall voltage and strive to provide values thereof. Consequently, there has yet been no exact definition of wall voltage which is a component controlling the discharge effect in a surface discharge AC PDP and thus there are problems because quantitative experiment values of wall voltage may not be produced.

Disclosure of Invention

The puφose of the present invention is to make it possible to measure exact wall charge and wall voltage by providing a new definition of the PDP wall voltage.

Another pmpose of the present invention is to optimize the control of the PDP discharge.

In order to achieve these puφoses, method for measuring wall charge and wall voltage on the plasma display panel according to the present invention comprises the steps of: making the serial connection of an external capacitor with a certain capacitance to one side of a plasma display panel and applying a power supply voltage to both ends of the entirety of the plasma display panel and the external capacitor; measuring a voltage between both ends of the plasma display panel and a voltage between both ends of the external capacitor resulting from the power supply voltage; and measuring a wall voltage and a wall charge of the plasma display panel using the measured voltage between the plasma display panel's both ends and the measured voltage between the external capacitor's both ends, wherein discharge characteristics are analyzed upon the assumption that the wall voltage is a dependent power source of the power supply voltage. Preferably, the wall voltage is calculated by adding a capacitance voltage of the plasma display panel and a capacitance voltage of the external capacitor.

Furthermore, the wall voltage and the wall charge may be measured in accordance with a waveform applied by the power supply voltage. In the preferred implementation, in the case that there is no discharge in the

.. Cc _{τ r} Cp

J/ = ] ye = - Vs plasma display panel: P CcA-Cp ; CcA-Cp ; and

VpCp = VcCc

Vc Thus, Cp = — -— Cc . Vp

Here, Vs is the power supply voltage. Vp is the voltage between the plasma display panel's both ends. Vc is the voltage between the external capacitor's both ends. Cp is the capacitance value of the entire panel between the two electrodes of the plasma display panel. Cc is the external capacitance value connected serially to the plasma display panel.

In the case that there is discharge in the plasma display panel, the voltage Vpw between the two ends of the plasma display panel applied by wall voltage may

be defined as follows: = _ Vw • Here, the voltage Vcw at the

2 Cc + Cp' two ends of the external capacitor may be defined as follows:

AAA = _ Af_ _Vw

2 Cc + Cp' Here, Vw is the wall voltage. Δ V is the measured voltage. Cc is the value of the external capacitance. Cp' is the capacitance value of the dielectric layer of the plasma display panel.

Brief Description of Drawings

Fig. 1 is the cross-sectional view illustrating the structure of a general plasma display panel.

Fig. 2 is an illustration of a model structured to define the wall voltage of a plasma display panel according to the prior art. Fig. 3 is a diagram of the equivalent circuit of the model of Fig. 2 prior to discharge.

Fig. 4 is a diagram of the equivalent circuit of the model of Fig. 2 after discharge.

Fig. 5 is another illustration of a model structured to define the wall voltage of a plasma display panel according to the prior art.

Fig. 6 is a diagram of the equivalent circuit of the model illustrated in Fig. 5.

Fig. 7 is a diagram of the equivalent circuit of the circuit adopted by the method for measuring wall charge and wall voltage on plasma display panel according to the present invention. Fig. 8 is another diagram of the equivalent circuit of the circuit adopted by the method for measuring wall charge and wall voltage on plasma display panel according to the present invention.

Fig. 9 is a diagram of the voltage waveform in the equivalent circuit of Fig. 8 prior to discharge. Fig. 10 is a diagram of the voltage waveform in the equivalent circuit of Fig. 8 after discharge has commenced.

Fig. 11 is a graphic illustrating the Lissajous diagram in the normal discharge state for the measuring of wall voltage of a plasma display panel according to the present invention.

Fig. 12 is a graphic illustrating the Lissajous diagram in the self-erasing discharge state for the measuring of wall voltage of a plasma display panel according to the present invention.

Fig. 13 is a graphic illustrating the changes in wall voltage caused by voltage applied to the panel according to a preferred implementation of the present invention.

Fig. 14 is a graphic illustrating the changes in the output wall voltage corresponding to the input wall voltage and the voltage applied to the panel according to a preferred implementation of the present invention.

Best Mode for Carrying Out the Invention

Reference will now be made in detail method for measuring wall charge and wall voltage on plasma display panel according to the present invention as illustrated in the accompanying drawings.

Fig. 7 is a diagram of the equivalent circuit of the circuit adopted by the method for measuring wall charge and wall voltage on plasma display panel according to the present invention. Fig. 8 is another diagram of the equivalent circuit of the circuit adopted by the method for measuring wall charge and wall voltage on plasma display panel according to the present invention. Fig. 9 is a diagram of the voltage waveform in the equivalent circuit of Fig. 8 prior to discharge. Fig. 10 is a diagram of the voltage waveform in the equivalent circuit of Fig. 8 after discharge has commenced. For the convenience of explanation, the description of the present invention is made based upon one cell of a plasma display panel. However, it is apparent that a plasma display panel actually contains multiple cells. As illustrated in Fig. 7 and Fig. 8, in order to measure wall voltage of a PDP, an external capacitor with capacitance value of Cc is connected serially to the outside of the PDP which is equivalent to a capacitor with capacitance value of Cp. The waveforms of the voltage Vp between the two ends of the PDP and the voltage Vc between the two ends of the external capacitor induced by the power supply voltage Vs are recorded both prior to and after discharge. Then, the outputs are inteφreted.

Prior to discharge, if the power supply voltage with the voltage value Vs' is supplied in a pulse form as shown in Fig. 9, the voltage Vp at the two ends of the PDP is measured to be a pulse form with the voltage value of Vp'. The voltage Vc at the two ends of the external capacitor is a pulse form with the voltage value of Vc'. Now, it is explained how wall voltage is construed from the voltage waveforms measured prior to discharge. Prior to discharge, there is no change in wall voltage of a PDP. Thus, only the capacitance value of Cp in the PDP needs to be calculated. Here:

^y

V C

Vc Thus, Cp — -r— - Cc Vp

Here, Vs is the power supply voltage. Vp is the voltage between the plasma display panel's both ends. Vc is the voltage between the external capacitor's both ends.

Cp is the capacitance value of the entire panel between the two electrodes of the plasma display panel. Cc is the external capacitance value connected serially to the plasma display panel. Also, after discharge has commenced, if the power supply voltage with the voltage value Vs' is applied in a pulse form as shown in Fig. 10, the voltage Vp at the two ends of the PDP is measured to be a pulse form with the voltage value of Vp'. The voltage Vc at the two ends of the external capacitor is measured to be a pulse form with the voltage value of Vc'. As illustrated above, differently from the state prior to discharge, once discharge commences, the PDP begins to have changes in wall voltage inside of the

PDP.

Thus, the equivalent circuit after the discharge is as illustrated in Fig. 8.

Capacitance on the entire PDP Cp is composed of two capacitances 2Cp' created upon the dielectric layer and the capacitance in the discharge space A. As shown in Fig. 10, the voltage waveforms after the commencement of discharge are similar to those influenced by two different power sources.

Accordingly, in the present invention, the wall voltage Vw is inteφreted as an independent power source because the wall voltage Vw generated by discharge has the effect of applying an independent additional power supply voltage. Therefore, the voltage Vp at the PDP and the voltage Vc at the external capacitor may easily be analyzed based upon the voltage supeφosition principle of the wall voltage Vw and the power supply voltage Vs.

More specifically, the voltage distribution by the wall voltage component may be expressed by the following equations.^* Vw = Vpw' + Vcw;

Cc Cp'

Vpw' - Vw w - Vw

Cc + Cp ' and Vc

Cc + Cp'

Here, Vpw' is the voltage corresponding to the total capacitance Cp' of the

PDP's two capacitances 2Cp'. Vcw is the voltage corresponding to capacitance Cc.

Accordingly, the actual voltage Vpw detected at the two ends of the PDP in Fig. 8 may be calculated by the following equation:

Vpw = -Vw + Vpw ¹ ; and Vpw' = _Cc ^_c , Vw .

Cp' Thus, ^" P ^~ Q_C __j_ Q , This value is the same as

Vpw =

Vcw, the voltage at the capacitance Cc. Also, this value may be expressed to be -Δ V/2 as shown in Fig. 10.

Accordingly, the relationship in the following equation becomes valid.

^{A F} - ^CP'

2 Cc + Cp' v._*

Thus, the voltage Vpw at the two ends of the PDP caused by the wall voltage Vw

becomes: _. = £__ y_w ,and the Vcw at the capacitance Cc

2 Cc + Cp'

caused by the wall voltage Vw is: = ±_ Vw •

2 Cc + Cp' Consequently, the following equations are true:

Cp' LAV Cp' L\ V

Vpw Vw- Vcw = Vw =

Cc+Cp' and Cc + Cp'

With respect to the voltage distribution caused by the power supply voltage Vs, the voltage Vps at the two ends of the PDP caused by the power supply voltage

Vs is *— ^c _j^_s , and the voltage Vcs at the capacitance Cc caused by

Cc -+- CAAjp

^■^ T s AAc -t- Afjy the power supply voltage Vs is

I ". ^{VPS =} Cc + Cp ^VS nd ^Vcs = Cc ÷ Cp ^Vs

The voltage Vp upon the PDP after the discharge is the sum of the voltage upon the PDP caused by the wall voltage Vw and the voltage upon the PDP caused by the power supply voltage Vs. Accordingly, Vp and Vc may be expressed as follows:

Q? _τ Cp' _{τ r} Cp _τr Δ ϊ⁷

Here, it is assumed that wall charge +Qw has been formed inside the PDP in X V Fig. 8. Then, 2 *^{s tne} voltage resulting from wall charge -Qw, the wall charge with the opposing polarity of the wall charge +Qw, induced at one electrode with the capacitance 2Cp' and from wall charge -Qw, the wall charge with the opposing polarity of the wall charge +Qw, induced at one electrode with the capacitance Cc.

Resultantly, the following equation is deduced.

On the other hand, the Lissajous diagram implemented on an oscilloscope through the voltage waveforms of Fig. 10 at the normal discharge state is as illustrated in Fig. 11. The Lissajous diagram at the self-erasing discharge state is as illustrated in Fig. 12.

In Fig. 11, the slope between Point 4 and Point 1 or the slope between Point 3 and Point 2 multiplied by the external capacitance Cc equals the capacitance Cp which is the entire capacitance component of the PDP prior to discharge. In Fig. 12, the slope between Point 1 and Point 4, between Point 2 and Point 3, between Point 8 and Point 5, or between Point 6 and Point 7, multiplied by the external capacitance Cc equals the capacitance Cp which is the entire capacitance component of the PDP prior to discharge. Here, if it is assumed that the discharge path during the discharge is a conductor,

Cp equals Cp'. Accordingly, the value of Cp' may be calculated. In other words, the value is calculated by multiplying the external capacitance Cc to the slope between Point 1 and Point 2 or the slope between Point 3 and Point 4 in Fig. 11, or to the slope between Point 1 and Point 2, between Point 3 and Point 8, between Point 5 and Point 6, or between Point 7 and Point 4 in Fig. 12.

Accordingly, capacitance Cp may be expressed with the following equation:

Cp = _τ , — Cc Vp '+ Δ V

Here, capacitance Cp is the value of the capacitance of the entire panel including the wall charge component both prior to discharge and during the idle period after discharge.

Where the discharge path generated by discharge has the conductivity, capacitance Cp' is the value of the capacitance formed among the space charge on the dielectric layer and X, Y electrodes of the panel caused by the discharge and is measured in Fig. 11 or Fig 12.

As evidenced in the result of the analysis pursuant to the above explanations, Cp, Cp', wall voltage Vw and wall charge Qw generated upon the dielectric layer of a

PDP may all be calculated. In other words, Cp is calculated by the equation, C_O — Vc ' Cc

^ Vp '+ V

Cp' is calculated through the slope of the Lissajous diagram. Also, the wall

L\ V _ Cp' voltage Vw is calculated by the equation, — - — — — -x. -^- Vw

A V Qw Furthermore, the wall charge Qw is calculated by the equation, — - — = — —

2 Cc

On the other hand, as shown in Fig. 13 and Fig. 14, it is possible to set the design standard of the driving waveform by applying wall voltage Vw calculated through the modeling of Fig. 7 and the voltage between the PDP's both ends.

The relationship between the wall voltage Vw component and the wall voltage caused by the external voltage directly applied to the PDP is as shown in Fig. 13. Vwout corresponding to Vwin + Vp is as illustrated in Fig. 14. The wall voltage value changes as shown in Fig. 13 during the rising and falling periods. When the wall voltage finally reaches the value of the voltage Vp between the PDP's both ends, the stable status is maintained.

Accordingly, if the initial wall voltage and the voltage to be applied to the PDP are known, the wall voltage inside the discharge cell may be calculated. Thus, the information concerning discharge may be estimated and the waveform of the applied voltage may be designed therefrom. Consequently, it is made possible to design the PDP's structure and to analyze the characteristic of the gas charged in the discharge space.

Industrial Applicability

As explained above, the present invention provides the method for measuring wall charge and wall voltage which are elements controlling the discharge characteristics in a surface discharge AC type PDP. The present invention provides the standards for the waveform design of the voltage supplied to control discharge in a PDP and for the design of a PDP structure. Consequently, discharge in a PDP may effectively be controlled and furthermore the discharge characteristics of the PDP may be improved.

Claims

What is claimed is:

1. A method for measuring wall charge and wall voltage on plasma display panel comprising the steps of:

Electrically connecting an external capacitor of a certain capacitance serially to one side of the plasma display panel and applying a power supply voltage to two ends of the entirety of a plasma display panel and the external capacitor; measuring a voltage at the two ends of the plasma display panel and a voltage at the two ends of the external capacitor, resulting from the power supply voltage; and measuring a wall voltage and a wall charge of the plasma display panel using the measured voltage at the plasma display panel's ends and at the external capacitor's ends, wherein the wall voltage is deemed to be a dependent power source of the power supply voltage for the puφose of inteφreting discharge characteristics.

2. The method according to claim 1, wherein the wall voltage is calculated to be the sum of a voltage corresponding to a capacitance of the plasma display panel itself and a voltage corresponding to the capacitance of the external capacitor.

3. The method according to claim 1, wherein the wall voltage and the wall charge are measured in accordance with an applied waveform of the power supply voltage which changes as time passes.

4. The method according to claim 1, wherein, in the event that there is no discharge in the panel: V = —^— Vs ; Vc = ^Cp Vs ;

^P Cc+Cp ' Cc+Cp

Vc Vp Cp = VcCc . _{andj thuSj} Cp - — Cc _(γs ._{s the power}

supply voltage; Vp is the voltage at the plasma display panel's two ends; Vc is the voltage at the external capacitor's two ends; Cp is the capacitance of the entire plasma display panel; and Cc is the capacitance of the external capacitor serially connected to the plasma display panel).

5. The method according to claim 1, wherein, in the event that there is discharge in the plasma display panel: a voltage Vpw at the plasma display panel's two ends is defined as

Δ F _ Cp' _τ-

— vw ^• and a voltage Vcw at the external capacitor's

Cc + Cp'

\ V Cp'

Vw two ends caused by the wall voltage is defined as follows : 2 Cc + Cp '

(Vw is the wall voltage; Δ V is the measured voltage; Cc is the external capacitance; and Cp' is the capacitance of the dielectric layer of the plasma display panel).