WO2001091169A1 - Elimination de la diffusion laterale de dopants a partir de regions source/drain de mosfets - Google Patents

Elimination de la diffusion laterale de dopants a partir de regions source/drain de mosfets Download PDF

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Publication number
WO2001091169A1
WO2001091169A1 PCT/US2001/015898 US0115898W WO0191169A1 WO 2001091169 A1 WO2001091169 A1 WO 2001091169A1 US 0115898 W US0115898 W US 0115898W WO 0191169 A1 WO0191169 A1 WO 0191169A1
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Prior art keywords
dopants
substrate
gate stack
nitrogen
recited
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PCT/US2001/015898
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English (en)
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Kil-Ho Lee
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Infineon Technologies North America Corp.
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Publication of WO2001091169A1 publication Critical patent/WO2001091169A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • This disclosure relates to semiconductor fabrication and more particularly, to a method for suppressing dopant diffusion from source/drain regions of a transistor into a channel region of the transistor.
  • MOSFET metal oxide semiconductor field effect transistors
  • a LLD (Lightly-Doped-Drain) drain extension has been inevitably used to simultaneously achieve a shallow enough junction at the channel to minimize the short channel effects and to provide a deep junction in a contact region to minimize extrinsic series resistance.
  • Effective channel length to be as long as possible to minimize the short channel effect, is strongly affected by lateral junction movement.
  • vertical junction depth is as shallow as possible, if we take an empirical thumb rule of 70% lateral junction movement with respect to the junction depth of boron.
  • the formation of ultra-shallow vertical p+ junction is very difficult due to serious boron channeling and fast boron diffusion upon annealing.
  • MOSFET 10 includes an extended source/drain structure 12 and a deep source/drain junction structure 14.
  • MOSFET 10 includes an extended source/drain structure 12 and a deep source/drain junction structure 14.
  • BF 2 ions are usually implanted at energies below 15 keV and a dose below lxlO 15 cm 2 to form a source/drain extension surface 12.
  • spacers 18 BF ions are usually implanted at energies below 30 keV and dose below 5 ⁇ l0 15 cm 2 to make deep junctions 14 for ensuring low metal-to-p+ junction contact resistance, followed by subsequent annealing such as Rapid Thermal Annealing (RTA) or Furnace annealing (FA) .
  • RTA Rapid Thermal Annealing
  • FA Furnace annealing
  • boron diffuses in all directions as indicated by lines 22 to form source drain junctions 24.
  • the diffusion in the vertical direction is due to TED (Transient Enhanced Diffusion) caused by the interstitial supersaturation.
  • Lateral diffusion of boron also occurs, because there are so many interstitials in channel edge regions 20 resulting from lateral straggling of boron.
  • a method for suppressing lateral diffusion in semiconductor fabrication processes includes forming a gate stack on a semiconductor substrate and implanting nitrogen into the substrate at an angle relative to the gate stack such that nitrogen dopants are implanted below the gate stack. Dopants are implanted to form source and drain regions in the substrate adjacent to the gate stack. The dopants extend to a depth at least equal to a depth of the implanted nitrogen in the substrate such that lateral diffusion of the dopants below the gate stack is suppressed.
  • the dopants are preferably provided by employing boron or boron fluoride .
  • the method may include the step of annealing the substrate to drive in the dopants, wherein the dopants extend deeper into the substrate but are suppressed from lateral diffusion by the nitrogen implants.
  • the step of forming dielectric spacers on sides of the gate stack may be included.
  • the step of forming dielectric spacers on sides of the gate stack may occur before the step of implanting nitrogen.
  • the step of forming dielectric spacers on sides of the gate stack may occur after the step of implanting dopants.
  • the angle may be between about 20 degrees and about 45 degrees relative to a surface normal of a major surface of the substrate.
  • a projected range of the nitrogen is preferably approximately equal to a projected range of the dopants .
  • a method for suppressing lateral diffusion in semiconductor fabrication processes includes forming a gate stack on a semiconductor substrate, implanting nitrogen into the substrate at an angle relative to the gate stack such that nitrogen dopants are implanted below the gate stack, and implanting first dopants to form extended source and drain regions in the substrate on opposite sides of the gate stack and adjacent to the gate stack, the first dopants extending to a depth at least equal to a depth of the implanted nitrogen in the substrate such that lateral diffusion of the dopants below the gate stack is suppressed.
  • Dielectric spacers are formed on lateral sides of the gate stack, and deep implantation regions are formed by implanting second dopants into the substrate deeper than the extended source and drain regions.
  • a method for suppressing lateral diffusion in semiconductor fabrication processes includes the steps of forming a gate stack on a semiconductor substrate, implanting nitrogen into the substrate at an angle relative to the gate stack such that nitrogen dopants are implanted below the gate stack, forming dielectric spacers on lateral sides of the gate stack after nitrogen implantation, implanting first dopants to form extended source and drain regions in the substrate on opposite sides of the gate stack and adjacent to the gate stack, the first dopants extending to a depth at least equal to a depth of the implanted nitrogen in the substrate such that lateral diffusion of the dopants below the gate stack is suppressed, patterning a dielectric layer on the substrate having openings formed therethrough for accessing the extended source and drain regions and forming deep implantation regions deeper by implanting second dopants into the substrate deeper than the extended source and drain regions through the openings in the dielectric layer.
  • the dopants are preferably provided by employing boron or boron fluoride.
  • the method may include the step of annealing the substrate to drive in the first and second dopants, wherein the first and second dopants extend deeper into the substrate but are suppressed from lateral diffusion by the nitrogen implants .
  • the step of forming dielectric spacers may occur after the steps of implanting nitrogen and implanting first dopants.
  • the step of forming dielectric spacers may occur before the step of forming deep implantation regions.
  • the angle may be between about 20 degrees and about 45 degrees relative to a surface normal of a major surface of the substrate.
  • a projected range of the nitrogen is preferably approximately equal to a projected range of the first dopants .
  • the method may include the step of patterning a contact dielectric layer on the substrate wherein the step of forming deep implantation regions may include the step of forming the deep implantation regions by implanting the second dopant through openings in the contact dielectric layer.
  • the method may include the step of forming contacts in the openings of the dielectric layer
  • FIG. 1 is a schematic cross-sectional view showing a conventional MOSFET device with lateral diffusion into a channel region
  • FIG. 2 is a cross-sectional view of a gate stack formed on a substrate for implementing the present invention
  • FIG. 3 is a cross-sectional view of a gate stack formed on a substrate with spacers for implementing the present invention
  • FIG. 4 is a cross-sectional view of a partially fabricated transistor device (e.g., MOSFET) showing nitrogen impurities being implanted at an angle in accordance with the present invention
  • FIG. 5 is a cross-sectional view of a -partially fabricated transistor device (e.g., MOSFET) showing nitrogen impurities being implanted at an angle prior to spacer formation in accordance with the present invention
  • FIG. 6 is a cross-sectional view of the transistor device of FIG. 4 showing dopants being implanted in accordance with the present inven ion;
  • FIG. 7 is a cross-sectional view of the transistor device of FIG. 5 showing dopants being implanted in accordance with the present invention
  • FIG. 8 is a cross-sectional view of the transistor device of FIGS. 6 or 7 showing suppression of lateral diffusion of dopants during an anneal process in accordance with the present invention
  • FIG. 9 is a cross-sectional view of the transistor device of FIG. 8 showing a dielectric layer patterned for contacts in accordance with the present invention.
  • FIG. 10 is a cross-sectional view of the transistor device of FIG. 9 showing contacts formed through the ' dielectric layer in accordance with the present invention
  • FIG. 11 is a cross-sectional view of a transistor device showing both extended and deep implantation regions in accordance with the present invention
  • FIG. 12 is a cross-sectional view of a transistor device showing both extended and deep implantation regions wherein the deep implantation regions were implanted through openings in a dielectric layer employed for contacts in accordance with the present invention.
  • FIG. 13 is a cross-sectional view of the transistor device of FIG. 12 showing both extended and deep implantation regions annealed and showing contacts formed in accordance with the present invention.
  • the present invention includes methods for preventing lateral diffusion of dopants in semiconductor devices.
  • the present invention focuses on suppression of lateral boron diffusion by implementing a angle-tilt nitrogen implantation into the channel region.
  • the angle tilt may be in the range of about 20E to about 45E.
  • a gate stack 102 is formed on a substrate 104, e.g., a silicon substrate.
  • gate stack 102 includes a gate oxide 106, a doped polysilicon layer 108 and a metal suicide 110, such as tungsten suicide. Other materials and gate structures may be employed as well.
  • a silicon nitride cap 112 is placed over gate stack 102. Gate stack 102 is then patterned to provide the structure shown in FIG. 2.
  • spacers 109 may be formed on sides of gate stack 102.
  • Spacers 109 preferably include silicon nitride. Spacers 109 may be formed at this time (e.g., before extended diffusion region implantation, before deep diffusion region implantation and/or before nitrogen implantation) or at a later time (e.g., after extended diffusion region implantation, after deep diffusion region implantation or after nitrogen implantation) . If an extended source/drain region implantation is performed, the extended source/drain region implantation and the nitrogen implantation are preferably performed prior to the formation of spacers 109, and the deep implantation is preferably performed after the formation of spacers 109. This is illustratively shown in FIG. 12 below.
  • a angle-tilt-nitrogen implantation is advantageously employed.
  • nitrogen is not a commonly used ion species in Si ultra- large scale integration (ULSI) . It cannot be used as an n- type dopant because of its low solubility in Si.
  • the solid solubility of nitrogen in Si is 5 ⁇ l0 15 cm 3 and its activation ratio is below 1%. Thus, no extra electrical effect by nitrogen implantation is expected.
  • the nitrogen ions act as sites of interstitial traps and strain-induced gettering and therefore suppress dopant diffusion, especially in the case of boron dopants.
  • a cross-sectional view of transistor 100 is shown where angle-tilt nitrogen 130 is implanted into a region 131 below gate stack 102.
  • the nitrogen implantation is performed after gate stack 102 and spacer 109 are formed.
  • nitrogen implantation may be performed before spacer 109 is formed.
  • Nitrogen tilt-angle implantation preferably includes a tilt angle, ⁇ , which may range from about 20E to about 45E.
  • Nitrogen implantation energy is selected to cover the subsequently implanted dopant (e.g., boron) peak regions or slightly below these regions, not tail regions of boron (tail regions are the low concentration regions or "tails" of a concentration distribution curve) . That is, the projected range (Rp) of nitrogen is preferably about the same as that of boron.
  • Nitrogen dose may range from about l ⁇ l0 14 /cm 2 to about 5 ⁇ l0 1 ⁇ /cm 2 .
  • Nitrogen (N + ) energy may range from between about 10 keV to about 50 keV for tilt-angle-nitrogen implantation.
  • nitrogen implantation energy is selected to cover the subsequently formed dopant (e.g., boron) peak region, e.g., a same depth as the dopant implantation, vertical diffusion is permitted (e.g., deeper into the substrate) for the dopants while lateral diffusion is reduced or suppressed. Lateral diffusion length of dopants can be adjusted by tilt angle and nitrogen dose. Thus, effective channel length (L eff ) can be easily adjusted by large-angle-tilt-nitrogen implantation .
  • dopant e.g., boron
  • Source and drain regions 111 and 113 are formed.
  • Source and drain regions 111 and 113 are preferably formed in an ion implantation process.
  • One of the advantages of the present invention includes a one-time dopant (e.g., boron) implantation to make p+ junctions for source and drain regions 111 and 113.
  • Dopants for source and drain regions 111 and 113 may be implanted in a single implantation step. Alternately, both an extended implantation region 150 and a deep implantation region 152 may be employed, as shown in FIG. 11. However, extended junctions, as described above, are no longer needed, but both deep and extended regions may be maintained, if desired.
  • dopants of source and drain regions 111 and 113 are implanted at an energy between about 5 and 50 keV at a dose of between about 5 ⁇ l0 14 /cm 2 and about 5 ⁇ l0 5 /cm 2 .
  • Dopants of source and drain regions 111 and 113 may include boron, arsenic, phosphorous, etc. Boron dopants are preferably implanted although boron containing compounds, such as BF 3 may be employed.
  • boron is employed as a dopant for regions 111 and 113, and is implanted to a depth greater than or equal to the depth the previously implanted nitrogen in regions 131.
  • the deep implantation step may be employed to further improve metal to dopant contact resistance.
  • spacers 109 are formed after the implantation of dopants as shown in FIG. 7.
  • the anneal process may include a rapid thermal anneal (RTA) , a furnace anneal (FA) or other anneal process .
  • RTA rapid thermal anneal
  • FA furnace anneal
  • the temperature of the anneal is sufficient to cause the appropriate amount of diffusion.
  • RTA temperatures in the range of about 850°C and about 1050 °C are employed.
  • RTA times may be between about 5 seconds and about 30 seconds.
  • FA temperatures in the range of between about 750 °C and about 900 °C are employed.
  • FA times may be between about 10 minutes and about 40 minutes.
  • the lateral diffusion is suppressed by the presence of nitrogen.
  • the effective channel length is increased by about 20-30% over prior art devices (See, e.g. , FIG. 1) .
  • a dielectric layer 140 is patterned over substrate 104 to form openings 144 for contacts 142.
  • Dielectric layer 140 preferably includes a silicon oxide.
  • Contacts may include a metal such as, titanium/titanium nitride followed by tungsten, aluminum, or other conductive material .
  • extended source and drain regions 150 and deep implantation regions 152 may both be employed.
  • Spacers 109 are shown and may have been formed after nitrogen implantation and extended source/drain implantation or before nitrogen implantation and extended source/drain implantation.
  • the annealing step is preferably performed after both extended implantation and the deep implantation are performed, but may be performed after the extended implantation but before the deep implantation.
  • Regions 150 may be implanted with dopants having a projected range of less than, equal to, or greater than the projected range of the nitrogen impurities of region 131. In this way, vertical and lateral diffusion may be suppressed (in the case of less than the projected range of the nitrogen impurities of region 131) , or lateral diffusion suppressed (in the case of greater than or equal to the projected range of the nitrogen impurities of region 131) .
  • a deep source drain implant is performed to form regions 152.
  • FIG. 11, shows the case where region 150 is formed with dopants having a projected range of less than the projected range of the nitrogen impurities of region 131. In an alternate embodiment, the deep implant may be performed before spacers 109 are formed.
  • Deep source/drain implantation may be performed through contact openings 144 in a dielectric layer 140.
  • Extended regions 150 are shown to be implanted with dopants having a projected range of greater than the projected range of the nitrogen impurities of region 131, and the dopants of regions 150 have diffused vertically, e.g., deeper into substrate 104, while lateral diffusion below gate stack 102 is suppressed.
  • Deep implantation regions 152 are formed by causing dopants 153 to pass through openings 144 in dielectric layer and in contact mask 146, and be implanted in substrate 104. The structure of FIG.
  • a post-deep- implantation anneal as shown in FIG. 13 may be performed instead of or in addition to a previous anneal.
  • Contacts 142 are formed in openings 144.
  • angle- tilt-nitrogen implantation and source/drain extension implantation may be performed prior to spacer formation, followed by spacer formation and deep source/drain implantation.
  • large-angle-tilt-nitrogen may be performed prior to spacer formation, followed by spacer formation and extended source/drain implantation.
  • deep source/drain implantation may be performed when a metal contact mask is opened.
  • the deep implantations of the present invention may include dopants such as B, As, P etc.

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Abstract

L'invention concerne un procédé permettant de supprimer la diffusion latérale dans des processus de fabrication de semi-conducteurs, consistant à former un empilement de grille (102) sur un substrat semi-conducteur (104) et à incorporer de l'azote (131) dans ledit substrat à un angle par rapport audit empilement de grille, de sorte que des dopants azote sont incorporés en dessous de l'empilement de grille. On incorpore des dopants pour former des régions source/drain (111, 113) dans le substrat adjacent à l'empilement de grille. Ces dopants s'étendent sur une profondeur au moins égale à une profondeur de l'azote incorporé dans le substrat de sorte que la diffusion latérale des dopants en dessous de l'empilement de grille est éliminée.
PCT/US2001/015898 2000-05-24 2001-05-16 Elimination de la diffusion laterale de dopants a partir de regions source/drain de mosfets WO2001091169A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2455054A (en) * 2007-09-27 2009-06-03 Nxp Bv Method of manufacturing a FINFET

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4430366A1 (de) * 1993-09-02 1995-03-09 Mitsubishi Electric Corp Halbleitereinrichtung und Verfahren zum Herstellen derselben
US5516707A (en) * 1995-06-12 1996-05-14 Vlsi Technology, Inc. Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor
EP0789400A2 (fr) * 1996-02-07 1997-08-13 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur et méthode de fabrication
EP0949669A2 (fr) * 1998-04-07 1999-10-13 Seiko Epson Corporation Méthode de fabrication d'un dispositif semiconducteur
EP0999594A1 (fr) * 1998-11-06 2000-05-10 Infineon Technologies AG Circuit intégré comportant des transistors à effet de champ de type MOS comprenant des régions dopées à l'azote et méthode de fabrication correspondante

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4430366A1 (de) * 1993-09-02 1995-03-09 Mitsubishi Electric Corp Halbleitereinrichtung und Verfahren zum Herstellen derselben
US5516707A (en) * 1995-06-12 1996-05-14 Vlsi Technology, Inc. Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor
EP0789400A2 (fr) * 1996-02-07 1997-08-13 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur et méthode de fabrication
EP0949669A2 (fr) * 1998-04-07 1999-10-13 Seiko Epson Corporation Méthode de fabrication d'un dispositif semiconducteur
EP0999594A1 (fr) * 1998-11-06 2000-05-10 Infineon Technologies AG Circuit intégré comportant des transistors à effet de champ de type MOS comprenant des régions dopées à l'azote et méthode de fabrication correspondante

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KUROI T ET AL: "HIGHLY RELIABLE 0.15 MUM MOSFETS WITH SURFACE PROXIMITY GETTERING (SPG) AND NITRIDED OXIDE SPACER USING NITROGEN OXIDE SPACER USING NITROGEN IMPLANTATION", SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS, XX, XX, 1995, pages 19 - 20, XP000770868 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2455054A (en) * 2007-09-27 2009-06-03 Nxp Bv Method of manufacturing a FINFET
GB2455054B (en) * 2007-09-27 2011-12-07 Nxp Bv Method of manufacturing a finfet

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