WO2001086821A2 - Turbocodes ameliores a faible taux d'erreur - Google Patents

Turbocodes ameliores a faible taux d'erreur Download PDF

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Publication number
WO2001086821A2
WO2001086821A2 PCT/US2001/014405 US0114405W WO0186821A2 WO 2001086821 A2 WO2001086821 A2 WO 2001086821A2 US 0114405 W US0114405 W US 0114405W WO 0186821 A2 WO0186821 A2 WO 0186821A2
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Prior art keywords
depth
encoder
information bits
rate
equal
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PCT/US2001/014405
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English (en)
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WO2001086821A3 (fr
Inventor
Paul K. Gray
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Icoding Technology, Inc.
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Priority to AU2001261185A priority Critical patent/AU2001261185A1/en
Publication of WO2001086821A2 publication Critical patent/WO2001086821A2/fr
Publication of WO2001086821A3 publication Critical patent/WO2001086821A3/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2742—Irregular interleaver wherein the permutation pattern is not obtained by a computation rule, e.g. interleaver based on random generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2742—Irregular interleaver wherein the permutation pattern is not obtained by a computation rule, e.g. interleaver based on random generators
    • H03M13/2746—S-random interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2996—Tail biting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2945—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using at least three error correction codes

Definitions

  • the present invention relates to the area of forward error correction. More particularly, the present invention relates to coding and decoding schemes for performing very low error rate data forward error correction.
  • Turbo coding a recently developed forward error correction coding and decoding technique that provides previously unavailable error correction performance.
  • a general description of parallel turbo code can be found in US Patent 5,446,747 entitled “Error-correction Coding Method With at Least Two Systematic Convolution Codings in Parallel, Corresponding Iterative Decoding Method, Decoding Module and Decoder,” filed April 16, 1992 assigned to France Telecom and incorporated herein by reference.
  • turbo codes facilitates the transmission of data over noisy channels, thereby improving the data transmission capability of all sorts of communications systems.
  • This error floor reduces the usefulness of turbo codes in many communications applications that require very low error rates such as cable modems and satellite television broadcast.
  • the present invention is directed to providing very low error rate performance in a turbo code based forward error correction scheme.
  • a turbo code providing very low error rate performance and which can be practically implemented on an integrated circuit is described.
  • a turbo code is comprised of three constituent codes and two interleavers placed in parallel concatenated configuration.
  • the constituent codes are configured with at least one higher rate code and at least one lower rate code.
  • the code is configured with one higher rate code and two lower rate codes.
  • the code is comprised of at least one higher depth constituent code and at least one lower depth constituent code.
  • the code is comprised of at least one higher rate and higher depth constituent code.
  • FIGs. 1A-D are diagrams of convolution encoders of different depth. configured in accordance with one embodiment of the invention.
  • the convolutional encoders are recursive systematic convolutional (RSC) encoders, which are generally the preferred constituent encoder for use in a turbo code, however, other types of convolutional encoders may also be used.
  • RSC systematic convolutional
  • the encoder is comprised of a set of memory elements D and a set of XOR gates labeled +.
  • depth is use to describe the number of memory elements (Labeled D) used for particular code, which is equal to K- 1.
  • the number of state in a code corresponds to 2 ⁇ (K- 1) or 2 ⁇ D.
  • constituent codes may be described in terms of constraint length (K), depth (D) or the number of states interchangeably.
  • Fig. 1C is an exemplary depth 2
  • Fig. 2 is a block diagram of a turbo encoder configured in accordance with one embodiment of the invention.
  • the encoder is comprised of three constituent encoders 200 and two interleavers 202.
  • each constituent encoder is also accompanied by a puncture circuit 204.
  • the outputs of the puncture circuits 204 are applied to multiplexer 206 which outputs the encoded symbols.
  • encoders 200 are rate encoders which are combined with puncture circuits 204 to yield encoders than can be programmed for a wide range of effective rates.
  • the use of alternative base rates (other than rate 1/2) is consistent with use of the invention.
  • the use of codes having a "natural" (unpunctured) rate equal to the rate desired for a particular application is also well known, but typically provides less flexibility than the use of punctured codes.
  • An exemplary rate 2/3 encoding is described.
  • data to be encoded is received by encoder 200(1) and interleavers 202(1) and 202(2).
  • Encoder 200(1) performs rate Vi encoding and the resulting symbols are received by puncture circuit 204(1).
  • Puncture circuit 204(1) removes three of every four parity symbols generated, yielding one parity bit for every four systematic bits transmitted. This yields an effective coding rate with respect to the systematic bits being transmitted of 4/5.
  • Interleaver 200(1) also receives the information bits and shuffles the bits according to a predetermined pattern yielding a first set of interleaved information bits.
  • the predetermined pattern is preferably a pseudo random pattern and one example is described in greater detail below.
  • Encoder 200(2) receives the first interleaved information bits and performs rate A encoding generating a parity bit for every information bit received. As with conventional two code turbo codes, the systematic bits from the second code are not used. Puncture circuit 204(2) removes 7 of every 8 parity bits received yielding an effective coding rate with respect to the systematic bits transmitted of 8/9.
  • interleaver 200(1) also receives the information bits and shuffles the bits according to a second predetermined pattern yielding a second set of interleaved information bits.
  • the predetermined pattern is preferably a pseudo random pattern and is described in greater detail below.
  • Encoder 200(3) receives the second interleaved information bits and performs rate VT. encoding generating a parity bit for every information bit received. As with conventional two code turbo codes the systematic bits from this code are not used as well. Puncture circuit 204(3) removes 7 of every 8 parity bits received yielding an effective coding rate with respect to the systematic bits transmitted of 8/9.
  • the combination of the rate 4/5 constituent code and two rate 8/9 constituent codes yields an overall encoding rate of 2/3. Configuring the overall code to have one higher rate constituent code provides superior error correction over a code comprised of three equal rate constituent codes. In contrast, a rate 2/3 code having three equal rate constituent codes would be comprised of three rate 6/7 constituent codes.
  • Table I illustrates the puncture pattern used in the rate 2/3 exemplary embodiment of the invention.
  • Punctured codes are more flexible because a wide range of rates can be achieved by simply modifying the puncture pattern, causing little modification of the circuitry. Punctured codes are more easily implemented because they allow the same base code (Rate Vz in the example case) to be used for both constituent codes while not requiring the effective rate of the constituent codes to be the same, which facilitates hardware sharing both during encoding and decoding.
  • lower depth constituent codes typically degrade more with heavy puncturing. The amount of degradation experienced, however, is significantly reduced when the effective rate of at least one constituent code is kept high.
  • the described embodiment allows lower depth constituent codes to be used in more highly punctured, higher rate, turbo codes.
  • the class of codes described also provides a lower error floor than the equivalent rate two constituent code based turbo codes or less optimized three constituent code based turbocodes, and therefore significantly increases the usefulness of turbocodes in a wide variety of applications which otherwise receive only minimal benefit from the incorporation of turbocoding technology.
  • Fig. 3 is a block diagram of an encoder configured in accordance with a second embodiment of the invention.
  • the encoder is comprised of three constituent encoders 300 and two interleavers 302. Each constituent encoder is also accompanied by a puncture circuit 304.
  • the outputs of the puncture circuits 304 are applied to multiplexer 306 which outputs the encoded symbols in interlaced fashion.
  • constituent encoders 200 are rate 3 encoders that combine with puncture circuits 204 to yield encoders than can be programmed for a wide range of effective rates. Additionally, there are some differences in the depths of constituent encoders 303.
  • the actual constituent codes selected correspond to the codes of Fig. 1.
  • other constituent codes may also be employed.
  • the effective rate of the three constituent encoders 300 and associated puncture circuits 304 is equal. That is, each puncture circuit 304 punctures at the same rate yielding, three effectively equal rate constituent codes. For the rate 2/3 example, each puncture circuit 304 punctures 5 of every 6 parity bits yielding three constituent codes of effective rate 6/7. Table II illustrates the puncturing performed for three constituent codes of effective rate 6/7.
  • turbo encoder having equal rate constituent codes described above with reference to Fig. 3 shows constituent code 300(1) to have the greatest depth
  • other embodiments of the invention may configure constituent code 300(2) or 300(3) to have the greatest depth.
  • 304 are different for different codes. That is, amount of puncturing performed by one puncture circuit 304 is lower than for at least one other puncture circuit 304.
  • a rate 2/3 code may be formed by a first code of effective rate 4/5 and two codes of effective rate 8/9 as described above with respect to Fig. 2.
  • the higher depth code should correspond to the code of lowest rate (the least punctured code).
  • the constituent code 300(1) should be the highest depth. If two codes have depths equal to the highest value, the higher rate code should be one of those two constituent codes.
  • Fig. 2 and Fig. 3 show separate constituent encoders, interleavers and puncture circuits, alternative embodiments of the invention may use time shared circuits for one or more of these blocks.
  • the exemplary rate 2/3 codes described herein may be combined with a 8PSK modulator configured in the well known Gray constellation.
  • the two systematic bits are transmitted over the two most protected symbols in the symbol word, and the parity bit is transmitted over the third, least protected, symbol in the symbol word.
  • Fig. 4 is a block diagram of a turbo decoder configured in accordance with one embodiment of the invention.
  • Depuncture circuit 402 is coupled to receive sample buffer 400 and log-MAP engine 404.
  • Log-MAP engine 404 is coupled to extrinsic information buffer 406 via interleaver (PI) 410 and deinterleaver (PI -1 ) 412, as well as multiplexers 414 and 416 and adder 418.
  • PI interleaver
  • PI -1 deinterleaver
  • depuncture circuit 402 can be configured by a control system (not shown, but typically a microprocessor controlled by software or a state machine) to depuncture for multiple puncture patterns.
  • Log-MAP engine 404 is preferably implemented as a sliding window MAP decoder to reduce memory requirements.
  • a description of a sliding window MAP decoder can be found in US Patent 5,933,462 incorporated herein by reference, as well as in co-pending US Patent Application serial no. 60/202,344 entitled "METHOD AND APPARATUS FOR IMPROVED PERORMANCE SLIDING WINDOW DECODING" assigned to the assignee of the present invention and incorporated herein by reference.
  • other embodiments of the invention may employ other MAP decoders, MAP decoder architectures, or soft-in-soft-out decoders.
  • receive samples that have been transmitted over the noisy channel are stored within receive sample buffer
  • Receive sample buffer is typically double buffered, whereby one full frame of receive samples are stored for decoding while another frame of receive samples is being received.
  • Each subiteration typically corresponds to one of the constituent codes used to encode the data.
  • Each iteration typically corresponds to the set of constituent codes used to perform encoding.
  • one iteration is typically comprised of a set of subiterations.
  • samples are retrieved from receive sample buffer 400 and depunctured by depuncture circuit 402.
  • the depuncturing is performed according to the puncture pattern of the particular constituent code for which decoding is being performed.
  • the parity bits from the other codes are skipped, and neutral values are inserted for the punctured bits.
  • extrinsic information from extrinsic buffers 406(1) and 406(3) would be passed to sum circuit 418 via multiplexers 416.
  • the summed extrinsic information is interleaved by intererleaver 410, which for this subiteration corresponds to the unity interleaver.
  • the resulting depunctured data stream (and extrinsic data for subsequent first subiterations) is fed to the log-MAP engine which performs rate 1/2 log-MAP decoding using a polynomial and depth of the corresponding constituent encoder.
  • this typically corresponds to constituent encoder 200(1) or 300(1). That is, the first decoding is typically performed for the constituent code that received the information bits in the same order as the transmitted bits, which typically corresponds to the constituent code that received non-interleaved information bits.
  • log-MAP decoder During the first decoding, log-MAP decoder generates extrinsic data that is passed through deinterleaver 412 to extrinsic information buffer 406(1).
  • the interleaver is the typically the identity interleaver, which results in no effective reordering of the extrinsic information from log- MAP decoder 404.
  • depuncture circuit 402 retrieves the receive samples from sample buffer 400 and performs puncturing according to the puncture pattern for the second constituent code.
  • the resulting depunctured information is fed to log-MAP decoder 406.
  • Log-MAP decoder 406 also receives extrinsic information from extrinsic information buffers 406(1) and 406(3) after being summed by sum circuit 418 and interleaved by interleaver 410. For the first iteration, the extrinsic information in extrinsic information buffer 406(3) will be zero, as the third subiteration has not been performed.
  • interleaver 410 performs interleaving on the extrinsic information according to the interleaver that feeds the constituent code corresponding to the second subiteration. In an exemplary decoding of the codes of Figs. 2 and 3 this would correspond to interleavers 200(1) or 300(1).
  • Log-MAP decoder 406 receives the receive samples and the interleaved extrinsic information and performs decoding according to the constituent code 202(2) or 302(2).
  • the new extrinsic information is deinterleaved by deinterleaver 412 according to the interleaving done by interleaver 410 during this subiteration and stored via multiplexer 414 into extrinsic information buffer 406(2).
  • depuncture circuit 402 retrieves receive samples from receive sample buffer 400 and performs depuncturing according to the puncture pattern use for the corresponding constituent code. For the exemplary codes this corresponds to puncturing performed by puncture circuit 204(2) and 304(3).
  • extrinsic information from extrinsic buffers 406(1) and 406(2) are then passed via mutiplexers 416 to sum circuit 418.
  • the resulting summed extrinsic information is then interleaved to match the order of the depunctured receive samples from depuncture circuit 402. In accordance with the exemplary codes this corresponds to interleavers 202(2) and 302(2).
  • Log-MAP decoder receives the interleaved extrinsic information and depunctured receive samples and is configured to perform decoding according to the third constituent encoder.
  • the resulting extrinsic information is deinterleaved by deinterleaver 412 according to the interleaver used for this subiteration and stored in extrinsic information buffer 406.
  • a single MAP decoder that can be configured to process different depth codes is used.
  • multiple log-MAP decoders each configured specifically for a particular constituent code may be employed. While this may increase the speed of each individual map decoder, greater circuit area will be required in order to implement the plurality of log-MAP decoders.
  • Vz log-MAP decoder in combination with a depuncture circuit to achieve different coding rates, multiple map decoders each with unique natural rate may be used in alternative embodiments of the invention.
  • an alternative embodiment of the invention may use multiple puncture circuits each configured for a particular puncture pattern.
  • SISO decoder While a log-MAP decoder is preferred due to the higher processing speed and excellent decoding performance, other SISO decoders may be employed such as a multiplicative MAP decoder or SISO trellis decoder.
  • both interleavers are s- type (spread) psuedo random interleavers.
  • the s-type interleaver is based on the random generation of N integers from 0 to N-1 constrained to spread out the addresses. In particular, each randomly selected integer is compared to the S most recently selected integers. If the current selection is within S of at least one of the previous S integers, then it is rejected and a new integer is selected until the previous condition is satisfied. While the use of s-type interleavers provides excellent performance, this types of interleaver requires the use of look-up tables operations to generate.
  • a set of highly spread highly randomized generatable interleavers are used.
  • Various method for generating such interleavers are described in co-pending US patent application serial no entitled "High Spread Highly Randomized
  • At least one of the interleavers used in the code is a highly randomized generatable interleaver configured in accordance with the interleaver generation principals set forth in the high spread patent.
  • both interleavers are highly randomized generatable interleavers configured in accordance with the interleaver generation principals set forth in the high spread patent. In this embodiment of the invention, some particularly good combinations exist.
  • one interleaver is defined by a set of n seed values to which a value is repeatedly addeded to generate the remaining addresses and the interleaver is defined by a set of n seed values to which a value is repeatedly subtracted to generate the remaining addresses.
  • each interleaver is also dithered as described in the high spread patent. Simulation has shown that this interleaver combination works well with a turbo code comprised of two 8 state codes and one 4 state code, although performance with many other codes is also very good.
  • one interleaver is comprised of an interleaver of size n*m where m is at least larger than m and preferably 2m.
  • the interleaver is then constructed by adding (or subtracting ) n to the set of seed values.
  • the second interleaver is size n*m, where m is less than m, however.
  • the second interleaver will have a smaller spread and increased randomness with respect to the first interleaver.
  • this interleaver combination when combined with a very simple code comprised of all four state constituent codes, this interleaver combination can achieve bit error rates as low as 10e-10 for a rate 2/3 8psk code for frame size of > 10,000 bits. Achiving error rates this low using very simple constituent codes and generated interleavers provides a highly efficient and economical coding scheme that will allow the benefits of turbo coding to be incorporated into many applications.
  • tail bit one or more of the constituent codes.
  • the use of tail biting is also described in the high spread interleaver patent. A description of tail biting can be found in the paper Wei ⁇ , Ch.; Bettstetter, Ch.; Riedel, S.: Turbo Decoding with Tail- Biting Trellises. In: Proc. 1998 URSI International Symposium on Signals, Systems, and Electronics, 29. Sept.-2. Oct. 1998, Pisa, juice, pp. 343-348.
  • the ending state XN depends on the entire information vector u encoded.
  • the initial state xo must be calculated, where x 0 will lead to the same state after N cycles.
  • the first step is to determine the zero-state response X[ ZS ],N for a given information vector u.
  • the second state is the actual encoding.
  • the encoder starts in the correct initial state xo; the information vector u is input and a valid codeword v results.
  • the precomputed solutions to (4) for the desired frame size N can be stored in a look-up table.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)

Abstract

Cette invention concerne un turbocode garantissant un très faible taux d'erreur, qui peut être pratiquement mis en oeuvre sur un circuit intégré. Selon un mode de réalisation, le trubocode se compose de trois codes constitutifs et de deux intercalaires en configuration concaténée parallèle. Selon un premier mode de réalisation, les codes constitutifs sont configurés avec au moins un code à taux supérieur et au moins un code à taux inférieur. Selon un deuxième mode de réalisation, le code est configuré avec un code à taux supérieur et deux codes à taux inférieur. Selon un troisième mode de réalisation, le code est composé d'au moins un code constitutif de profondeur plus importante et d'au moins un code constitutif de profondeur moins importante. Selon un quatrième mode de réaIisation, le code comprend au moins un code constitutif à taux supérieur et au moins un code constitutif de profondeur plus importante.
PCT/US2001/014405 2000-05-05 2001-05-04 Turbocodes ameliores a faible taux d'erreur WO2001086821A2 (fr)

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AU2001261185A AU2001261185A1 (en) 2000-05-05 2001-05-04 Improved error floor turbo codes

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60110083T2 (de) * 2001-10-10 2005-09-08 Matsushita Electric Industrial Co., Ltd., Kadoma Dekorrelation von interferenzen von mehreren verschachtelten Datenströmen
JP5622404B2 (ja) * 2010-02-22 2014-11-12 シャープ株式会社 無線通信システム、および通信装置
US9179362B2 (en) 2011-08-25 2015-11-03 Texas Instruments Incorporated Systems and methods for networking coding using Reed-Solomon codes
US8924831B2 (en) * 2011-08-26 2014-12-30 Texas Instruments Incorporated Systems and methods for network coding using convolutional codes
US9113470B2 (en) 2011-08-26 2015-08-18 Texas Instruments Incorporated Systems and methods for network coding using maximum distance separable (MDS) linear network codes
US9112916B2 (en) 2011-08-26 2015-08-18 Texas Instruments Incorporated Systems and methods for construction of and network coding using near-maximum distance separable (MDS) linear network codes
US9698935B2 (en) 2011-09-01 2017-07-04 Rambus Inc. Variable code rate transmission
EP4203402A4 (fr) * 2020-10-21 2023-11-08 Mitsubishi Electric Corporation Dispositif et procédé de traitement de code de transmission et transmetteur optique

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761248A (en) * 1995-07-19 1998-06-02 Siemens Aktiengesellschaft Method and arrangement for determining an adaptive abort criterion in iterative decoding of multi-dimensionally coded information
US6023783A (en) * 1996-05-15 2000-02-08 California Institute Of Technology Hybrid concatenated codes and iterative decoding
EP1024601A1 (fr) * 1999-01-26 2000-08-02 TRW Inc. Architecture pipeline pour le décodage de codes à concaténation parallèle ou série (turbo codes)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2639781B1 (fr) * 1988-11-25 1991-01-04 Alcatel Thomson Faisceaux Procede d'entrelacement pour dispositif de transmission numerique
FR2675971B1 (fr) * 1991-04-23 1993-08-06 France Telecom Procede de codage correcteur d'erreurs a au moins deux codages convolutifs systematiques en parallele, procede de decodage iteratif, module de decodage et decodeur correspondants.
US5721745A (en) * 1996-04-19 1998-02-24 General Electric Company Parallel concatenated tail-biting convolutional code and decoder therefor
US5907582A (en) * 1997-08-11 1999-05-25 Orbital Sciences Corporation System for turbo-coded satellite digital audio broadcasting
FI104133B (fi) * 1997-11-28 1999-11-15 Nokia Mobile Phones Ltd Koodaus- ja modulointimenetelmä ja laite sen soveltamiseksi
AU735889B2 (en) * 1998-04-18 2001-07-19 Samsung Electronics Co., Ltd. Channel encoding device and method for communication system
JP3415120B2 (ja) * 1998-06-05 2003-06-09 サムスン エレクトロニクス カンパニー リミテッド レートマッチングのためのチャネル符号化装置及びその方法
KR100280863B1 (ko) * 1998-09-25 2001-02-01 윤덕용 터보코드의 가중치를 준 병렬형 복호화 방법및 그 장치
US6202189B1 (en) * 1998-12-17 2001-03-13 Teledesic Llc Punctured serial concatenated convolutional coding system and method for low-earth-orbit satellite data communication
US6594318B1 (en) * 1999-12-02 2003-07-15 Qualcomm Incorporated Method and apparatus for computing soft decision input metrics to a turbo decoder
US6775800B2 (en) * 2000-01-03 2004-08-10 Icoding Technology, Inc. System and method for high speed processing of turbo codes

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761248A (en) * 1995-07-19 1998-06-02 Siemens Aktiengesellschaft Method and arrangement for determining an adaptive abort criterion in iterative decoding of multi-dimensionally coded information
US6023783A (en) * 1996-05-15 2000-02-08 California Institute Of Technology Hybrid concatenated codes and iterative decoding
EP1024601A1 (fr) * 1999-01-26 2000-08-02 TRW Inc. Architecture pipeline pour le décodage de codes à concaténation parallèle ou série (turbo codes)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HSU J-M ET AL: "A parallel decoding scheme for turbo codes" ISCAS '98. PROCEEDINGS OF THE 1998 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. MONTEREY, CA, MAY 31 - JUNE 3, 1998, IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, NEW YORK, NY: IEEE, US, vol. 1, 31 May 1998 (1998-05-31), pages 445-448, XP002124484 ISBN: 0-7803-4456-1 *

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