WO2001082227A1 - Pixel calculating device - Google Patents
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- WO2001082227A1 WO2001082227A1 PCT/IB2001/000665 IB0100665W WO0182227A1 WO 2001082227 A1 WO2001082227 A1 WO 2001082227A1 IB 0100665 W IB0100665 W IB 0100665W WO 0182227 A1 WO0182227 A1 WO 0182227A1
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- 238000004364 calculation method Methods 0.000 claims abstract description 20
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/80—Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T5/00—Image enhancement or restoration
- G06T5/20—Image enhancement or restoration using local operators
Definitions
- the present invention relates to a pixel operation device including a filtering circuit for resizing an image.
- the FIR finite e i m p u l s e r e s p s n s e
- FIG. 1 is a block diagram showing an example of a circuit for performing FIR filter processing according to the related art. The figure shows an FIR filter with seven taps and symmetric coefficients.
- data input in time series from a data input terminal 1001 is a delay unit 1002, 1003, 1004, 1005, 1100. 6, 1 0 7 are sequentially transferred in this order.
- the filter coefficients are symmetric, that is, the coefficient corresponding to the input of the data input terminal and the output of each delay device (called a tap) is the center tap (delay device 1004). Output), the data of each tap is added to the data of the same coefficient instead of multiplying the data of each evening by the filter coefficient. Multiplied by a coefficient.
- the input data of the data input unit 1001 and the output data of the delay unit 107 are added by the adder 1008, and the addition result is further added by the multiplier 1008.
- the coefficients hO and are multiplied are multiplied.
- the output of the delay unit 1002 and the output of the delay unit 1106 are added by the adder 1109, and the result of addition is multiplied by the coefficient hi in the multiplier 1109. Sa It is.
- Each output data of the multipliers 101 1 to 110 4 is added by the adder 101.
- the output data of the adder 101 is time-sequentially output from the data output terminal 116 as a filter processing result.
- the coefficients h0 to h3 are determined according to the image reduction ratio. For example, if the reduction ratio is 1/2, a reduced image can be obtained by inserting the time-series output data into the space 1Z2.
- the reason why the filter coefficient is selected symmetrically is that the linear phase (the phase characteristic becomes linear with respect to the frequency) is obtained, so that it is visually preferable to the image. is there.
- the circuit is different for each number of taps, so there is no freedom. If a circuit is provided for each number of taps, an enormous cost is required.
- a first object of the present invention is to provide a pixel operation device capable of changing the number of taps and performing a filtering process for increasing the processing speed without increasing the frequency. It is in.
- a second object of the present invention is to provide a pixel operation device which can be used not only for filtering processing but also for MC (motion compensation) processing, and has a reduced circuit scale. It is here.
- the third purpose is that it can be used not only for filtering processing but also for ME (motion prediction) processing, thus reducing the circuit size.
- ME motion prediction
- the fourth purpose is to use not only filtering processing but also OSD (OnScreenDisplay) processing in digital video equipment.
- Another object of the present invention is to provide a pixel operation device with a reduced circuit size. Disclosure of the invention
- the pixel operation device that achieves the first purpose is a pixel operation device that performs filter processing, and includes N pixel processing means, N pixel data, and filter coefficients. And a control means for operating the N pixel processing means in parallel.
- Each pixel processing means performs an operation using the pixel data supplied to the supply means and the filter coefficient, and then obtains pixel data from the pixel processing means adjacent to each pixel processing means, Calculation is performed using the acquired pixel data and the calculation results are accumulated.
- the control means repeats the acquisition of the pixel data from the adjacent pixel processing means, and the calculation and accumulation using the acquired pixel data a number of times corresponding to the number of taps. Is controlled.
- the N pixel processing means includes a first shifter that shifts the N pixel data to the right and a second shifter that shifts the N pixel data to the left.
- Each pixel processing means performs an operation using two pixel data shifted from two adjacent pixel processing means.
- the number of taps can be made variable, and filtering can be performed to increase the processing speed without increasing the frequency. You.
- the pixel operation device that achieves the second purpose supplies the pixel data of the difference image and the pixel data of the reference frame as the pixel data. Supplied by means.
- FIG. 1 is a block diagram showing an example of a circuit for performing FIR filter processing in the prior art.
- FIG. 2 is a block diagram showing a configuration of a media processor including a pixel operation unit.
- FIG. 3 is a block diagram showing the configuration of the pixel operation units (POU A, POU B).
- FIG. 4 is a block diagram showing the configuration of the left half of the pixel parallel processing unit.
- FIG. 5 is a block diagram showing the configuration of the right half of the pixel parallel processing unit.
- FIG. 6A is a block diagram showing a detailed configuration of the input buffer group 22.
- FIG. 6B is a block diagram showing a detailed configuration of the selection unit in the input buffer group 22. As shown in FIG.
- FIG. 7 is a block diagram showing the configuration of the output buffer group 23.
- FIG. 8 is a diagram illustrating initial input values of pixel data when performing a filter process in the pixel operation unit.
- FIG. 9 is an explanatory diagram showing an initial input value of pixel data to the pixel processing unit 1.
- FIG. 10 is a diagram showing a calculation process in the filter processing in the pixel processing unit 1.
- FIG. 11 is an explanatory diagram showing the computation contents of the filter processing in the pixel processing unit 1.
- FIG. 12 is a diagram showing input / output pixel data when an MC (motion compensation) process (P-picture) is performed in the pixel operation unit.
- MC motion compensation
- FIG. 13 is an explanatory diagram showing a decoding target frame and a reference frame in the MC processing.
- FIG. 14 is a diagram showing input / output pixel data when the MC processing (B-picture) is performed by the pixel operation unit.
- FIG. 15 is a diagram showing input / output pixel data when OSD (on-screen display) processing is performed by the pixel operation unit.
- FIG. 16 is an explanatory diagram of the OSD (On Screen Display) processing in the pixel operation unit.
- FIG. 17 is a diagram showing input / output pixel data when ME (motion prediction) processing is performed by the pixel operation unit.
- FIG. 18 is an explanatory diagram of ME (motion estimation) in the pixel operation unit.
- FIG. 19 is a schematic block diagram showing a data flow when performing vertical filtering in a media processor.
- FIG. 20 is an explanatory diagram in the case of performing vertical 12 reduction.
- Fig. 21 is an explanatory diagram of the case where vertical 1/2 reduction is performed in the conventional technology.
- FIG. 22 is an explanatory diagram in the case of performing vertical one-to-four reduction.
- Fig. 23 is an explanatory diagram of the case of performing vertical 1/4 reduction in the conventional technology.
- FIG. 24 is another schematic block diagram showing the flow of data when performing vertical filtering in a media processor.
- FIG. 25 is an explanatory diagram showing the timing of the decoding process and the vertical filtering process.
- FIG. 26 is an explanatory diagram in the case of performing the vertical 1-2 reduction.
- FIG. 27 is an explanatory diagram in the case of performing vertical 1/4 reduction.
- FIG. 28 is a diagram illustrating a first modification of the left half of the pixel parallel processing unit.
- FIG. 29 is a diagram illustrating a first modification of the right half of the pixel parallel processing unit.
- FIG. 30 is a diagram illustrating a second modification of the left half of the pixel parallel processing unit.
- FIG. 31 is a diagram illustrating a second modification of the right half of the pixel parallel processing unit.
- FIG. 32 is a diagram illustrating a third modification of the left half of the pixel parallel processing unit.
- FIG. 33 is a diagram illustrating a third modification of the right half of the pixel parallel processing unit.
- FIG. 34 is a diagram illustrating a modified example of the pixel processing unit. BEST MODE FOR CARRYING OUT THE INVENTION
- the pixel operation unit of the present invention mainly includes (a) a filter processing used for enlarging and reducing an image, (b) a moving compensation (hereinafter referred to as ME) processing, c) 0 SD (On Screen Display) processing, (d) Motion Estimation (hereinafter referred to as ME) processing, etc. are selectively executed.
- the filter processing the pixel operation unit is designed to be able to change the number of taps without fixing the number of taps, and to use a plurality of pixels continuous in the horizontal or vertical direction (for example, 6 pixels) are processed in parallel. Further, the vertical filter processing is performed in synchronization with the decompression processing of the compressed moving image data.
- the pixel calculation unit in the present embodiment is built in a media processor that performs media processing (decompression processing of compressed audio / video data, compression processing of audio / video data, etc.). This is explained below.
- the media processor is mounted on, for example, a set-top box for receiving digital TV broadcasts, a television receiver, a DVD recording / playback device, and the like.
- FIG. 2 is a block diagram showing a configuration of a media processor having a pixel operation unit.
- the media processor 200 is a dual port memory 100, a stream unit 201, an input / output buffer (hereinafter referred to as I, z ⁇ abbreviated as “knob”) 202, setup processor 203, bitstream FIF 204, variable-length code decoder (VLD) 20 5, variable-length code decoder 205, transfer engine (TE) 206, Pixel operation unit A (hereinafter P ⁇ UA) 207, Pixel operation unit B (hereinafter P ⁇ UB) 208, POUC209, Audio unit 210, I ⁇ P 211, I / O processor (hereinafter referred to as IOP) 211, Video knob memory 211, Video unit: 212, Host unit 214 , RE 215 and a filter section 216.
- I input / output buffer
- VLD variable-length code decoder
- TE transfer engine
- P ⁇ UA Pixel operation unit A
- Dual port memory 100 is an input / output port for external memory 220 (hereinafter referred to as an external port) and an input / output port for media ⁇ processor 200. (Hereinafter referred to as an internal port) and a cache memory, and the data is stored in an external memory 220 out of the components in the media processor 200.
- An access request from a component that reads and writes data (hereinafter referred to as a master device) is received from an internal port, and an external memory 220 is received in accordance with the received access request. Access the At that time, the dual port memory 100 caches a part of the data of the external memory 220 to the internal cache memory.
- the external memory 220 is a memory such as an SDRAM or a DRAM, and includes compressed video data, compressed audio data, decoded audio data, decoded video data, and the like. Is temporarily stored.
- the stream unit 201 inputs stream data (so-called MPEG stream) from outside, and inputs the input stream data. Is divided into a video elementary stream and an audio elementary stream, and each is written to the IO buffer 202.
- stream data so-called MPEG stream
- I / 0 Notifier 202 is for video elementary stream, audio elementary stream, audio data This is a buffer memory that temporarily stores data (extended audio data). Video elementary streams, audio elements The main stream is stored in the stream unit 201 to the I.Z0 notifier 202, and the control of the I0P211 is performed. Thus, the data is stored in the external memory 220 via the dual port memory 100. The audio data is stored in the I / O buffer 202 from the external memory 220 via the dual port memory 100 under the control of the IOP 211. Is done.
- the setup processor 203 is used to decode (decompress) the audio elementary stream and to decode the video elementary stream. Performs macroblock header analysis.
- the audio elementary stream and the video elementary stream are controlled by the IOP 211 to control the external memory 220 or the external memory. Are transferred to the bitstream FIF024 through the dual port memory 100.
- the setup processor 203 reads the audio elementary stream from the bitstream FIFO 204 and decodes it. Then, the audio data after decoding is stored in the setup memory 217.
- the audio data in the setup memory 211 is transferred to the external memory 220 via the dual port memory 100 by the IOP 211. You.
- the setup processor 203 also reads the video elementary stream from the bitstream FIFO 204, and Analyzes the block header and notifies VLD 205 of the analysis result.
- the bit stream FIFO 204 transfers the video elementary stream to the variable-length code decoding unit 205, and outputs the audio elementary stream. Is the FIFO memory for supplying the data to the setup processor 203.
- the video elementary stream and the audio elementary stream are dual-ported from the external memory 220 under the control of the IOP 211. One memory 1 It is transferred to the bitstream FIFO 204 via 00.
- VLD 205 decodes a variable length code included in the video elementary stream supplied from the bit stream FIF O 204.
- the result of this decoding is a group of DCT coefficients in macroblock units.
- the TE 206 performs IQ (inverse quantization) processing and IDCT (inverse DCT) processing in macroblock units on the decoding result of VLD 205.
- the result of these processes is a macro block.
- One macro block is composed of four luminance blocks (Y1 to Y4) and two chrominance blocks (Cb, Cr).
- One block is 8 x 8 pixels.
- the TE 206 stores the decrypted result in the external memory 220 via the dual port memory 100.
- the POU 207 selectively performs mainly (a) filter processing, (b) MC processing, (c) OSD processing, and (d) motion estimation (Moving Estimation) processing.
- the POUA 207 filters 16 pixel data included in the video data (frame data) stored in the external memory 220 in parallel. Filter and expand or contract by thinning out or interpolating the 16 pixels after filtering. The data after the contracted word is stored in the external memory 220 via the dual port memory 100 under the control of the POU 209. '
- the POUA 207 obtains the IQ and IDCT processing results (P and B pictures) stored in the external memory 220 by the TE 206. That is, the pixel data in the reference frame is added in parallel with the pixel data in the reference frame. You. 16 sets of difference values and pixel data are based on the motion vector detected by the macroblock header analysis in the setup processor 203. Is input to POUA207 by POUC209.
- the POUA 207 inputs an OSD image (still image) stored in the external memory 220 or the like via the dual port memory 100, and Overwrites the display frame data in memory 220.
- the OSD image refers to a menu image displayed according to a user's remote control operation, a time display, a channel number display, and the like.
- the ME processing of (d) is to search a macroblock to be coded in uncompressed frame data for a highly correlated rectangular area in the reference frame, and perform coding. This is the process of finding the motion vector pointing to the rectangular area with the highest correlation from the macroblock to be converted.
- the POU 207 calculates 16 differences between the pixel of the macro block to be encoded and the pixel of the rectangular area in the search area in parallel.
- the POU 208 has the same configuration as the POU 207, and dynamically shares the processes (a) to (d).
- the POU 209 controls the supply of the pixel data group to the POU 207 and the POU 209, and the transfer of the processing result to the external memory 220.
- the audio unit 210 outputs the audio data stored in the I / O buffer 202.
- the IOP 211 controls data input / output (data transfer) in the media processor 200.
- data transfer There are the following types of data transfer.
- the audio data stored in the external memory device 2 is transferred to the I / O buffer 202 via the dual port memory 100. It is.
- the video unit 211 reads out a few lines of pixel data from the video data (image frame) of the external memory 220 and outputs the video data to the video unit.
- a storage device such as a television receiver, is connected to an external memory, which stores the image data in two or three lines into a video signal. Output to ⁇
- the host unit (HOST) 214 receives an instruction from an external host microcomputer, and responds to the instruction to execute MPEG decoding, MPEG encoding, and OSD processing. Controls the start and end of reduction and enlargement processing.
- the rendering engine (RE) 215 is a master device that performs rendering processing in computer graphics. Data input / output is performed when the dedicated LSI 218 is connected externally.
- the filter 216 performs still image data scaling processing. Data input / output is performed when the dedicated LSI218 is connected externally.
- the media processor has been described mainly focusing on the case where stream data is input from the stream unit 201 and decoded (decompressed), but it is not compressed.
- the flow is reversed.
- POU A207 or POU2208 performs ME processing
- TE 206 performs DCT processing and Q (quantization) processing. 5 performs variable length coding.
- FIG. 3 is a block diagram showing the configuration of the pixel operation unit. Since POU 207 and POU 208 have the same configuration, POU 207 will be described here.
- POUUA207 is composed of a pixel parallel processing unit 21 and an input buffer group 22.
- An output buffer group 23, an instruction memory 24, an instruction decoder 25, an instruction circuit 26, and a DDA circuit 27 are provided.
- the pixel parallel processing unit 21 includes a pixel transfer unit 17, 16 pixel processing units 1 to 16, and a pixel transfer unit 18, and is input from an input buffer group 22.
- the above-described (a) filter processing, (b) MC processing, (c) OSD processing, and (d) ME) processing are performed on a plurality of pixels, and output to the output buffer group 23.
- Each of the processes (a) to (d) is completed by repeating a macroblock unit, that is, 16 pixels, 16 times (16 lines).
- the activation of each process is controlled by POU 209.
- the pixel transfer unit 17 holds a plurality of left (or upper) pixels (eight pixels in this case) in addition to the 16 pixels in the filter processing, and the right pixel for each clock. shift.
- the pixel transfer unit 18 holds a plurality of right (or lower) pixels (eight pixels in this case) in addition to the 16 pixels in the filter processing, and performs a left shift for each clock. Out.
- the input buffer group 22 holds a plurality of pixels to be processed transferred from the dual port memory 100 under the control of the POUC 209, and furthermore, In the filter processing, filter coefficients are also retained.
- the output buffer group 23 arbitrarily changes the arrangement of the processing results (the processing results of 16 corresponding to 16 pixels) by the pixel parallel processing unit 21. Temporarily. In the filter processing, pixels are thinned out (at the time of reduction) or interpolated (at the time of enlargement) by changing and maintaining the arrangement of pixels.
- the instruction memory 24 includes a microprogram for filter processing (filter P), a microprogram for MC processing (MCP;), and a ⁇ program for SD processing. It stores the micro program (OSD ⁇ P :) and the micro program (MEP) for ME processing.
- the instruction memory 24 includes a microprogram for format conversion of a macroblock and a microcontroller for converting a numerical representation of a pixel.
- the format of the macro block is “4: 2: 0”, “4: 2: 2”, or “4: 4: 4” as defined in the MPEG standard.
- In the numerical representation of a pixel when the value of the pixel is represented as 0 to 255 (typical MPEG data, etc.), it is represented as 1128 to 127 (DV camera, etc.).
- the instruction decoder 25 sequentially reads out and decodes the microcode in the microprogram from the instruction memory 24, and decodes the code according to the decoding result. Control each part in 7.
- the instruction circuit 26 receives, from the POUC 209, an instruction (such as a start address) indicating which of the microphone ⁇ programs of the instruction memory 24 should be started, and issues the designated micro macro. Start the program.
- an instruction such as a start address
- the DDA circuit 27 includes a group of input buffers in the filter processing.
- Figs. 4 and 5 are block diagrams showing the detailed configuration of the left half and the right half of the pixel parallel processing unit.
- the pixel transfer section 17 has eight input ports A 17 0 1 to H1708, 8 delayers A1701 to 1 to hold pixel data and delay by one clock time to HI709, pixel data of input port and left delay 7 selection sections A1 171 to G1 723 to select one of the output signals from the input buffer, 8 delays of 8 pixels input in parallel from the input buffer group 22 It functions as a right shifter that shifts the pixels held by the eight delay units to the right in clock synchronization.
- the pixel transfer unit 18 is different from the pixel transfer unit 17 in that the shift direction is on the left, and the other configuration is the same, so that the description is omitted.
- the pixel processing unit 2 Since the sixteen pixel processing units 1 to 16 in FIGS. 4 and 5 have the same configuration, the pixel processing unit 2 will be described as a representative.
- Pixel processing unit 2 has input ports A201 to C203, selectors A204, B205, delay units A206 to D209, adder A It consists of 120, a multiplier A211, an adder B212, and an output port D213.
- the selection unit A204 selects one of the pixel data input from the input port A201 and the pixel data output from the pixel transfer unit 17 on the left.
- the selection unit A 204 and the delay unit A 206 also have a function of shifting the pixel data input from the pixel processing unit 3 on the right to the pixel processing unit 1 on the left.
- the selection unit B205 is one of the pixel data input from the input port B202 and the pixel data output from the external memory 220 adjacent to the right. Select .
- the selection unit B205 and the delay unit B207 shift the pixel data input from the pixel processing unit 1 on the left to the pixel processing unit 3 on the right. Also performs the function of
- the delay unit A206 and the delay unit B207 hold the pixel data selected in the selection unit A204 and the selection unit B205, respectively.
- Delay device B207 holds the pixel data from input port C203
- the adder A120 adds the pixel data output from the delay unit A206 and the delay unit B207.
- Multiplier A 211 multiplies the addition result of adder A 120 by the pixel data from delay unit C 208. This multiplier A211 is used for the multiplication of the pixel data and the filter coefficient in the filter processing.
- the adder B 221 adds the multiplication result of the multiplier A 211 to the data of the delay unit D 209.
- the delay unit D109 accumulates the addition result of the adder B221.
- the pixel processing unit 2 performs the above-described (a) filter processing, (b) MC processing, (c) OSD processing, and (d) ME processing by selectively operating these components. Execute. The operation of selectively combining these components is performed by the microprogram control by the instruction memory 24 and the instruction decoder 25.
- FIG. 6 (a) is a block diagram showing a detailed configuration of the input buffer group 22. As shown in FIG.
- the input buffer group 22 includes eight latches 221, which supply pixel data to the pixel transfer unit 17, and pixel data to the pixel processing units 1 to 16. It is composed of 16 latch sections 22 2 for supplying pixel data and 8 latches 22 3 for supplying pixel data to the pixel transfer section 18. In these, the pixel data group is transferred from the external memory 220 via the dual port memory 100 under the control of the POUC 209.
- Each of the latch sections 222 has two latches for supplying pixel data to input ports A and B of the pixel processing section, and pixel data or a filter for input port C of the pixel processing section. It consists of a selection section 2 2 4 for supplying the coefficient.
- FIG. 6B is a block diagram showing a detailed configuration of the selection unit 222. As shown in FIG.
- the selection unit 224 includes eight latches 224a to 224h and a selector for selecting any one of the data from the eight latches. It consists of 2 2 4 i.
- Latches 224a to 224h hold filter coefficients a0 to a7 (or a0 / 2, al to a7) in the filter processing. These filter coefficients are obtained by the POUC 209 from the external memory 220 through the dual port memory 100, and the latches 224a to 224. Transferred to h.
- the selectors 224i are sequentially selected from the latches 224a to 224h in synchronization with the clock. In this way, the supply of the filter coefficient to the pixel processing unit is not directly controlled by the microcode, but rather by the DDA circuit 27. The speed is increased because it is controlled by
- FIG. 7 is a block diagram showing the configuration of the output knob group 23.
- the output buffer group 23 is composed of 16 selectors 24a to 24p and 16 latches 23a to 23p. Become. Each of the selectors 24a to 24p receives 16 processing results of the pixel processing units 1 to 16, and selects one of them. This selection control is performed by the instruction decoder 25.
- Latches 23a to 23p hold the selection results of selectors 24a to 24p, respectively.
- the processing results of the pixel processing units 1 to 16 for 16 pixels are selected and stored in latches 23a to 23h, and furthermore, one of the pixel processing units 1 to 16 for the next 16 pixels is selected.
- eight selectors 24 i to 24 p select the processing results of pixel processing units 2, 4, 6, ... 16 and latch 23 Stored in i ⁇ 23 3 p. In this way, the pixels are thinned out, and 16 pixel data reduced by 1 to 2 is held in the output buffer group 23, and further controlled by the POUC 209. Transferred to the external memory 220 via the dual port memory 100.
- POUC 209 specifies the macro block to be filtered, and 32 pixel data and filter coefficient a0 / 0 for POUA207 or POUB208. 2, and al to a7 are transferred to the input buffer group 22 as initial values, and the instruction circuit 26 is notified of the number of taps and instructs the start of filter processing. I do.
- FIG. 8 is a diagram showing initial input values of pixel data in the case where file processing is performed by the pixel operation unit (POUA207).
- the input port column means each of the input ports shown in FIGS.
- the input pixel column means pixel data supplied from the input buffer group 22 to each input port.
- the output port column indicates the output port D (adder B output) shown in Figs. 4 and 5, and the output pixel column indicates the output value.
- the input buffer group 22 that supplies pixel data to the input port has 32 pixel data XI to X32 that are continuous in the horizontal direction as shown in Fig. 9, and the POUC 209 Transferred and retained.
- the target of the filter processing here is 16 pixel data X9 to X24. As shown in Fig. 8, pixel data X9 to X24 are selected for input ports A and B of pixel processing units 1 to 16 and input buffer group 22 is selected for input port C.
- the filter coefficient aO / 2 is supplied as the initial value.
- the number of taps corresponding to the number of taps desired for the filter processing is determined. Filter processing is performed by mouth input.
- FIG. 10 is an explanatory diagram showing the calculation process of the pixel processing unit 1 as a representative of the 16 pixel processing units.
- the contents held by the delay units A to D in the pixel processing unit 1 and the output value of the adder B are described for each number of input clocks.
- FIG. 11 shows the output value of output port D (output of adder B) for each clock input of pixel processing section 1.
- the pixel processing unit 1 uses the first clock input (CLK1) as the initial input value, and the delay units A and B use the pixel data X9, and the delay unit D uses the filter coefficient aO / 2 as the initial input value. Hold and delay]) are cleared to zero.
- the selection sections A and B have both selected the input port.
- adder A outputs (X9 + X9), multiplier A outputs (X9 + X9) * a0 / 2
- adder B outputs (X9 * a0 / 2 + 0 (that is, aO * X9). (See Figure 11).
- the selectors A and B select the shift output from the adjacent pixel processor or pixel transfer unit instead of the input ports A and B. .
- the adder B outputs aO * X9 + al (X10 + X8) (see Fig. 11).
- the filter coefficient al (delay C)
- the pixel processing unit 1 operates in the same way as the second clock input, so that the adder B sends aO * X9 + Output al (X 10 + x8) + a2 (X 11 + X7).
- the adder B By operating in the same manner at the fourth to ninth clock inputs (CLK4 to CLK9), the adder B outputs the output values shown in Fig. 11 respectively.
- Figures 10 and 11 show the process up to CLK9, but the number of input clocks is determined by the instruction decoder according to the number of taps notified from POUC209. It is aborted by the control of 25.
- each pixel processing unit ends the filter processing with CLK2 when the number of taps is three, ends with CLK3 when the number of taps is five, and uses CLK4 when the number of taps is seven.
- the filtering process ends.
- the filter processing of the number of taps (2n-1) ends with n clock inputs.
- the instruction decoder 25 repeats the parallel processing of 16 pixels for 16 lines, thereby completing the 4-block file processing.
- the 16 filter processing results are reduced or enlarged by being subjected to the thinning processing or the interpolation processing in the output filter group 23.
- the pixel group after the reduction or enlargement of the output buffer group 23 is controlled by the POUC 209 every time 16 pixels are retained, so that the output buffer group 23 is controlled via the dual port memory 100. Transferred to external memory 220.
- the instruction decoder 25 ends at POUC 209 at the end of the 16th line. Notify that The P0UC209 instructs the POUA207 to supply the initial input value and the filter coefficient and to start the filter processing for the next macro block in the same manner as described above.
- the pixel parallel processing unit 21 performs the filter processing on the 16 input pixels in parallel, and also controls the number of taps by controlling the number of input clocks. Can be optional.
- the input pixels of the input ports A, B, and C of the pixel processing unit 1 are (X9, X9, aO / 2), but (X9, 0, aO) or (0. X9, aO).
- the P 0 UC 209 instructs the instruction circuit 26 to start the MC processing, as well as the macro block (difference value) in the frame being decoded, which is the target of the MC processing. Identify the rectangular area pointed to by the motion vector in the reference frame, and specify POUA207 or POUB207.
- the pixel data P1 to P16 are set in the input buffer group 22.
- Figure 12 is a diagram showing the input and output pixel data when performing the MC processing (P picture) in the pixel operation unit.
- the input port column means the input ports of the pixel transfer unit 17, the pixel processing units 1 to 16, and the pixel transfer unit 18 shown in FIGS. 4 and 5.
- the input pixel column means pixel data input to the input port. Since the pixel transfer sections 17 and 18 are not used in the MC processing, the input pixels may be of any type (don't care).
- the output port column indicates the output port D (output of the adder B) shown in Figs. 4 and 5, and the output pixel column indicates the output value.
- FIG. 13 is an explanatory diagram of the input pixels to the pixel processing units 1 to 16 in the MC processing.
- D1 to D16 are 16 difference values in the macro block (MB) of the frame to be decoded.
- Pl to P16 are 16 pixel data in the rectangular area indicated by the motion vector in the reference frame.
- the selection units A and B in the pixel processing units 1 to 16 always select the input ports A and B, respectively.
- the pixel data from the input port A and the difference value from the input port B are input to and held by the delay units A and B via the selection units A and B, respectively.
- the result of this addition is multiplied by 1 in the multiplier, added to 0 in the adder B, and output from the output port D. That is, the pixel data from input port A and the difference value from input port B are simply added and output from output port D.
- the result of addition is stored in the output buffer group 23, and the external memory 220 is output by the POUC 209 via the dual port memory 100. Is written back to the decryption target frame in.
- the MC processing is performed by repeating the above processing for each 16-pixel unit of the frame to be decoded. Note that each pixel processing unit uses simple processing. Only the calculation is performed, and the addition result of 16 pixels can be obtained for each clock.
- FIG. 14 is a diagram showing input / output pixel data when the MC processing (B picture) is performed by the pixel operation unit.
- the input port column, input pixel column, output port column, and output pixel column are the same as in FIG.
- the input pixel column differs from Fig. 12 in that the input is divided into the first clock (CLK1) and the second clock (CLK2) twice.
- Pl to P16 and B1 to B16 are 16 pixel data in the rectangular area pointed to by the motion vector in two different reference frames.
- the selection units A and B in the pixel processing units 1 to 16 always select the input ports A and B, respectively.
- Pl and B1 are held in delay units A and B from input ports A and B via selectors A and B, and at the same time, a constant 1 It is held in the / 2 delay C.
- (P1 + B / 2 is obtained from the multiplier A.
- the multiplication result ( ⁇ 1 + ⁇ / 2) is held in the delay unit D.
- the result of the 16 additions is stored in the output buffer group 23, and is output to the external memory 220 via the dual port memory 100 by the POUC 209. It is written back to the decryption target frame in.
- the POUC 209 instructs the instruction circuit 26 to start OSD processing, and sequentially obtains 16 pixel data XI to XI from the OSD image stored in the external memory 220. Read 6 and set to input buffer group 22.
- FIG. 15 is a diagram showing input / output pixel data when an OSD (On Screen Display) process is performed in the pixel operation unit.
- OSD On Screen Display
- Pixel transfer sections 17 and 18 are not used.
- Pixel data X1 to X16 from input buffer group 22 are input to input port A of pixel processing units 1 to 16, 0 is input to input port B, and 0 is input to input port C. Is entered as 1.
- Figure 16 shows how 16 pixels in the OSD image are sequentially written to the input buffer group 22.
- Each of the selection units A and B in the pixel processing units 1 to 16 always selects an input port in the OSD processing.
- the addition result is multiplied by “1” input from input port C by multiplier A, and “0” is added by adder B.
- the pixel data XI of the input port A is output from the adder B as it is.
- the pixel data X2 to X16 of the input port A from the pixel processing units 2 to 16 are output from the adder B as they are.
- the pixel data XI to XI 6 output from the adder B are stored in the output buffer group 23, and the dual port memory 100 is further processed by the POUC 209. Overwrites the display frame data in the external memory 220 via By repeating the above processing for the entire OSD image as shown in Fig. 16, the OSD image in the external memory 220 is overwritten on the display frame data. You will be This is the simplest of the OSD processes, and the POUA207 or POUB208 simply relays the 0SD image in 16-pixel units.
- an OSD image and display frame data may be blended.
- the blend ratio is 0.5
- the pixel data of the OSD image is input to each of the input ports A of the pixel processing units 1 to 16 from the input buffer group 22 and the pixel data of the OSD image.
- the pixel data of the display frame data should be supplied to the input port B.
- the input ports A, B, and C of each pixel processing unit in the first port from the input buffer group 22 are used.
- the pixel data of the OSD image, 0, may be supplied in the second clock (0, the pixel data of the display frame data, 1—).
- the above-mentioned filtering process is applied to the OSD image from the input buffer group 22 and the display frame data from the output buffer group 23. You can overwrite and copy it to the position where you want to display it in reduced size.
- the blend may be performed after the OSD image is reduced by filter processing.
- Figure 17 is a diagram showing input / output pixel data when ME (motion estimation) processing is performed by the pixel operation unit.
- X1 to X16 are 16 pixels of the macroblock in the frame to be encoded
- R1 to R16 are 16 x 16 pixels in the reference frame. 16 pixels in the rectangular area.
- FIG. 18 is an explanatory diagram showing the relationship between these pixels.
- the motion vector (MV) search range in the reference frame in the figure is around the same position as the macroblock to be encoded (for example, +16 pixels in the horizontal and vertical directions). This is the range in which the motion vector (6 pixels) is searched.
- a rectangular area of 16 pixels XI 6 pixels exists at 16 XI 6 positions in a pixel-by-pixel search, and a half-pel (1 pixel) unit In the search for, there are 32 x 32 locations.
- Fig. 13 shows only the upper left rectangular area within the MV search range.
- the ME process calculates the sum of the differences between each pixel between each rectangular area within the MV search range and the macroblock to be coded, and further calculates the rectangle with the smallest sum.
- the motion vector is determined as the displacement of the relative position between the region (that is, the rectangular region with the highest correlation) and the macroblock to be coded. The difference between the block to be coded and the rectangular area with the highest correlation is taken.
- the input buffer group 22 has pixel data X1 to X16 to be coded and pixel data R1 to R1 in one rectangular area under the control of POUC209. ⁇ 6 and are transferred.
- the pixel data Rl to R16 in this rectangular area one line in the rectangular area is transferred for each clock. Therefore, R1 to R16 for 16 lines are transferred for one rectangular area.
- the pixel processing unit 1 shown in FIG. 4 uses the input port in the first clock.
- the pixel data XI of A and the pixel data R 1 of the input port B are subtracted and converted into absolute values by the adder A and passed through the multiplier A (multiplied by 1).
- the adder B outputs the sum of the multiplier output and the data held by the delay unit D. In the first clock, the adder B outputs the first line IXI-RI.
- the first line of I XI-R1 I is held in the delay device, so that the adder B outputs the second line of IX-R1 from the multiplier A. Add I and the first line IX input R1 I held in the delay device D.
- adders B accumulate the first and second lines of IX1-R1 I in the delay device, so that the adder B receives the third line of I xi- Ri I and the 1st line I XI -m I held in the delay unit]).
- the adder B calculates the accumulated value of IXI-R1I from 1 to 16 lines ( ⁇ I X1-R1
- the pixel processing units 2 to 16 also output the accumulated values ( ⁇ I Xl -Rl I;) to ( ⁇ I X16 -R16 I), respectively.
- the sum of the differences is similarly calculated for other rectangular areas within the MV search range.
- the rectangular area having the smallest value is determined to be the rectangular area having the highest correlation.
- a motion vector is generated.
- the sum of the 16 accumulated values from the pixel processing unit is separately calculated, but the sum of the 16 accumulated values is calculated in the pixel processing units 1 to 16. You may do it.
- 16 accumulated values for one rectangular area are saved from the output buffer group 23 to the work area of the external memory 220 as they are, and In this work area, the cumulative value group is stored for 6 or more rectangular areas.
- each of the pixel processing units 1 to 16 shares one rectangular area and sequentially accumulates 16 accumulated values, thereby obtaining the sum of the differences. I just need.
- the difference is calculated in pixel units, but may be calculated in half pel units.
- I XI-R1 I is calculated in one clock cycle for the actual line, as described above, between the half line and the actual line, and the neutral line is calculated. For example, for one clock out of two clocks, the pixel value of the North Pell is
- Fig. 19 is a schematic block diagram of the media processor, showing the flow of data when performing vertical filtering in the media processor shown in Fig. 2. is there.
- the decoder section 301 decodes (extends) the video elementary stream in FIG. 2 into VLD 205, TE 206 and POUA. This is equivalent to 2007 (MC processing), and decodes (decompresses) the video elementary stream.
- the frame memory 302 corresponds to the external memory 220 and holds video data (frame data) as a decoded result.
- the vertical filter 303 corresponds to POUB 208, and performs vertical reduction by vertical filter processing.
- the memory memory 304 corresponds to the external memory 220, and holds reduced video data (frame data for display).
- the image output section 305 is for video off-line memory 211, video This is equivalent to unit 2 13 and converts display frame data to video signals and outputs them.
- POU 207 is responsible for MC processing
- POU 208 is responsible for vertical filter processing.
- the reduction in the horizontal direction by the horizontal filter processing is performed by one of the POUA 207 and POUB 208 with respect to the decoded frame data of the frame memory 302. It shall be assumed.
- FIG. 20 is a diagram showing a time change of the data supply state of the frame memory 302 and the non-memory 304 when the 1/2 reduction processing is performed in FIG. It is.
- the vertical axes of the graphs 70 1 to 70 3 indicate the time in units of the period V of the vertical synchronization signal of the field. In the figure, five periods are shown, and the time axes of graphs 70 to 703 coincide.
- the horizontal axis of the graph 701 indicates the amount of frame memory 302 data.
- the horizontal axis of the graph 7702 indicates the amount of data in the memory 304.
- a graph 703 indicates a frame (field) being output in the image output unit 305.
- the solid line 704 in the graph 701 indicates the amount of frame data supplied from the decoder unit 301 to the frame memory 302.
- the broken line 705 indicates the amount of frame data supplied from the frame memory 302 to the vertical filter section 303.
- the broken line 706 in the graph 702 indicates the supply amount of the 1st field reduced image from the vertical filter section 303 to the buffer memory 304. I have.
- An alternate long and short dash line 707 indicates the supply amount of the 2nd field reduced image from the vertical filter section 303 to the buffer memory 304.
- the solid line 708 in the graph 702 is the reference memory 304. 1 shows the supply state of the 1st field reduced image data to the image output unit 305.
- the display position of the reduced image is from the upper half position of the frame to the lower half position, so the solid line 709 in the figure indicates the timing according to the display position.
- a solid line 709 indicates the state of supply of the 2nd field reduced image data from the buffer memory 304 to the image output unit 305.
- the supply of the n-th frame data from the decoder unit 301 to the frame memory 302 is the second frame of the n-1 frame. It starts immediately after the supply of the field from the frame memory 302 to the vertical filter section 303 and starts from the frame memory 302 to the vertical filter section 30.
- the supply of the nth frame to frame 3 is from the nth frame of the 1st field frame memory 302 to just before the completion of the supply to the vertical filter section 303.
- the control is performed so as to end with.
- the frame data of the 1st field of the nth frame from the vertical filter section 303 to the non- Supply is during the display of the 2nd field of the n-1 frame, while supply of the frame data of the 2nd field of the n frame is during the display of the 1st field of the n frame Control is performed so that each is completed.
- one frame of frame data is transferred between the decoder unit 301 and the frame memory 302 during a period of 2 V.
- the ability to do so is sufficient.
- From the frame memory 302 to the vertical filter section 303 it is sufficient to have the ability to transfer 1/2 frame data during a 1 V period.
- the decoder section 301 is capable of generating one frame of frame data during the period of 2 V, and the vertical filter section 303 is one-half during the period of IV. It is sufficient to have the computing power to filter the frame data of the frame.
- the vertical filter section 303 and the notch memory 304 it is sufficient to have the ability to transfer 1/4 frame data during the IV period. is there.
- the frame memory 304 holds the frame data 1 frame, and the not frame memory 304 stores the frame data 1/2 frame. It is enough to have the capacity to hold the system.
- FIG. 21 shows a time change of a data supply state in a case where the no-fault memory 304 is not provided.
- the supply of the n-frame digital image data to the frame memory 302 is performed as indicated by a broken line 507 as indicated by a solid line 506 as indicated by a solid line 506. It starts from the time when supply to the vertical filter section 303 of the second field of one frame starts, and the first frame of the n frame shown by the broken line 508 It ends before the supply of the field to the vertical filter section 303 is completed. Therefore, one frame of digital image data is supplied at a constant speed during the 2 V period shown on the graph in FIG.
- the supply of digital image data from the frame memory 302 of the 1st field of the nth frame to the vertical filter section 303 is broken. As indicated by 508, the processing is completed immediately after the supply of the n-frame digital image data to the frame memory 302 shown by the solid line 511 is completed, followed by 2 Start processing the nd field. For this reason, the supply of digital image data from the frame memory 302 to the vertical filter section 303 requires one frame during the 1 V period shown on the graph of FIG. Digital image data of the field is supplied at a constant speed. However, when performing 1/2 reduction processing, the timing at which the supply of n-frame digital image data to the frame memory 302 can be started is as follows. Depends on the display position of the 2nd field of the n-1 frame.
- the supply of digital image data from the frame memory 302 to the vertical filter section 303 is indicated by a broken line. Timing that is performed somewhere between 509 and 510 to enable the start of supply of n-frame digital image data to frame memory 302 The time is the most delayed in the case of the display position indicated by the broken line 5110. In this case, the 1/2 reduced image is output to the lower half of the image output section 501, and n-frame digital image data is supplied to the frame memory 302. It must be completed before the supply to the vertical filter section 303 of the 1st field of the n frame indicated by the broken line 5 1 1 is completed. Therefore, it is necessary to supply one frame of digital image data at a constant speed during the 1 V period shown on the graph of FIG. 21, which is twice as large as that without reduction. Supply capacity is required.
- the supply of digital image data from the frame memory 302 of the 1st field of the nth frame to the vertical filter section 303 is indicated by a broken line 5111.
- the processing is completed immediately after the supply of the n-frame digital image data to the frame memory 302 shown by the solid line 512 is completed, followed by the 2nd field. Starts processing the code. Therefore, it is necessary to supply one field of digital image data at a constant speed during the 1/2 V period shown on the graph of FIG. 5, and if no reduction is performed, Double the supply capacity is required. Since the vertical filter section 303 is required to have the performance corresponding to the supplied digital image data, the vertical filter section 303 requires twice as much computing capacity as compared to the case where no reduction is performed.
- Fig. 23 shows the data supply state in the case where no memory memory 304 is provided and 1/4 reduction processing is performed, for comparison with Fig. 20. Of FIG.
- Figure 23 shows a graph when performing 1/4 reduction processing.
- the computational power of the vertical filter needs to be four times that of the case without reduction processing.
- the non-memory memory 304 is not provided, as the reduction ratio increases, the required peak performance also increases.
- FIG. 22 is a diagram showing a data supply state of each part and its time change when performing 1/4 reduction by the media processor shown in FIG.
- the horizontal and vertical axes of the graph are the same as in FIG.
- the solid line 804 on the graph indicates the state of supply of frame data from the decoder unit 301 to the frame memory 302.
- a broken line 805 on the graph indicates a state of supplying frame data from the frame memory 302 to the vertical filter section 303.
- a dashed line 806 on the graph indicates the supply state of the 1st field reduced image data from the vertical filter section 303 to the no-floor memory 304.
- a broken line 807 on the graph indicates the supply state of the 2nd field reduced image data from the vertical filter section 303 to the no-floor memory 304. .
- a solid line 808 on the graph indicates a supply state of the 1st field reduced image data from the no-fault memory 304 to the image output unit 305.
- a solid line 809 on the graph indicates a supply state of the second field reduced image data from the non-memory 304 to the image output unit 305.
- the vertical filter section 303 is capable of filtering half-frame data during the 1 V period, and has a calculation capability. Between the memory 304 and the image output unit 305 from the memory device 304 to the image output unit 305 during the IV period. An 8-frame frame data transfer capability is sufficient. Frame memory 302 that can hold frame data 1 frame and Knob memory 304 that can hold frame data 1/4 frame are required. .
- Each of these required performances is the average performance at least in the IV period, and even if the reduction ratio is large, a large peak performance is not required in a short period.
- the processing performance is most required in the case of no reduction.
- one frame frame overnight transfer capacity of 2 V is sufficient.
- a frame data transfer capacity of 1/2 frame during the period IV is sufficient.
- the decoder section 301 needs only the computing capacity to generate one frame of frame data during a period of 2 V.
- the vertical filter section 303 needs only the computing capacity to filter 1/2 frame data during the IV period.
- a half-frame frame data transfer capacity in a 1 V period is sufficient.
- Image from the memory memory 304 Between the image output sections 305, a half frame frame transfer capability of one-half frame during the IV period is sufficient. It is only necessary that the frame memory 302 can hold the frame data 1 frame, and the no-floor memory 304 can hold the frame data 1 frame. This ability can perform any vertical reduction process. As a result, the circuit scale can be reduced, and the operating clock can be reduced.
- FIG. 24 is a schematic block diagram showing the flow of data when performing vertical filtering in a media processor.
- the figure shows a decoder section 401, a non-filter memory section 402, a vertical filter section 403, a non-filter memory section 404, a video output section 405,
- the control unit consists of 406.
- the figure shows that the decode section 401, the vertical filter section 403, the off-chip memory section 404, and the video output section 405 have the same configuration. Same as element. Therefore, the description of the same points is omitted, and different points will be mainly described.
- the buffer memory 402 differs from the frame memory 302 in that it requires less storage space than one frame of storage.
- the vertical filter section 403 is controlled by the control section every time the filter processing of 64 lines in the vertical direction (4 macroblock lines in the frame before processing) is completed. This is different from the vertical filter section 303 in that it notifies the filter to that effect (filter state).
- the unit of notification may be 2 to 3 units of macro block line.
- the decoding unit 401 is configured to notify the control unit 406 of the fact (decoding state) to the control unit 406 each time the decoding in the unit of 64 lines is completed. Is different.
- the unit of notification may be 16 lines.
- the control section 406 corresponds to the IOP 211 in FIG. 2, and controls the operation states of the decode section 401 and the vertical filter section 403 respectively. Monitoring is performed based on these notifications, so that the vertical filter processing does not exceed the decoding processing, and the decoding processing does not pass the vertical filtering processing. And the vertical filter section 403. That is, the following two of the control sections 406 are controlled.
- One is that the decoder section 401 writes the pixel data group of the macro-procedure line to be filtered to the buffer memory 402. Even though there is no filter, the vertical filter section 4003 performs filtering on the pixel data group of the macro block line in the previous frame (or field) This is to prevent this.
- the other is that the vertical filter section 403 is the target of vertical filter processing but the macro section is not processed. This is to prevent the pixel data group of the frame from being overwritten.
- FIG. 25 is an explanatory diagram showing the control contents in the control unit 406.
- the horizontal axis in the figure is time, and the control unit 406, VSYNC (vertical synchronization signal), decode unit 401, vertical filter unit 403, and video output unit 405 Each operation is described.
- the decoder section 401 notifies the control section 406 each time the decoding of the line is completed, and the vertical filter section 403 notifies the control section 406 of the completion. Each time the filtering of 4 lines is completed, this is notified to the control unit 400.
- the control unit 406 holds and updates the line number Nd for which decoding has been completed and the line number Nf for which filtering has been completed under these notifications, and Nd ( In order to satisfy Nf (current frame)> Nf (current frame), Nd (next frame), Nf (current frame), the decoding section 401, vertical frame Controls the filter section 403.
- control unit 406 sets the decode unit 4 ⁇ 1 and the vertical unit when Nd and Nf approach each other (when the difference falls below a threshold value). Temporarily stop one of the filter sections 403. Note that Nd and Nf may be macroblock line numbers.
- one of the decoding unit 410 and the vertical filter unit 403 is controlled by the control unit 406.
- the control to determine whether or not Nd and Nf approach each other and to temporarily stop the decode unit 410 or the vertical filter unit 400 are not performed.
- the configuration may be such that a unit other than the control unit 406 is in charge.
- the vertical filter section 403 notifies the decoder section 401 of the above-mentioned filter state, and the decoder section 401 notifies the filter state of the filter state. It is determined whether or not Nd and Nf have approached each other according to and the internal decoding state, and the decoding operation is temporarily stopped or the vertical filter section 40 is determined according to the determination result. 3 may be temporarily stopped.
- the decoder unit 401 notifies the vertical filter unit 403 of the above-mentioned decoding state, and the vertical filter unit 4003 Based on the notification of the decoding state and the internal filtering state, it is determined whether Nd and Nf have approached each other, and the filter processing is temporarily stopped or decoupling is performed according to the determination result.
- the configuration may be such that the load section 401 is temporarily stopped.
- FIG. 26 is a diagram showing the amount of data supplied to each unit when performing the 1/2 reduction processing in FIG.
- the horizontal axis of the graph 901 indicates the amount of frame data stored in the memory memory 402, and the vertical axis indicates the time.
- the horizontal axis of the graph 902 indicates the amount of frame data in the memory 404, and the vertical axis indicates the time.
- the graph 903 is a state in which the states of the image output unit 405 are arranged in chronological order, and the time axis is graphs 901 and 902. It is in line with the vertical axis.
- the solid line 904 on the graph indicates the state of supply of frame data from the decoder unit 401 to the no-flag memory 402.
- a dashed line 905 on the graph indicates a state of supplying frame data from the non-memory 404 to the vertical filter 403.
- a broken line 906 on the graph indicates the supply state of the 1st field reduced image data from the vertical filter section 403 to the no-floor memory 404.
- a dashed line 907 on the graph indicates the supply state of the 2nd field reduced image data from the vertical filter section 403 to the no-flip memory 404.
- a solid line 908 on the graph indicates a supply state of the 1st field reduced image data from the no-memory 404 to the image output unit 405.
- the solid line 909 on the graph indicates the state of supply of the 2nd field reduced image data from the no-memory 404 to the image output unit 405.
- n-frame data from the decoder section 401 to the no-fault memory 402 starts. Immediately after this, supply of n-frame frame data from the no-memory 402 to the vertical filter section 403 is started, and the decoder section 40 Immediately after the supply of n frames of frame data from the memory 1 to the memory 400 is completed, the vertical memory is transferred from the memory 402 immediately after the supply of the frame data ends. Control is performed so that the supply of frame data of n frames to the router section 403 ends. As shown by the graph 902, the supply of the n-frame frame data from the vertical filter section 403 to the non-memory 404 is n_ l Control to complete while displaying the frame.
- a frame of 1 frame is provided between the decoder section 401 and the buffer memory 402 during a period of 2 V.
- Data transfer capability, vertical filter section from NOF memory 402 During the period of 400 V, one frame of frame data can be transferred during the period of 2 V, and the decoder unit 401 can transmit one frame of the frame data during the period of 2 V.
- the computing capacity to generate and the vertical filter section 403 are the computing capacity to filter one frame of frame data during the 2 V period, and the vertical filter section 4 From 0 3 to the no-f memory 4 0 4, the frame data transfer capacity of 1/2 frame during the 2 V period, from the buffer memory 4 0 4 Between the image output sections 405, a 1/4 frame of frame data transfer capability and a no-floor memory that can hold several lines of frame data during a 1 V period 2. Frame data Each of the memory modules 404 that can hold one frame is required. ⁇ 3.2.2 1 Z 4 reduction>
- FIG. 27 is a diagram showing the overnight supply amount of each part when the quarter is reduced in FIG.
- the horizontal axis of the graph 1001 indicates the amount of frame data on the memory 104, and the vertical axis indicates the time.
- the horizontal axis of the graph 1002 indicates the amount of frame data on the memory 104, and the vertical axis indicates the time.
- the graph 1003 is obtained by arranging the states of the image output unit 405 in chronological order, and the time axis is aligned with the vertical axes of the graphs 1001 and 1002.
- the solid line 1004 on the graph indicates the state of supply of frame data from the decoder section 401 to the no-flag memory 402.
- a broken line 1005 on the graph indicates a state in which frame data is supplied from the non-memory 4002 to the vertical filter section 4003.
- the broken line 1006 on the graph is from the vertical filter section 4.03 to the Knob memory.
- the broken line 1007 on the graph indicates the supply state of the 2nd field reduced image data from the vertical filter section 403 to the buffer memory 404.
- the solid line 1008 on the graph is the buffer Shows the supply state of 1st field reduced image data from the memory 404 to the image output unit 405.
- a solid line 1109 on the graph indicates a supply state of the 2nd field reduced image data from the no-memory 404 to the image output unit 405.
- a frame of 1 frame is provided between the decoder section 401 and the no-flag memory 402 during a period of 2 V. Data transfer capability is sufficient.
- a frame data transfer capacity of one frame is sufficient for a period of 2 V, and the decoder
- the section 401 has enough computing power to generate one frame of data during the period of 2 V, and the vertical filter section 403 is capable of generating one frame of data during the period of 2 V.
- the computing capacity for filtering is sufficient, and between the vertical filter section 403 and the non-memory 404 is 1/4 frame during the 2 V period.
- One frame data transfer capability is sufficient, and between the buffer memory 404 and the image output unit 405, a 1/8 frame frame data transfer capability during the 1 V period is sufficient. Yes.
- the buffer memory 402 can hold several lines of frame data, and the buffer memory 404 can hold half a frame data. Is enough.
- Each of these required performances is the average capability during the period of the IV at the shortest, and a large peak performance is not required in the period in which the reduction ratio is short.
- a request is made between the decoder section 401 and the non-memory 404. Is the frame data transfer capacity of one frame during the period of 2 V, and the interval between the non-memory 402 and the vertical filter section 403 is the period of 2 V. 1 frame of frame data transfer capability, the decoder section 401 generates 1 frame of frame data during the 2 V period The vertical filter section 403 is capable of filtering one frame of frame data during the 2 V period, and the vertical filter section 403 is notched.
- the frame data transfer capability of one frame during the period of 2 V the image data output from the memory 404 to the image output unit 405 During this period, a half-frame frame transfer rate of 1 V during a 1 V period, a buffer memory 402 that can hold several lines of frame data, and a frame memory A buffer memory 404 that can hold 2 frames of frame data.
- This capability can perform any vertical reduction processing. As a result, the circuit scale can be reduced, and the operating clock can be reduced.
- FIGS. 28 and 29 are diagrams showing a first modified example of the left half and the right half of the pixel parallel processing unit.
- the same components as those in FIGS. 3 and 4 are denoted by the same reference numerals, and the description thereof will be omitted, and different points will be mainly described.
- Figures 28 and 29 show the pixel processing sections la to 16a in place of the pixel processing sections 1 to 16 in Figs. 3 and 4, and the pixel transfer section instead of the pixel transfer sections 17 and 18 in Figs. It has 17a and 18b. Since the pixel processing units la to 16a have the same configuration, the pixel processing unit 1a will be described as a representative.
- the pixel processing unit la includes a selection unit A104a and a selection unit B105a instead of the selection unit A104 and the selection unit B105 in the pixel processing unit 1.
- the selection section A l 0 4a has two inputs compared to the selection section A 104.
- the selection section A104a is
- Pixel data input is increasing from the delay unit (delay unit B) of the pixel transfer unit (or pixel processing unit) next to it.
- the selection section B 105 a is similarly connected to the next adjacent pixel transfer section (or pixel).
- the pixel data input to the delay unit (delay unit B) in the processing unit is increasing.
- the pixel transfer section 17a includes a selection section B1703a to a selection section G1708a instead of the selection section B1773 to the selection section G1708.
- the selection unit Bl703a to selection unit Gl708a are three inputs instead of two inputs, respectively.
- the increasing input is the pixel data input from the two left delays.
- the pixel transfer section 18a includes a selection section Bl803a to a selection section Gl808a instead of the selection section B1803 to the selection section G1808.
- the selection unit Bl 803 a to the selection unit Gl 808 a have three inputs instead of two inputs, respectively. The increasing input is the pixel data input from the two delay units to the right.
- the pixel processing unit 1a can calculate the following equation.
- FIGS. 30 and 31 are diagrams illustrating a second modification of the left half and the right half of the pixel parallel processing unit.
- FIGS. 30 and 31 include a pixel processing unit 1b and a pixel processing unit 16b instead of the pixel processing unit 1 and the pixel processing unit 16 in FIGS.
- the pixel processing unit 1 b includes a selection unit b 105 b instead of the selection unit B 105 in the pixel processing unit 1.
- the selection unit B105B differs from the selection unit B105 in that it has a feedback input from the delay unit B107.
- the pixel processing section 16b includes a selection section A164b instead of the selection section A164 in the pixel processing section 16.
- the selection unit A1664b is different from the selection unit A1655 in that it has a feed knock input from the delay unit A1666. According to this configuration, the pixel processing unit 1b performs, for example, the following calculation. a3 * X6 + a2 * X7 + al * X8 + a0 * X9 + al * X10 + a2 * Xll + a3 * X12
- the output of the pixel processing unit 2 is as follows.
- the output of the pixel processing unit 16b is as follows.
- the left end of the pixel processing unit lb is the left end of the column
- the selection unit B105b selects the feed knock input from the delay unit B in the pixel processing unit 1b.
- the selector A1664b feeds the data from the delay unit A1666. Select the packing input.
- FIGS. 32 and 33 are diagrams showing a second modification of the left half and the right half of the pixel parallel processing unit.
- Figures 3 2 and 3 3 show the pixel processing sections 1 c to 16 c instead of the pixel processing sections 1 to 16 in FIGS. 3 and 4, and the pixel transfer section instead of the pixel transfer sections 17 and 18 in FIGS. 17 c and 18 c are provided.
- Pixel processing section l c-: I 6 c has the same configuration, and therefore, the pixel processing section 1 a will be described as a representative.
- the pixel processing unit 1 c includes a selection unit A 104 c and a selection unit B 105 c instead of the selection unit A 104 and the selection unit B 105 in the pixel processing unit 1.
- the selection unit A104c is different from the selection unit A104 in that the number of inputs is changed from two to three. That is, in the selection unit A104c, the number of pixel data inputs to the delay unit (delay unit B) of the pixel transfer unit (or the pixel processing unit) adjacent to the two is increased.
- the selection unit BlO5c includes a pixel data input of a delay unit (delay unit B) of a pixel transfer unit (or a pixel processing unit) of two adjacent pixels, and a feed from the delay unit B107. Knock input and are increasing.
- the pixel transfer units 17c and 18c have three inputs instead of two inputs, similarly to the pixel transfer units 17a and 18a shown in FIGS. 28 and 29.
- the pixel processing unit 1c performs, for example, the following calculation. a3 * X9 + a2 * X9 + al * X9 + aO * X9 + al * Xl 1 + a2 * X13 + a3 * X15
- the output of the pixel processing unit 2 c is as follows.
- the output of the pixel processing unit 15c is as follows.
- the output of the pixel processing unit 16 c is as follows.
- FIG. 34 is a diagram showing a modified example of POUUA207.
- the POU 207 in the figure is different from that in FIG. 2 in that an upsampling circuit 22a and a downsampling circuit 23a are added.
- the description of the same points as those in Fig. 2 is omitted, and the description focuses on the differences.
- the up-sampling circuit 22a vertically expands the pixel data group input from the input canopy group 22. For example, in order to interpolate pixel data to double the pixel data group input from the input buffer group 22 in the vertical direction, the input buffer group 22 The same pixel data group is output to the pixel parallel processing unit 21 twice for each input of the pixel data group.
- the down sampling circuit 23a vertically reduces the pixel data group input from the pixel parallel processing unit 21. For example, pixel data is thinned out so that the pixel data group input from the pixel parallel processing unit 21 is vertically multiplied by 12 times. In other words, in response to the input of the pixel data group from the pixel parallel processing unit 21 twice, one input is discarded and one output is output.
- the input side of the pixel parallel processing unit 21 has a vertical 2 times in the output direction and 1 to 2 times in the vertical direction on the output side, so that the amount of data per frame in the external memory 220 can be reduced by half in the vertical direction.
- the data transfer amount to the POUA 207 by the POUC 209 can be reduced by one to two.
- the bus connection can be eliminated.
- the pixel arithmetic device of the present invention performs the file ring processing for resizing an image in parallel with respect to a plurality of pixels, it performs compression processing, decompression processing, and resizing of a moving image. Used in digital video equipment such as media processors that handle it.
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Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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EP01938474A EP1278157A1 (en) | 2000-04-21 | 2001-04-23 | Pixel calculating device |
US10/019,419 US6809777B2 (en) | 2000-04-21 | 2001-04-23 | Pixel calculating device |
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JP2000120753 | 2000-04-21 | ||
JP2000-120753 | 2000-04-21 | ||
JP2000120754 | 2000-04-21 | ||
JP2000-120754 | 2000-04-21 |
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WO2001082227A1 true WO2001082227A1 (en) | 2001-11-01 |
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PCT/IB2001/000665 WO2001082227A1 (en) | 2000-04-21 | 2001-04-23 | Pixel calculating device |
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US (1) | US6809777B2 (ja) |
EP (1) | EP1278157A1 (ja) |
KR (1) | KR100794098B1 (ja) |
CN (1) | CN1269076C (ja) |
WO (1) | WO2001082227A1 (ja) |
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US7315934B2 (en) * | 2002-03-06 | 2008-01-01 | Matsushita Electric Industrial Co., Ltd. | Data processor and program for processing a data matrix |
US7882164B1 (en) * | 2004-09-24 | 2011-02-01 | University Of Southern California | Image convolution engine optimized for use in programmable gate arrays |
JP2011035655A (ja) * | 2009-07-31 | 2011-02-17 | Sanyo Electric Co Ltd | フレームレート変換装置、およびそれを搭載した表示装置 |
US10410575B2 (en) * | 2017-07-19 | 2019-09-10 | Apple Inc. | Adjustable underrun outputs |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO1998029832A1 (fr) * | 1996-12-25 | 1998-07-09 | Sony Corporation | Processeur d'images, processeur de donnees et procedes correspondants |
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US4802111A (en) * | 1986-03-10 | 1989-01-31 | Zoran Corporation | Cascadable digital filter processor employing moving coefficients |
US5227863A (en) * | 1989-11-14 | 1993-07-13 | Intelligent Resources Integrated Systems, Inc. | Programmable digital video processing system |
JPH0548388A (ja) | 1991-08-20 | 1993-02-26 | Rohm Co Ltd | デイジタルフイルタ |
US5315700A (en) * | 1992-02-18 | 1994-05-24 | Neopath, Inc. | Method and apparatus for rapidly processing data sequences |
US5600582A (en) * | 1994-04-05 | 1997-02-04 | Texas Instruments Incorporated | Programmable horizontal line filter implemented with synchronous vector processor |
JP2944439B2 (ja) * | 1994-12-27 | 1999-09-06 | シャープ株式会社 | 手書き文字入力装置および方法 |
US5528301A (en) * | 1995-03-31 | 1996-06-18 | Panasonic Technologies, Inc. | Universal video format sample size converter |
US5587742A (en) * | 1995-08-25 | 1996-12-24 | Panasonic Technologies, Inc. | Flexible parallel processing architecture for video resizing |
CA2246536C (en) | 1996-12-25 | 2007-08-21 | Sony Corporation | Image processor, data processor, and their methods |
US6681059B1 (en) * | 1998-07-28 | 2004-01-20 | Dvdo, Inc. | Method and apparatus for efficient video scaling |
US6154761A (en) * | 1999-02-12 | 2000-11-28 | Sony Corporation | Classified adaptive multiple processing system |
-
2001
- 2001-04-23 CN CNB018017355A patent/CN1269076C/zh not_active Expired - Fee Related
- 2001-04-23 US US10/019,419 patent/US6809777B2/en not_active Expired - Lifetime
- 2001-04-23 WO PCT/IB2001/000665 patent/WO2001082227A1/ja active Application Filing
- 2001-04-23 EP EP01938474A patent/EP1278157A1/en not_active Withdrawn
- 2001-04-23 KR KR1020017016382A patent/KR100794098B1/ko not_active IP Right Cessation
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Publication number | Priority date | Publication date | Assignee | Title |
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WO1998029832A1 (fr) * | 1996-12-25 | 1998-07-09 | Sony Corporation | Processeur d'images, processeur de donnees et procedes correspondants |
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Publication number | Publication date |
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US6809777B2 (en) | 2004-10-26 |
KR100794098B1 (ko) | 2008-01-10 |
KR20020025899A (ko) | 2002-04-04 |
US20020106136A1 (en) | 2002-08-08 |
CN1269076C (zh) | 2006-08-09 |
EP1278157A1 (en) | 2003-01-22 |
CN1383529A (zh) | 2002-12-04 |
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