WO2001080295A1 - Procedes destines a la formation de jonctions tres peu profondes dans des plaquettes semi-conductrices par implantation d'azote - Google Patents

Procedes destines a la formation de jonctions tres peu profondes dans des plaquettes semi-conductrices par implantation d'azote Download PDF

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Publication number
WO2001080295A1
WO2001080295A1 PCT/US2001/012377 US0112377W WO0180295A1 WO 2001080295 A1 WO2001080295 A1 WO 2001080295A1 US 0112377 W US0112377 W US 0112377W WO 0180295 A1 WO0180295 A1 WO 0180295A1
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WO
WIPO (PCT)
Prior art keywords
nitrogen
implanting
boron
semiconductor wafer
kev
Prior art date
Application number
PCT/US2001/012377
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English (en)
Inventor
Sandeep Mehta
Naushad Kizhakevariam
Ukyo Jeong
Jinning Liu
Original Assignee
Varian Semiconductor Equipment Associates, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Varian Semiconductor Equipment Associates, Inc. filed Critical Varian Semiconductor Equipment Associates, Inc.
Publication of WO2001080295A1 publication Critical patent/WO2001080295A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • This invention relates to methods for forming ultrashallow junctions in semiconductor wafers by ion implantation and, more particularly, to methods for achieving ultrashallow junctions by implanting nitrogen and a dopant material into the semiconductor wafer at low energies.
  • Ion implantation is a standard technique for introducing conductivity-altering dopant materials into semiconductor wafers.
  • a desired dopant material is ionized in an ion source, the ions are accelerated to form an ion beam of 5 prescribed energy, and the ion beam is directed at the surface of the wafer.
  • the energetic ions in the ion beam penetrate into the bulk of the semiconductor material and are imbedded into the crystalline lattice of the semiconductor material.
  • the semiconductor wafer is annealed to activate the dopant material. Annealing involves heating the semiconductor wafer to a prescribed temperature for a prescribed time. 0
  • a well-known trend in the semiconductor industry is toward smaller, higher speed devices.
  • both the lateral dimensions and the depths of features in semiconductor devices are decreasing.
  • State of the art semiconductor devices require junction depths less than 1000 angstroms and may eventually require junction depths on the order of 200 angstroms or less. 5
  • the implanted depth of the dopant material is determined by the energy of the ions implanted into the semiconductor wafer. Shallow junctions are obtained with low implant energies.
  • the annealing process that is used for activation of the implanted dopant material causes the dopant material to diffuse from the implanted region of the semiconductor wafer. As a result of such diffusion, junction depths are increased by annealing.
  • the implant energy may be decreased, so that a desired junction depth after annealing is obtained.
  • This approach provides satisfactory results, except in the case of ultrashallow junctions.
  • a limit is reached as to the junction depth that can be obtained by decreasing implant energy, due to the diffusion of the dopant material that occurs during annealing.
  • Rapid thermal processing can be used to minimize the diffusion that occurs during annealing.
  • significant changes to the annealing process such as reduced annealing temperatures, would reduce the amount of dopant material activated and would adversely affect the operating characteristics of the semiconductor device.
  • Numerous efforts have been made to select thermal processing parameters which limit diffusion of the dopant material while achieving activation of the dopant material.
  • diffusion of the dopant material such as boron
  • diffusion of the dopant material can occur by several mechanisms. These include the intrinsic diffusion of boron as well as mechanisms attributed to transient enhanced diffusion (TED). This enhanced diffusion is attributed to a diffusion mechanism promoted by interstitial point defects introduced either during implant or thermal processing.
  • TED transient enhanced diffusion
  • a relatively high dose of boron is required for optimal electrical characteristics. Implanted boron doses of lE14-3E15/cm 2 are typically utilized. At these high doses, intrinsic diffusion combined with boron enhanced diffusion limit the shallowness of the junction.
  • a method for forming a shallow junction in a semiconductor wafer.
  • the method comprises the steps of implanting boron into the semiconductor wafer for forming a shallow junction, implanting nitrogen into the semiconductor wafer at an energy less than 10 keV, and activating the boron by thermal processing of the semiconductor wafer at a selected temperature for a selected time to form the shallow junction.
  • the energy of the nitrogen is selected such that the implanted depth of the nitrogen is approximately equal to or less than the implanted depth of the boron.
  • boron is implanted with energies at or below 1 keV
  • nitrogen is implanted with energies at or below 5 keV.
  • the nitrogen implant dose is preferably greater than about 2.5E14/cm .
  • boron is implanted at 1 keV and nitrogen is implanted at or below 2.6 keV.
  • boron is implanted at 500 eV and nitrogen is implanted at or below 1.3 keV.
  • boron is implanted at 250 eV and nitrogen is implanted at or below 0.6 keV.
  • the step of implanting boron may comprise implanting B + ions or BF 2 ions, and the step of implanting nitrogen may comprise implanting N 2 ions.
  • the step of implanting nitrogen may be performed before or after the step of implanting boron.
  • a method for forming a shallow junction in a semiconductor wafer.
  • the method comprises the steps of implanting a dopant material into the semiconductor wafer for forming a shallow junction, implanting nitrogen into the semiconductor wafer at an energy less than 10 keV, and activating the dopant material by thermal processing of the semiconductor wafer at a selected temperature for a selected time to form the shallow junction.
  • the energy of the nitrogen is selected such that the implanted depth of the nitrogen is approximately equal to or less than the implanted depth of the dopant material.
  • the nitrogen implant retards diffusion of the dopant material during thermal processing and thereby permits ultrashallow junctions to be fabricated.
  • the nitrogen implant does not adversely effect the characteristics of the devices being fabricated on the semiconductor wafer.
  • Fig. 1 is a simplified, partial cross-sectional view of a semiconductor wafer
  • Figs. 2 A and 2B are flow charts showing examples of processes for fabricating ultrashallow junctions in semiconductor wafers in accordance with the invention
  • Fig. 3 is a graph of boron concentration in atoms per cubic centimeter as a function of depth in angstroms for different processes, including an embodiment of the nitrogen process of the present invention
  • Fig. 4 is a graph of boron concentration in atoms per cubic centimeter as a function of depth in angstroms for nitrogen implants of 1.3 keV and 15 keV;
  • Fig. 5 is a graph of boron concentration in atoms per cubic centimeter as a function of depth in angstroms for different nitrogen implant doses.
  • FIG. 1 A highly simplified, partial cross-sectional view of a semiconductor wafer 10 is shown in Fig. 1.
  • An ion beam 12 of a dopant material is directed at wafer 10, producing an implanted region 14.
  • the boundaries of implanted region 14 are typically defined by an implant mask 16.
  • the wafer is then annealed, typically in a rapid thermal processor, to activate the dopant material.
  • the annealing process causes diffusion of the dopant material to an impurity region 20 that is larger than the implanted region 14.
  • the impurity region 20 is characterized by a junction depth X j , which is the depth of the impurity region 20 normal to the surface of wafer 10.
  • the increase injunction depth produced by annealing places a lower limit on the junction depth Xj that can be achieved.
  • junction depths X j may be reduced in comparison with prior art processes by utilizing a low energy nitrogen implant in conjunction with the dopant material implant to retard diffusion during annealing.
  • nitrogen may be implanted prior to low energy boron implantation.
  • nitrogen may be implanted following low energy boron implantation.
  • the nitrogen energy and dose are selected based on the boron energy and dose.
  • nitrogen in the form of N 2 + ions is implanted at an energy less than about 10 keV and a dose greater than about 2.5E14/cm 2 .
  • the notation 2.5E14/cm 2 represents an implant dose of 2.5 x 10 14 atoms per cubic centimeter.
  • the energy of the nitrogen is selected such that the implanted depth of the nitrogen is approximately equal to or less than the implanted depth of the boron.
  • the boron is activated by thermal processing of the semiconductor wafer using process parameters selected to minimize diffusion of the boron.
  • the nitrogen implant process may be utilized with other dopant materials, such as arsenic and phosphorous.
  • step 50 the dose and energy of the nitrogen implant are selected based on the dose and energy of the dopant material implant.
  • the energy of the nitrogen is selected such that the implanted depth of the nitrogen is approximately equal to or less than the implanted depth of the dopant material. Nitrogen energies less than about 10 keV are typically utilized. Specific examples are given below.
  • the nitrogen dose is typically greater than about 2.5E14/cm 2 . In general, the nitrogen dose increases with increasing dose of dopant material.
  • step 52 the nitrogen is implanted into the semiconductor wafer at the selected dose and energy.
  • the dopant material such as boron, is implanted into the semiconductor wafer.
  • a single implant mask may be used for the nitrogen and dopant material implants.
  • the process may be utilized, for example, in the fabrication of source/drain extensions for P-type and N-type MOS devices.
  • the dopant material is activated by thermal processing of the semiconductor wafer at a selected temperature for a selected time to form the ultrashallow junction.
  • Thermal processing typically includes annealing the semiconductor wafer at a temperature in a range of about 900°C to 1050°C for about 0.1 to 10 seconds, but is not limited to these ranges. It will be understood that any suitable thermal processing parameters may be utilized within the scope of the invention.
  • FIG. 2B A second example of the nitrogen process of the present invention is illustrated in the flow chart of Fig. 2B.
  • the process of Fig. 2B is the same as the process of Fig. 2 A, except that nitrogen implant step 52 and dopant material implant step 54 have been reversed in the sequence of process steps.
  • nitrogen is implanted after implantation of the dopant material in the process of Fig. 2B.
  • boron dopant profiles of Fig. 3 The dopant profiles shown in Fig. 3 were obtained by secondary ion mass spectroscopy (SIMS).
  • SIMS secondary ion mass spectroscopy
  • boron concentration in atoms per cubic centimeter is plotted as a function of depth from the wafer surface in angstroms.
  • silicon wafers were implanted with boron at an energy of 500 eV and a dose of lE15/cm 2 .
  • the j unction depth X j is defined in this case as the depth from the wafer surface at which the boron concentration drops below 4 E18/cm 2 .
  • Fig. 3 The dopant profiles shown in Fig. 3 were obtained by secondary ion mass spectroscopy (SIMS).
  • Fig. 3 boron concentration in atoms per cubic centimeter is plotted as a function of depth from the wafer surface in angstroms.
  • silicon wafers were implanted with boro
  • curve 70 represents a crystalline silicon wafer which was implanted with boron as described above and annealed for 10 seconds at a temperature of 1050°C
  • curve 72 represents a crystalline silicon wafer which was implanted with boron as described above and spike annealed for a time of 0 to 1 second at a temperature of 1050°C
  • curve 74 represents an indium preamorphized silicon wafer which was implanted with boron as described above and spike annealed for a time of 0 to 1 second at a temperature of 1050°C. Nitrogen was not implanted in the wafers represented by curves 70, 72 and 74.
  • Curve 76 represents a crystalline silicon wafer wherein nitrogen was implanted prior to boron implantation.
  • N 2 nitrogen ions were implanted at an energy of 1.3 keV and a dose of lE15/cm 2 .
  • the wafer represented by curve 76 was spike annealed for a time of 0 to 1 second at a temperature of 1050°C, where the anneal time was established from the temperature profiles of the rapid thermal processing system.
  • the nitrogen implanted wafer represented by curve 76 has a reduced junction depth in comparison with the other processes illustrated.
  • the junction depth obtained with the nitrogen process, as represented by curve 76 is 246 angstroms as compared with 402 angstroms without a nitrogen implant for the same anneal conditions, as represented by curve 72.
  • the energy and dose of the nitrogen implant are selected depending on the energy and dose of the boron or other dopant material.
  • nitrogen implant conditions have been developed for several boron implant energies.
  • the nitrogen implant energies are selected so that the implanted depths of the nitrogen and boron into silicon are similar.
  • implant energies of N 2 + nitrogen ions at or below about 5 keV are used for implant energies of B + ions at or below about 1 keV.
  • N + nitrogen ions can be implanted, with a reduction in implant energy by one half to obtain the same implant depth.
  • BF 2 + ions can be implanted, with an increase in implant energy to obtain the same boron implant depth.
  • boron dopant profiles of Fig. 4 boron concentration in atoms per cubic centimeter is plotted as a function of depth from the wafer surface in angstroms.
  • silicon wafers were implanted with boron at an energy of 500 eV and a dose of lE15/cm 2 .
  • the dopant profiles were obtained by SIMS.
  • Curve 80 represents a wafer implanted with N 2 + nitrogen ions at an energy of 1.3 keV.
  • Curve 82 represents a wafer implanted with N 2 + nitrogen ions at an energy of 15 keV. In each case, the nitrogen dose was 1E15/cm .
  • the wafers were spike annealed at a time of 0 to 1 second and a temperature of 1050°C.
  • Curve 82 represents a significantly deeper junction depth and segregation of dopants, as indicated by the fact that the dopant profile has more than one peak.
  • Transmission electron microscope (TEM) analysis of the wafers showed that at higher nitrogen implant energies, a substantial number of extended defects is formed. In contrast, at the lower nitrogen implant energies, the wafers are substantially free of extended defects. The presence of the extended defects can produce adverse electrical effects in the devices being fabricated on the wafer.
  • TEM Transmission electron microscope
  • nitrogen implant energies for effective shallow junction formation have been established.
  • B boron ions and N 2 + nitrogen ions are implanted.
  • the nitrogen implant energy is at or below 1.3 keV; for 250 eV boron implants, the nitrogen implant energy is at or below 0.6 keV; and for 1 keV boron implants, the nitrogen implant energy is at or below 2.6 keV.
  • Higher nitrogen implant energies may be used when deeper junctions are required.
  • boron implant profiles In addition to energy, nitrogen dose must be selected.
  • the effect of nitrogen dose on boron implant profiles is illustrated in Fig. 5. Boron concentration in atoms per cubic centimeter is plotted as a function of depth in angstroms from the wafer surface for different nitrogen implant doses.
  • the dopant profiles were obtained by SIMS. In each case, a semiconductor wafer was implanted with boron at an energy of 500 eV and a dose of 1E15/cm 2 and with N 2 + nitrogen ions at an energy of 1.3 keV.
  • Curve 90 represents the boron profile with no nitrogen implanted; curve 92 represents the boron profile with a nitrogen dose of 5E13/cm 2 (curves 90 and 92 are essentially superimposed in Fig.
  • curve 94 represents the boron profile with a nitrogen dose of 2.5E14/cm 2
  • curve 96 represents the boron profile with a nitrogen dose of lE15/cm .
  • the wafers were spike annealed for a time of 0 to 1 second and a temperature of 1050°C.
  • a reduction in junction depth is observed at a nitrogen implant dose of about 2.5E14/cm 2 .
  • nitrogen implant doses at about this level or greater are preferred. In general, it is desirable to reduce the nitrogen implant dose to the level needed to obtain the desired junction depth, so as to minimize the adverse impact of the nitrogen implant on throughput.
  • Variations of the nitrogen implant process have been examined. These variations include (1) introduction of an anneal step between nitrogen and boron implants, and (2) multiple nitrogen implants before and after the boron implant.

Abstract

L'invention concerne un procédé destiné à la formation d'une jonction peu profonde dans une plaquette semi-conductrice. Ce procédé consiste à implanter une matière dopante, tel que du bore, dans la plaquette semi-conductrice à une énergie inférieure à 10 keV, puis à activer la matière dopante par traitement thermique de la plaquette semi-conductrice à une température sélectionnée pendant un laps de temps sélectionné afin de former la jonction peu profonde. L'énergie de l'azote est sélectionnée de façon que la profondeur de l'implantation de l'azote soit approximativement inférieure ou égale à la profondeur d'implantation de la matière dopante. La dose d'azote est de préférence supérieure à environ 2,5E14/cm2. L'étape d'implantation d'azote peut être effectuée avant ou après l'étape d'implantation de la matière dopante.
PCT/US2001/012377 2000-04-17 2001-04-16 Procedes destines a la formation de jonctions tres peu profondes dans des plaquettes semi-conductrices par implantation d'azote WO2001080295A1 (fr)

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US55057600A 2000-04-17 2000-04-17
US09/550,576 2000-04-17

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7846822B2 (en) 2004-07-30 2010-12-07 The Board Of Trustees Of The University Of Illinois Methods for controlling dopant concentration and activation in semiconductor structures
US7968440B2 (en) 2008-03-19 2011-06-28 The Board Of Trustees Of The University Of Illinois Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering
US8871670B2 (en) 2011-01-05 2014-10-28 The Board Of Trustees Of The University Of Illinois Defect engineering in metal oxides via surfaces

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2762138A1 (fr) * 1997-04-11 1998-10-16 Sgs Thomson Microelectronics Transistor mos a fort gradient de dopage sous sa grille
EP0887842A1 (fr) * 1997-06-25 1998-12-30 Lucent Technologies Inc. Dispositif à effet de champ comportant un isolant de porte amélioré et son procédé de fabrication
US5937301A (en) * 1997-08-19 1999-08-10 Advanced Micro Devices Method of making a semiconductor device having sidewall spacers with improved profiles
US5972783A (en) * 1996-02-07 1999-10-26 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor device having a nitrogen diffusion layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972783A (en) * 1996-02-07 1999-10-26 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor device having a nitrogen diffusion layer
FR2762138A1 (fr) * 1997-04-11 1998-10-16 Sgs Thomson Microelectronics Transistor mos a fort gradient de dopage sous sa grille
EP0887842A1 (fr) * 1997-06-25 1998-12-30 Lucent Technologies Inc. Dispositif à effet de champ comportant un isolant de porte amélioré et son procédé de fabrication
US5937301A (en) * 1997-08-19 1999-08-10 Advanced Micro Devices Method of making a semiconductor device having sidewall spacers with improved profiles

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7846822B2 (en) 2004-07-30 2010-12-07 The Board Of Trustees Of The University Of Illinois Methods for controlling dopant concentration and activation in semiconductor structures
US7968440B2 (en) 2008-03-19 2011-06-28 The Board Of Trustees Of The University Of Illinois Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering
US8871670B2 (en) 2011-01-05 2014-10-28 The Board Of Trustees Of The University Of Illinois Defect engineering in metal oxides via surfaces

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