WO2001078140A2

WO2001078140A2 - Chip carrier, relative manufacturing process, and electronic component incorporating such a carrier

Info

Publication number: WO2001078140A2
Application number: PCT/IT2001/000177
Authority: WO
Inventors: Giuseppe Pedretti; Carlo Arrigoni
Original assignee: Viasystems S.R.L.
Priority date: 2000-04-10
Filing date: 2001-04-09
Publication date: 2001-10-18
Also published as: ITTO20000334A1; WO2001078140A3; IT1320025B1; ITTO20000334A0

Abstract

A support (10) of the printed circuit type, also called 'chip carrier', for use in the making of electronic components (50), which comprises a sheet (13) of electrically insulating material, and which has, on one side (10a), a first plurality of cells or small areas (27), each of which is provided with solder pads or mounting areas (26) for receiving and electrically connecting to a corresponding integrated electronic circuit (41), and, on the other side (10b), a second plurality of cells provided with solder pads or mounting areas (26) for the coupling of the carrier (10) with a common electronic board (48); wherein a protective layer (28) is deposited on both sides (10a, 10b) of the carrier (10) in such a way as to leave uncovered the relative mounting areas (26), and wherein the carrier (10) also has, along the outlines of the cells (27), a plurality of etchings (33) which pass through the protective layer (28) to leave uncovered the layer (13) of insulating material underneath, and which correspond to removed portions (25a) of an original conducting grid (25), used during the manufacturing process of the carrier (10) itself to deposit a thin layer of solderable material (32) on the various pads or mounting areas (26). The carrier (10), thanks to the removal of these portions (25a) of the original conducting grid (25), acquires a structure which electrically insulates the various cells (27) from one another, so that the carrier (10) may be tested advantageously together with the integrated electronic circuits (41) mounted thereon, before the stage in which the carrier (10) is divided into electronic components (50), thereby avoiding the much more costly testing of the single electronic components (50), piece by piece.

Description

CHIP CARRIER, RELATIVE MANUFACTURING PROCESS, AND ELECTRONIC COMPONENT INCORPORATING SUCH A CARRIER

FIELD OF THE INVENTION This invention relates generally to printed circuit technology, and more specifically to a support or carrier, made using this technology, suitable for being coupled with a plurality of integrated electronic circuits for producing a plurality of electronic components compatible with the mounting on a common electronic board.

Correspondingly the invention also relates to a process for manufacturing a carrier such as that defined above, and to a generic electronic component obtainable using this support.

TECHNICAL BACKGROUND Carriers of this type for integrated electronic circuits, more often called "chip carriers", have been developed and are widespread in the field of electronic technology, because they allow to mount rapidly and at low cost on a normal electronic board, by means of standard assembly machines of consolidated use, integrated electronic circuits of particular complexity combined with a high degree of integration between the relative circuits, and typically having a large number of connection points or electrical connections with the electronic board.

In particular, as will become clear from the following description, each chip carrier constitutes a printed circuit having a plurality of tracks and mounting areas, which has on one side a first configuration of mounting points or areas optimized for connecting to terminals of a corresponding integrated electronic circuit, and on the other side a second configuration of mounting areas optimized for connecting to an ordinary electronic board. In this way, the carrier, when coupled with the corresponding integrated electronic circuit, forms an electronic component, which has the advantage, unlike the integrated electronic circuit by itself, of being able to be mounted easily and rapidly on the electronic board, with standard assembly techniques, while at the same time making, thanks to the interposition of the carrier, the electrical connection between the integrated electronic circuit and the electronic board.

In the current state of the art, chip carriers are generally produced according to the processes and technologies used in printed circuit manufacture.

Though these processes and technologies are widely known and used, it has been considered useful, for a more complete picture, to describe below the operations into which a process of known characteristics for manufacturing these chip carriers is divided, with reference to the flow diagram of Fig. 7. The process commences with the availability of a flat laminate, made particularly of an inner sheet produced from a glass fibre fabric impregnated with resin, and two thin layers of copper deposited on the opposing outer faces of the inner sheet of fabric.

This laminate, as is known to those acquainted with the sector art, constitutes a basic, readily available material, which is used universally in the making of printed circuits.

In a first step 101, suitable drilling machines produce a plurality of pass- through holes on a sheet or plate of this laminate, in accordance with a given configuration or mask corresponding to the specific design of chip carrier to be manufactured.

This configuration depends, in turn, on the structure of integrated electronic circuit intended to be coupled with the chip carrier, in order to form the corresponding electronic component.

Normally a sheet of this laminate is envisaged for supporting and therefore for being coupled with a plurality of completely identical integrated electronic circuits, so that the surface of the laminate is generally subdivided into a plurality of cells, adjacent to one another and each intended for accommodating an integrated electric circuit, and having the relative holes duplicated in the different cells. In a successive step 102, the drilled sheet of laminate is plunged into a chemical metallization bath containing copper, so as to metallize with a thin layer of copper the inner surface of the holes.

Then, in a step 103, the sheet of laminate is subjected to an electrochemical process, of known characteristics, having the function of growing the thickness of copper, both along the two outer faces of the laminate, and also along the inner surface of the holes, in function of the type of chip carrier to be manufactured and of the applications that the latter is intended for.

Later, in the step 104, the various holes are filled with an insulating resin, in order to protect the layer of copper deposited on the inner surface of the holes.

At this point, in the step 106, a film of photosensitive material, generally called "dry film", is applied on the two sides of the sheet of laminate, by way of suitable laminating machines, so as to cover the two sides of the laminate with this film.

Subsequently, in the step 107, the laminate is subjected along its two outer faces to a series of operations the purpose of which is to reproduce on the photosensitive layer the image of the tracks and of the conducting areas, and of the circuits in general, that are to be made on the laminate. In particular, firstly the film of photosensitive material is selectively exposed to light on the two faces of the laminate, using a suitable mask, so^' that it receives the light only in given areas which reproduce the shape of these circuits.

In this way only the areas exposed to light on the photosensitive film are subject to a chemical reaction which renders them resistant during the subsequent development stage.

The sheet of laminate is then developed, i.e. plunged into a chemical bath containing special substances which selectively remove from the laminate only those areas of the photosensitive film not exposed to light, in such a way as to protect the underlying layer of copper only in certain areas corresponding to the non-removed areas of the photosensitive film, and uncover the remaining area of the layer of copper. Then, in an etching step 108, the laminate is plunged into another chemical bath which etches the layer of copper on the two faces of the laminate, so as to remove the areas of this layer of copper not protected on top by the photosensitive film.

The remaining photosensitive film is subsequently removed from the two faces of the laminate.

Accordingly a sheet of laminate is produced that on its two faces has a plurality of tracks of pads and of copper, electrically connected through the layer of copper disposed along the holes, which constitute the desired circuits and electric connections. In particular, as anticipated above, on one of its two faces the laminate has a plurality of cells, each intended for accommodating a corresponding integrated electronic circuit, and on the other face a like plurality of cells, each one with a set of points configured for assembly on an electronic board.

In addition, the steps of exposure of the dry film, of development, of removal of the dry film, and of etching the layer of copper, are suitable for also producing, on each side of the sheet of laminate, as well as the circuits and pads already mentioned, a conducting grid, corresponding to the plurality of cells, and in particular made up of a plurality of square or generally rectangular shape meshes which each delimit a given cell. The two conducting grids made on opposite sides of the laminate are electrically connected to the circuits of each cell, in particular with the mounting areas or solder pads arranged along the two faces of the laminate, and have the role of permitting, via electrochemical means, a layer of solderable material to be deposited on these mounting areas, as will be better described in the following.

Once the step 108 is completed, the sheet of laminate is generally submitted, in the step 109, for an optical inspection, or AOI which stands for "Automatic Optical Inspection", to check if the tracks and areas of copper on the two faces of the laminate have been formed correctly and are without any defects.

Next the sheet of laminate is generally processed in order to produce a solder mask, the purpose of which is to protect the surfaces of the two faces of the laminate, with the exception of those areas destined to be soldered in the successive operations.

In particular, in the step 111, a layer of protective paint is spread on the two faces of the laminate, so as to cover their entire surface area.

Then, in the step 112, the protective paint layer is dried, and then selectively exposed to light, using a suitable mask, so as to be impressed and accordingly acquire a certain resistance only in given areas, corresponding to the parts of the circuits underneath, including the conducting grid, that are to be protected.

Following this, the paint layer is removed by way of known techniques in correspondence with the areas not exposed to light.

In this way, with the upper layer of paint only a part of the circuits formed on the laminate and naturally the conducting grid are protected, whereas on the two faces of the laminate, those parts of these circuits which constitute the areas or pads intended to be subsequently soldered or in some way connected to other elements are left uncovered or unprotected.

Thus the sheet of laminate is introduced in appropriate ovens where it is suitably baked, in such a way that the paint of the protective layer undergoes a. process of polymerisation such as to make it stable and resistant. At this point, in the step 113, also called gold-plating step, the laminate is processed in an electrochemical bath for the purpose of growing at the top the different nonprotected mounting areas disposed on the two sides of the laminate with a thin layer of solderable material. This layer has generally a composite structure and is made in two steps, namely by first depositing a lower layer of nickel on the mounting areas, and later depositing on the latter a layer of gold.

In particular, this step 113 exploits the possibility of maintaining, during the depositing of the solderable material, the mounting areas at the same potential, thanks to the two conducting grids which electrically connect and thus short-circuit, along the two sides of the laminate, the circuits of the various cells.

In this way, the mounting areas of the laminate acquire good solderability, such as to guarantee a correct and reliable soldering of the laminate in successive operations. Finally, the laminate is cut into a suitable format that is compatible with the future work on the laminate, and is also washed and submitted for testing to ascertain whether or not there are defects in the laminate.

In short, the known process described up to now, globally indicated with P1 and comprising from step 101 to step 113 inclusive, permits to manufacture a sheet of laminate, constituting a chip carrier, which in construction and structural terms is equivalent to a classical printed circuit.

In general, this process P1 is carried out entirely in companies which specialize in the production of these carriers, and which make them to supply them to other companies different from the former type, and typically to companies which manufacture electronic components, where the carriers are used for mounting and packing thereon a plurality of integrated circuits. The process employed by electronic component manufacturing companies for mounting integrated electronic circuits on the chip carrier in order to produce electronic components is also well known.

The latter process, which comes after the process P1 and which is designated P2 in short in Fig. 7, initially comprises a step 116 in which, in highly automated equipment, the integrated electronic circuits are arranged upon the corresponding cells of the chip carrier, and then connected electrically to the corresponding pads or mounting areas present on these cells.

In particular, in this step 116, appropriate machines create, for each integrated electronic circuit, a plurality of electric connections, obtained for example from very thin wires, between the terminals of the integrated electronic circuit and the corresponding mounting areas on the cell.

These connection techniques are known universally, and more often than not are called "bonding". Later, during a step 117, a layer of filler insulating material is poured over the carrier so as to englobe and affix stably on the latter both the integrated electronic circuits and the relative electric connections.

Accordingly, in this way, a rigid board is obtained which stably integrates, in a single block, both the carrier and the plurality of integrated electronic circuits. Finally, using known techniques and during a step 118, this board is cut and divided into elementary units, so as to obtain a plurality of electronic components each corresponding to an integrated electronic circuit and to a cell of the original carrier.

In particular, in each electronic component, the side of the carrier opposite that which receives the integrated electronic circuit defines a mounting surface provided with suitable connecting points or zones to allow the electronic component to be assembled on an electronic board of the usual characteristics. Therefore each electronic component thus obtained can easily be mounted on electronic boards and/or printed circuits having soldering densities and pitches conforming to the standard usually adopted, and using widely known and tested techniques and machines. For example, according to one of these techniques, in a first step micro-pellets of solderable material are deposited on the connection points present on the mounting surface of the electronic component; then the electronic component itself is placed on the electronic board, where its is subjected to a wave of heat that causes these pellets to melt and the electronic component to be soldered on to the board. The known process, described in detail above, however has the drawback of including a fairly expensive testing step of the electronic components which are obtained from the coupling of the chip carrier produced using this method with the integrated electronic circuits.

In fact the electronic components, after they have been divided or, to use the sector jargon word, "singularised", must be inspected one by one, during a step 119, with an obvious outlay of time and at costs that cannot be neglected.

Added to this is the fact that all trace of the conducting grid must be removed totally from the edges of each electric component obtained by cutting the carrier, in order to permit correct testing of the electronic components. The presence of this grid could in fact disturb the correct management of the signals in each component, and as a result prevent the electrical testing of the relative circuits.

SUMMARY OF THE INVENTION The object of this invention is therefore to produce a chip carrier for a plurality of integrated electronic circuits, which can overcome the drawbacks of the known art, and in particular which permits to avoid the costly inspection, piece by piece, of the electronic components that are obtained by the successive coupling of the carrier with the integrated electronic circuits.

This object is achieved by the carrier for integrated electronic circuits, produced using the typical printed circuit technology, having the characteristics defined in the main claim.

As will be better understood in the following, the carrier according to this invention has the important advantage that it can be tested by the carrier manufacturer to check whether or not there are short circuits or defects in general in the cells intended for accommodating the integrated electronic circuits. In this way, therefore, the manufacturer can guarantee better quality for the carrier and even demonstrate superior characteristics with respect to traditional carriers.

BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, characteristics and advantages of the invention will become apparent from the following description of a preferred embodiment, provided by way of non-restricting example, with reference to the accompanying diagrams in which:

Fig. 1 is a perspective view of a carrier for a plurality of integrated electronic circuits according to this invention; Fig. 2 is a detailed view of a portion of the carrier of Fig. 1 ;

Fig. 3 is a flow diagram relative to a process, according to this invention, for manufacturing the carrier of Fig. 1 using the printed circuit technology;

Fig. 4 (sect, a-i) is a sectional view showing how the structure of the carrier of Fig. 1 changes gradually, during the different stages of its manufacturing process; Fig. 5 is a partial sectional view of an electronic component obtainable using the carrier of Fig. 1 ; Fig. 6 (sect, a-f) is a view representing in sequence the stages by means of which the electronic component of Fig. 5 may be obtained starting from the carrier of Fig. 1 ; and

Fig. 7 is a flow diagram relative to a process used in the current art for manufacturing a carrier of known characteristics, for a plurality of integrated electronic circuits.

PREFERRED MODE FOR CARRYING OUT THE INVENTION With reference to Fig. 1 , a chip carrier made in accordance with this invention, is generically indicated with the numeral 10. As better described below, the carrier 10 is typically used in the electronics industry where it is coupled with a plurality of integrated electronic circuits for the purpose of producing a plurality of corresponding electronic components having a structure compatible with the mounting on a common electronic board.

The final structure of the carrier 10, represented in Fig. 1 and in greater detail in Fig. 2, will become clear from the following description of its manufacturing process, taken with reference to Figs. 3 and 4, and which show respectively the sequence of steps comprising this process, and the progressive and corresponding structural modifications that occur and are part of this process to progressively form the carrier 10. The first steps of this process are known and correspond to steps widely known and applied throughout the printed circuit industry.

In particular, the process starts with the availability of a laminate 11, represented in Fig. 4 (sect, a) and readily available in commerce, which consists of a sheet or inner layer 13 made of a fabric of glass fibre threads impregnated with resin, and two thin outer layers of copper, respectively an upper layer 14a and a lower layer

14b, arranged on the two opposite faces or sides of the laminate 11. The two opposite faces of the laminate 11 , also corresponding to the faces of the carrier 10 which will be made by means of this process, are indicated with numerals 10a and 10b.

In particular, the face 10a corresponds to the face of the carrier 10 intended for receiving integrated electronic circuits, while the face 10b corresponds to the face of the carrier 10 intended for coupling in contact with an ordinary electronic board, as described below.

In a step 51 represented in Fig. 4 (sect, b), the laminate 11 is drilled in accordance with a mask having a determined configuration, so as to produce along its surface a plurality of holes 16.

Typically the holes 16 are divided into groups of like geometry which are arranged one beside the other and are repeated in modules along the laminate 11 , in such a way as to arrange a unique laminate 11 for the successive coupling with a plurality of identical integrated electronic circuits, as will be better described below. Then the laminate 11 is plunged into a chemical bath containing copper in order to metallize the inner surface of the holes 16.

The thin layer of copper deposited in this metallization operation is also called "chemical copper".

Next, in a step 52, the laminate 11 is subjected to a known type electrochemical process, which results in a growing of the thickness of the copper deposited on the laminate 11 , so as to form a consistent and sufficiently thick layer of copper 18 on the two faces 10a and 10b of the laminate 11 and along the inner surface of the holes 16.

The copper deposited in this step and which defines the layer 18 is also called the "copper panel".

Then the holes 16 are plugged with resin 12, and following this, the next step 53 is that of a first laying by lamination, on the two faces of the laminate 11, of a photosensitive film 21, also called "dry film", represented with the dot and dash line in Fig. 4 (sect, c), to cover the entire layer of copper 18 disposed along the two faces 10a, 10b of the laminate 11.

Next the layer of photosensitive film 21 is selectively exposed to light, on the two sides of the laminate 11 , through an illuminating mask having a given shape which corresponds to that of the tracks and of the mounting pads to be made on the two sides 10a and 10b of the laminate 11.

This mask is also suitably shaped to define a conducting grid, for each of the sides 10a and 10b of the laminate 11. Then the layer of photosensitive film 21 is developed by way of a known process in such a way as to acquire a certain resistance to the successive operations only in correspondence with the zones exposed to light.

Finally, again using known techniques, the zones of photosensitive film 21 not exposed to light, and therefore not resistant, are removed from the two sides 10a and 10b of the laminate 11.

In this way, the image of the tracks, of the pads and of the two conducting grids, which have to be produced on the two sides of the laminate 11 , is reproduced on the layer 21 of photosensitive film.

The structure obtained up to this point of the process is represented with a continuous line in Fig. 4 (sect. c).

Subsequently, in a step 54, the layer of copper 18 is etched in correspondence with the areas that are uncovered, i.e. not protected by the overlying layer of photosensitive film 21 , so as to obtain the desired configuration of tracks and pads on the two sides 10a and 10b of the laminate 11. In particular, the pads made in this step are indicated with 26, and extend generally though not necessarily, in a zone adjacent to the holes 16, now plugged. The etching step 54 also permits to obtain on the sides 10a and 10b two respective conducting grids, both indicated with the numeral 25 and each made up of a plurality of generically rectangular meshes.

To sum up, the steps described up to now are such as to produce on each side 10a and 10b of the laminate 11, a plurality of groups of tracks and pads 26, associated with the groups of holes 16 and of similar geometry, which are duplicated many times and are delimited by the meshes of the corresponding conducting grid 25. In this way, the laminate 11 presents on the face 10a a first plurality of identical cells 27, delimited by the meshes of a first conducting grid 25, in which each of these cells 27 corresponds to a single integrated electronic circuit which will be mounted on the chip carrier 10.

Similarly the laminate 11 presents on the face 10b a second plurality of identical cell 27, which are delimited by the meshes of a second conducting grid 25 and are adapted for coupling with an electronic board. As will be clear, particularly with reference to the known process sketched in

Fig. 7, the operations described above and performed up to this point correspond to a known sequence.

According to an essential characteristic of this invention, at this point of the process a layer of protective paint is spread on the two faces 10a, 10b of the laminate 11, and then processed in order to produce a soldering mask so as to leave uncovered, not only the pads 26, or in general those zones of the circuits intended for subsequently receiving a thin layer of material that will make them easily solderable, but also predefined portions of each of the meshes constituting the two conducting grids 25. In particular, in a step 55, a protective paint 28 is applied on the two sides 10a and 10b of the laminate 11 , and then selectively exposed to light via a mask having a predefined shape. This mask is adapted to prevent the light from impressing the paint 28 on the two sides 10a and 10b, both local to the pads 26 of each cell 27, and also local to determined portions, indicated with 25a, of the sides of each mesh of the two conducting grids 25. Then, in a step 56, the protective paint 28 is first developed and then removed, as indicated by way of example with the dot and dash line in Fig. 4 (sect, e), in such a way as to leave uncovered the pads 26, and the portions 25a of the meshes of the conducting grids 25.

The next step 57 is that of application by lamination of a second photosensitive film 31 both on the side 10a of the laminate 11 intended for receiving the integrated electronic circuits, and on the side 10b intended for coupling with the electronic board.

Then in a step 58, this photosensitive film 31 is exposed to light, developed, and removed with the known techniques, already cited above, in such a way as to cover and thus protect only those predefined portions 25a, previously uncovered, of the meshes of the two conducting grids 25 formed on the sides 10a and 10b.

Fig. 4 (sect, f) shows the existing structure at this point of the process with the layer of photosensitive film reduced to covering solely the portions 25a of the two conducting grids 25.

In particular, the portions 25a of the two conducting grids 25, which are accordingly protected by the upper layer of photosensitive film 31, are made from central stretches, of limited length, of the four sides of each elementary mesh of the conducting grids 25.

Correspondingly the remaining parts of the two conducting grids 25 which are still protected by the paint 28 have an extension limited to the zone of the nodes of the grids 25.

Following this, in a step 59 generally called gold-plating and depicted in Fig. 4 (sect, g), the laminate 11 undergoes an electrolytic type process in which a thin layer 32 of solderable material is deposited on the uncovered pads 26 present in each cell 27.

As in the known technique, this layer 32 is typically made in two parts, i.e. by depositing on the pads 26 a first thin thickness of nickel, and subsequently depositing a second thin thickness of gold on top of the nickel.

In particular, this step of electrolytic depositing is made possible by the presence, on each side 10a and 10b, of the respective conducting grid 25 which, by electrically connecting among themselves the pads 26 of the different cells 27, permits the solderable material 32 to be deposited uniformly thereon. For this purpose, the meshes of the two conducting grids 25 are provided with connection points, even if not visible on the drawings, which electrically connect the meshes with the pads 26 of each cell 27, in such a way as to short-circuit all the pads 26 of all the cells 27.

Then, in a step 61 shown in Fig.4 (sect, h), the residual layer of photosensitive film 31 deposited on the portions 25a of the conducting grid 25 is removed, for example by means of a chemical bath, in order to uncover these portions 25a.

Next, in a selective etching step 62, these portions 25a are totally removed using known techniques, for instance by plunging the laminate 11 in a suitable chemical bath which chemically corrodes only the portions 25a, and leaves intact the remaining surface of the laminate 11.

In this way, at the end of the step 62, a product is obtained, the structure of which is shown in section in Fig. 4 (sect, i), which constitutes the chip carrier 10, according to this invention, for integrated electronic circuits, and which presents on its surface, local to the portions 25a removed from the original conducting grid, a plurality of etchings 33 that leave the inner layer 13 of glass fabric uncovered.

Furthermore each original conducting grid 25 is reduced to a plurality of cross formations, indicated with the numeral 34 and shown in Fig. 2, which are protected by the layer of paint 28 and are disposed in correspondence with the nodes of the original conducting grid 25.

The carrier 10 now presents on its two sides 10a and 10b a plurality of zones, defined by the cells 27 and each including a plurality of tracks and pads 26 for a corresponding integrated electronic circuit, which are electrically insulated from each other, thanks to the electric insulation made by the removal of the portions 25a between one mesh and the next of the original conducting grids 25.

For clarity's sake, in Fig. 3, the process just described comprising the steps from 51 to 62 to produce the carrier 10 is globally indicated with P3. Similarly to the known process P1 , the process P3 of the invention also reveals itself to be suitable to be employed typically and integrally in industries which specialize in the production of printed circuits, and which supply their products, for example as semi-finished goods, to other companies, which in turn specialize in sectors other than that of printed circuits. In this case, the carrier 10 manufactured in the way described above is adapted to be supplied to industries specializing in the manufacture of electronic components, where the carrier 10, during a series of operations globally indicated P3 in Fig. 3 and represented schematically in Fig. 6, is coupled with a plurality of integrated electronic circuits 41 to produce a plurality of electronic components. In particular, in a step 63 depicted schematically in Fig. 6 (sect, a), the integrated electronic circuits 41 are disposed and oriented according to a predefined pattern on the various cells 27 defined on the face 10a of the carrier 10, as indicated by the arrows 40, so that the terminations of each integrated electronic circuit 41 and the contact pads 26 of the corresponding cell 27 match perfectly with one another. In addition, still in the step 63 and as represented in Fig. 6 (sect, b), the terminations of each integrated electronic circuit 41 are connected electrically, through known techniques, with the pads 26 of the respective cell 27. This known connection technology, also generically called "wire bonding", typically comprises the application, in correspondence with each cell 27 of the chip carrier 10, of extremely thin connecting wires 42 which are soldered at one end to the pads 26 and at the other to the terminations of the integrated circuit 41. In particular, during this step the soldering to the pads 26 is aided by the presence of the solderable layer 32.

In this way, each integrated circuit 41 is electrically connected to the circuits of each corresponding cell 27. Then, in a step 64 shown in Fig. 6 (sect, c), a solidifiable filler material 43 is poured on to each integrated circuit 41 so as to englobe it together with the relative connecting wires 42, and integrate it stably with the carrier 10.

In this way the filler material 43 also forms a solid cover suitable for protecting each integrated circuit 41 with respect to the outside.

This step 64 is often called "packaging" step. At the end of this step, a composite board 45 is therefore obtained, structured as a single block.

Subsequently, as sketched in Fig. 6 (sect, d), the ηπonobloc board 45 is subjected to an inspection step 66 the purpose of which is to check if the circuits of the board 45 are capable of working according to the required specifications, and have been made correctly.

The step 66 is conducted on an ordinary test machine, by sending to the board 45 suitable input signals, which simulate operating conditions, to generate corresponding output signals which are processed by the test machine in order to check whether or not the board is conforming to the required specifications. In particular, these input and output signals are sent to and received from the board 45 through a plurality of prods 46 which are brought into contact with the pads or the contact points 26 disposed on one side 45a of the board, corresponding to the side 10b of the carrier 10.

The board 45 has the significant advantage of allowing to test from the functional aspect the various portions of the board 45, which correspond to the various integrated circuits 41 , totally independently from one another.

In other words, it is possible to test, as a single unit, the set of tracks, circuits, connections, pads formed by the combination of each cell 27 of the carrier 10 with a corresponding integrated electronic circuit 41, without the need, when performing this test, as is the case on the other hand in the known art, to cut or "singularise" the board 45 into a plurality of portions corresponding to the integrated circuits.

The board 45 in fact, thanks to having a structure without any conducting grid or other means capable of electrically connecting the circuits made in the different elementary portions of the board 45, allows the signals that are sent during the test to each of the portions to circulate only inside the latter, without any possibility of being transmitted to or of being disturbed by the other portions.

This possibility represents an undoubted economic advantage because it means that the test costs can be minimised, while maintaining or possibly even improving the effectiveness of the test itself.

In other words, the test machine can test each cell, one by one, in combination with the corresponding integrated electronic circuit, without the possibility of the transmitted signals being propagated to the adjacent cells and therefore disturbing and/or altering the result of the test.

Finally, in a step 67, the monobloc board 45 is cut or rather, to use again the jargon word, "singularised", along the outlines of the various cells 27 of the carrier 10 incorporated in the board 45, for example by way of a cutting machine sketched in

Fig. 6 (sect, e) and indicated with the numeral 47, in order to obtain a plurality of blocks each constituting an electronic component 50, like the one shown in detail in Fig. 5.

The electronic components 50 thus obtained are finally mounted, during a step 68 and by way of known fixtures and processes, on a common electronic board 48, having in particular unified distances between the connecting points or zones disposed on its surface 48a intended for receiving the components 50.

Fig. 6 (sect, f) schematically illustrates this mounting operation, in which the component 50 is moved in the direction of the arrow 49 to be stably mounted, generally by means of a soldering process, on the surface 48a of the electronic board 48.

In particular, the soldering is facilitated and rendered more reliable by the presence of the thin layer 32 of solderable material on the pads 26, disposed on the side 10b of the carrier 10 incorporated in the component 50, which are intended for coupling with corresponding pads disposed on the surface 48a of the electronic board 48.

In short, without prejudice to the principle of this invention, the construction details and embodiments may be amply varied with respect to what has been described and illustrated, without departing from the scope of the invention.

Claims

1. Carrier (10) for a plurality of integrated electronic circuits (41 ), comprising: a sheet (13) of electrically insulating material; a plurality of cells (27) defined on at least one side (10a, 10b) of said carrier (10), each of said cells (27) being provided with a plurality of mounting areas or pads (26) associated with a layer of solderable material (32) to allow said carrier (10) receive and electrically connect to a corresponding integrated electronic circuit (41); and a protective layer (28) deposited on said side (10a, 10b) in order to protect said cells (27) while leaving said mounting areas (26) uncovered, characterized in that said carrier (10) has, along the outlines of said cells (27), a plurality of etchings (33), which pass through said protective layer (28) so as to uncover the underlying sheet of insulating material (13), wherein said etchings (33) correspond to removed portions of an original conducting grid (25) which was used, during the manufacturing process of said carrier (10), for depositing said solderable material (32) on said mounting areas (26).

2. Carrier (10) for a plurality of integrated electronic circuits (41 ), comprising: a sheet (13) of electrically insulating material; a plurality of cells (27) defined on at least one side (10a, 10b) of said carrier (10), each of said cells (27) being provided with a plurality of mounting areas (26) associated with a layer of solderable material (32) to allow said carrier

(10) to receive and connect electrically to a corresponding integrated electronic circuit (41); and a protective layer deposited on said side (10a, 10b) in order to protect said cells (27) leaving said mounting areas (26) uncovered, characterized in that said carrier (10) has, along the outlines of said cells (27), a plurality of etchings (33), which pass through said protective layer (28) so as to uncover the underlying sheet of insulating material (13), wherein said etchings (33) are suitable for interrupting the electric continuity of a conducting grid (25), arranged underneath said protective layer (28), which was used for depositing said solderable material on said mounting areas (26) during the manufacturing process of said carrier (10).

3. Carrier (10) for a plurality of integrated electronic circuits, comprising: a sheet (13) of electrically insulated material; a plurality of cells (27) defined on one side (10a, 10b) of said plate, each of said cells (27) being provided with a plurality of tracks and mounting areas (26) associated with a layer of solderable material (32) for receiving and electrically connecting to a corresponding integrated electronic circuit (41); and a protective layer (28) composed of a first protective substance, said protective layer being deposited on said side (10a, 10b) in order to protect said cells (26) leaving said mounting areas (26) uncovered, characterized in that said carrier (10) has, along the outlines of said cells (27), a plurality of etchings (33), which pass through said protective layer (28) so as to leave uncovered the underlying sheet (13) of insulating material, and to electrically insulate said cells (27) from one other, wherein said etchings (33) and the electric insulation between said cells are obtained by way of a process that includes the following steps: making on said side (10a, 10b), with the typical printed circuit technology, a conducting grid (25) suitable for electrically connecting between one another the mounting areas (26) of said cells (27), said conducting grid (25) being made up of a plurality of elementary meshes each of which defines the outline of a corresponding cell (27); depositing on said side (10a, 10b) said protective layer (28) composed of said first protective substance; selectively removing said protective layer (28) in order to uncover the mounting areas (26) of each of said cells (27) and at least one determined portion (25a) of the corresponding elementary mesh of said conducting grid (25) ; depositing on said side (10a, 10b) a temporary protective layer made up of a second protective substance (31); selectively removing said temporary protective layer so as to protect with said second protective substance (31) only said determined portion (25a), previously uncovered, of each of the elementary meshes of said conducting grid _, (25); depositing via electrochemical means, using said conducting grid, a solderable substance (32) on the mounting areas (26) of each of said cells (27); completely removing said second protective substance (31) so as to uncover said determined portion (25a) of each of the elementary meshes of said conducting grid (25); and selectively removing said determined portion (25a) of each of the elementary meshes of said conducting grid (25), so as to form said etchings (33) along the outlines of said cells (27) and at the same time electrically insulate the tracks and mounting areas (26) proper to each of said cells from those of any other cell.

4. Carrier (10) for a plurality of integrated electronic circuits (41 ) according to one of the previous claims, wherein the original conducting grid (25) consists of a plurality of rectangular meshes which delimit said cells (27), characterized in that said etchings (33) extend along a central portion of the side of each rectangular mesh of the original conducting grid (25), so that the remaining part of the conducting grid, which is still in said carrier, has a plurality of cross-shaped zones (34) disposed in correspondence with the nodes of said original grid (25).

5. Carrier (10) for a plurality of integrated electronic circuits (41 ) according to one of the previous claims, characterized in that said layer of solderable material (32) consists of a lower layer of nickel and an upper layer of gold deposited on top of said layer of nickel.

6. Carrier (10) for a plurality of integrated electronic circuits (41 ) according to one of the previous claims, characterized in that said carrier has, on both sides, a plurality of etchings (33) which pass through a protective layer (28) disposed on these sides, so as to uncover the underlying sheet of insulating material (13), wherein the etchings (33) present on a first and on a second of said sides correspond to portions removed (25a) respectively from a first (25) and from a second conducting grid (25) which were used, during the manufacturing process of said carrier (10), for depositing solderable material on mounting areas (26) disposed on both the sides (10a, 10b) of said carrier (10).

7. Manufacturing process of a carrier (10) for a plurality of integrated electronic circuits (41 ), comprising the following succession of steps: making, with the typical printed circuit technology, a laminate that has, on at least one side (10a, 10b), a conducting grid (25) and a plurality of cells (27) defined by said conducting grid, each of said cells (27) being delimited by a corresponding elementary mesh of said conducting grid and being provided with a plurality of mounting areas (26) for receiving and electrically connecting to a corresponding integrated electronic circuit, the mounting areas of said cells being electrically connected between one another through said conducting grid (25); depositing on said side a first film or protective layer (28) consisting of a first protective substance; selectively removing said first protective layer (28) so as to uncover the mounting areas (26) of each of said cells and at least a portion (25a) of the corresponding elementary mesh of said conducting grid; depositing on said side (10a, 10b) a second film or protective layer consisting of a second protective substance (31); selectively removing said second protective layer in such a way as to protect with said second protective substance (31) the portions (25a), previously uncovered, of the elementary meshes of said conducting grid (25); depositing via electrochemical means, using said conducting grid (25), a solderable substance on the mounting areas (26) of each of said cells (27); removing said second protective substance (31) in such a way as to uncover the portions (25a), previously protected, of the elementary meshes of said conducting grid (25); and selectively removing the uncovered portions (25a) of the elementary meshes of said conducting grid, so as to electrically insulate the mounting areas (26) and the tracks proper to each of said cells (27) from those of any other cell.

8. Manufacturing process of a carrier (10) for a plurality of integrated electronic circuits (41) according to claim 7, characterized in that the step of selectively removing said first protective layer (28) comprises a first sub-step during which said first protective layer is illuminated through a suitable mask, and a successive second sub-step during which said carrier is plunged into a chemical bath to remove the areas of said first protective layer not exposed to light.

9. Manufacturing process of a carrier (10) for a plurality of integrated electronic circuits according to claim 7, characterized in that the step of selectively removing said second protective layer comprises a first sub-step during which said second protective layer is illuminated through a suitable mask solely in correspondence with the portions of said conducting grid intended to be removed, and a successive second sub-step during which said carrier is plunged into a chemical bath to remove the areas of said second protective layer not exposed to light.

10. Electronic component (50) characterized in that it is manufactured by using a chip carrier (10) in accordance with claim 1.

11. Electronic component according to claim 10, wherein the relative manufacturing process comprises the following steps: providing a chip carrier (10) in accordance with claim 1 , disposing a plurality of integrated electronic circuits (41) on said carrier (10) in correspondence with the cells (27) defined thereon, electrically connecting the terminals of said integrated electronic circuits to the corresponding mounting areas (26) present in said cells (27), depositing on said carrier (10) a filler material (43) capable of englobing both said integrated electronic circuits (41 ) and the relative electric connections and of integrating them stably with said carrier, and sub-dividing said carrier into blocks or elementary parts corresponding to said cells to constitute, with any one of these parts, said electronic component (50).

12. Electronic component (50) according to claim 11 , characterized in that the electrically connecting step comprises a step for applying and connecting a plurality of conductive wires (42) between the terminations of each integrated electronic circuit (41) and the mounting areas (26) of the corresponding cell (27).