WO2001067832A1 - Electrical circuit and substrate therefor - Google Patents

Electrical circuit and substrate therefor Download PDF

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Publication number
WO2001067832A1
WO2001067832A1 PCT/DE2001/000766 DE0100766W WO0167832A1 WO 2001067832 A1 WO2001067832 A1 WO 2001067832A1 DE 0100766 W DE0100766 W DE 0100766W WO 0167832 A1 WO0167832 A1 WO 0167832A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
component
electrical circuit
conductor track
Prior art date
Application number
PCT/DE2001/000766
Other languages
German (de)
French (fr)
Inventor
Albert-Andreas Hoebel
Frank Heider
Bernd Rautzenberg
Thomas Raica
Andreas Haugeneder
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to HU0300062A priority Critical patent/HUP0300062A2/en
Priority to DE50110448T priority patent/DE50110448D1/en
Priority to JP2001565716A priority patent/JP2003526220A/en
Priority to EP01915069A priority patent/EP1269805B1/en
Publication of WO2001067832A1 publication Critical patent/WO2001067832A1/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09381Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969Apertured conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098Special shape of the cross-section of conductors, e.g. very thick plated conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention is based on an electrical circuit on a substrate or on a substrate according to the preamble of the independent claims. It is known to fasten components, for example on a printed circuit board, by soldering. The components must be attached at certain locations to enable bonding and electrical testing, to avoid short circuits and to ensure a tight circuit package. To limit the area in which the solder can spread during assembly, it is known to apply solder resist to the substrate or the conductor track, or to attach limiting materials (so-called soldering templates) which rise above the surface of the substrate to the substrate before soldering.
  • the circuit according to the invention or the substrate according to the invention with the characterizing features of the independent claims have the advantage that a solder stop structure without additional process steps for the defined placement of components, that is to prevent "floating away” or to reduce the tilting of the component during assembly
  • the depressions can be realized together with the structuring of the conductor tracks in one step.
  • the depressions leave the properties of the substrate unaffected, in contrast to the use of a lost soldering template.
  • the depressions designed as holes or trenches also contribute to stabilizing the mechanical connection, for example between the metallic interconnect layer and the ceramic substrate, which are two materials with very different expansion coefficients.
  • FIG. 1b shows a circuit with a conductor track layer which has elongated depressions (trenches).
  • Figure 2 shows a cross-sectional side view.
  • FIG. 1 a shows a printed circuit board 10 with conductor track layers 20, 21, 22, 23, 24 and 25 arranged on the surface of the substrate.
  • Components 30 and 40 for example power modules, transistor chips or diode chips, are applied to the conductor track layers.
  • the underside of these components is in electrical contact with the respective conductor track layer via a solder connection.
  • the components are holes at their corners (English “Dimples") 50 and 51 surrounded in the respective conductor track layer.
  • FIG. 1b shows a printed circuit board 10 with a conductor track layer 26 analogous to Figure la.
  • the component 30 is on one side of two trenches 60 in the
  • the distance between the trenches and the component 30 corresponds approximately to the distance 52 illustrated in FIG. 1a.
  • the two trenches 60 are separated from one another by a connecting web 70.
  • the holes or the trenches are used in the solder assembly to define the position of components on the circuit board (more generally the substrate). If solder is applied to the layer on which a component is to be attached, the holes / trenches represent a barrier (poorly wettable area) for the solder, over which the component cannot swim. This is due to the restoring forces that occur for the solder and the “floating” component as soon as the component comes to the limit by “floating away” during assembly. This creates a defined
  • the edge of the trench should not be less than a certain distance, for example 200 micrometers, in order to use the boundary structure (holes or trenches) within the given assembly tolerance, which is given, among other things, by the placement machine used, which places the components on the circuit board Reflow process only partially filled with solder after remelting.
  • a certain distance for example 200 micrometers
  • the circuit board can be a DBC (Direct bonded copper) substrate or consist of other substrate materials, for example IMS (insulated metal substrates).
  • the holes 50, 51 can also be arranged along the side edges and not only at the corners, the effect of the position definition already being ensured by the corner hole structures and the filling of the
  • the trenches 60 can also be provided on all or at least several sides of the component, alternatively, connecting webs 70 can also be partially omitted.
  • the boundary between the metal layer under the component and the rest of the conductor layer is limited by the maximum current to be carried, which must flow over the areas between the holes or between the trenches.
  • FIG. 2 shows a cross-sectional side view of part of a DBC substrate 10 according to FIG. 1.
  • the back of the substrate is provided with a copper layer 80.
  • the conductor track layer 22 (FIG. 1 a) or 26 (FIG. 1 b) is shown on the front in the vicinity of a hole 50 or a trench 60. Hole 50
  • the conductor track layer consists of a first metal layer 220 made of copper, which is applied directly to the substrate; the backside metallization is made of the same metal.
  • the second layer 221 applied to the first metal layer is a layer of gold and nickel, the nickel partial layer being applied to the copper and the gold partial layer being applied to the nickel partial layer.
  • the rear side metallization has a layer thickness of typically 300 micrometers, for example the electrical insulation layer 10 consisting of ceramic has a thickness of 600 micrometers, the first metal layer 220 (copper layer) has a thickness of approximately 300 micrometers, the nickel partial layer has a thickness of approximately 20 to 70 micrometers and that Gold partial layer approximately 0.02 - 0.1 microns thick.
  • the holes 50, 51 or trenches 60 are structured together with the conductor track layers on the substrate.
  • the poorer wettability of the solder in the delimitation structure than on the conductor track layers stems from the fact that the bottom of the delimitation structure is made of non-wettable substrate material (for example ceramic). exists, so that the solder can still wet the wall of the boundary structure, but due to the intermediate floor does not completely fill the structure.
  • parts of the side walls of the holes or trenches can also consist of substrate or printed circuit board material. Then, however, the delimiting structure must be introduced by material removal in a separate operation, this material removal then at least partially also covering the substrate 10.
  • the delimiting structure must be introduced by material removal in a separate operation, this material removal then at least partially also covering the substrate 10.
  • Conductor walls of the boundary structure are still selectively oxidized, making them poorly wetted.
  • the diameter of the holes can also be selected to be smaller than 400 micrometers due to the increased barrier effect.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

The invention relates to an electrical circuit placed on a substrate (10) with at least one component (30; 40) which is fastened to a conductor track layer (20; 21; 22; 23; 24; 25) and which is surrounded by recesses (50; 51; 60) provided in the conductor track layer. The invention also relates to a substrate comprising at least one conductor track layer for fastening at least one electrical component, whereby the conductor track layer is provided with recesses that form a flow barrier for a joining material used for fastening the component. Said recesses surround an area for fastening the component and are interspaced in such a manner that the component has space between the recesses without the recesses having to be covered by the component.

Description

Elektrische Schaltung und Substrat hierzuElectrical circuit and substrate for this
Stand der TechnikState of the art
Die Erfindung geht aus von einer elektrischen Schaltung auf einem Substrat beziehungsweise von einem Substrat nach der Gattung der unabhängigen Ansprüche. Es ist bekannt, Bauelemente beispielsweise auf einer Leiterplatte per Lötmontage zu befestigen. Die Bauelemente müssen an bestimmten Orten befestigt sein, um ein Bonden sowie eine elektrische Prüfung zu ermöglichen und um Kurzschlüsse zu vermeiden und eine dichte Schaltungspackung zu gewährleisten. Zur Begrenzung des Bereichs, in dem sich das Lot bei der Montage ausbreiten kann, ist es bekannt, auf das Substrat beziehungsweise die Leiterbahn Lötstoplack aufzutragen oder sich über die Oberfläche des Substrats erhebende Begrenzungsmaterialien (sogenannte Lötschablonen) vor dem Löten auf dem Substrat zu befestigen.The invention is based on an electrical circuit on a substrate or on a substrate according to the preamble of the independent claims. It is known to fasten components, for example on a printed circuit board, by soldering. The components must be attached at certain locations to enable bonding and electrical testing, to avoid short circuits and to ensure a tight circuit package. To limit the area in which the solder can spread during assembly, it is known to apply solder resist to the substrate or the conductor track, or to attach limiting materials (so-called soldering templates) which rise above the surface of the substrate to the substrate before soldering.
Vorteile der ErfindungAdvantages of the invention
Die erfindungsgemäße Schaltung beziehungsweise das erfindungsgemäße Substrat mit den kennzeichnenden Merkmalen der unabhängigen Ansprüche haben demgegenüber den Vorteil, daß zur definierten Plazierung von Bauelementen, das heißt zum Unterbinden eines „Wegschwimmens" beziehungsweise zum Vermindern des Verkippens des Bauelements während der Montage, eine Lötstopstruktur ohne zusätzliche Prozeßschritte realisiert werden kann. Die Vertiefungen können zusammen mit der Strukturierung der Leiterbahnen in einem Schritt hergestellt werden. Darüber hinaus lassen die Vertiefungen die Eigenschaften des Substrats im Gegensatz zum Einsatz einer verlorenen Lötschablone unbeeinflußt. Die als Löcher oder Gräben ausgebildeten Vertiefungen tragen auch zu einer Stabilisierung der mechanischen Verbindung beispielsweise zwischen der metallischen Leiterbahnschicht und dem keramischen Substrat bei, welches zwei Materialien mit stark unterschiedlichen Ausdehnungskoeffizienten sind.The circuit according to the invention or the substrate according to the invention with the characterizing features of the independent claims have the advantage that a solder stop structure without additional process steps for the defined placement of components, that is to prevent "floating away" or to reduce the tilting of the component during assembly The depressions can be realized together with the structuring of the conductor tracks in one step. In addition, the depressions leave the properties of the substrate unaffected, in contrast to the use of a lost soldering template. The depressions designed as holes or trenches also contribute to stabilizing the mechanical connection, for example between the metallic interconnect layer and the ceramic substrate, which are two materials with very different expansion coefficients.
Durch die in den abhängigen Ansprüchen und in derBy the in the dependent claims and in the
Beschreibung aufgeführten Maßnahmen sind vorteilhafte Weiterbildungen und Verbesserungen der in den unabhängigen Ansprüchen angegebenen Vorrichtungen möglich.Description of the measures listed are advantageous developments and improvements of the devices specified in the independent claims.
Zeichnungdrawing
Ausführungsbeispiele der Erfindung sind in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Figur la zeigt eine Schaltung mit Leiterbahnschichten, die Löcher aufweisen. Figur lb zeigt eine Schaltung mit einer Leiterbahnschicht, die längliche Vertiefungen (Gräben) aufweist. Figur 2 zeigt eine Querschnittsseitenansicht .Embodiments of the invention are shown in the drawing and explained in more detail in the following description. Figure la shows a circuit with interconnect layers that have holes. FIG. 1b shows a circuit with a conductor track layer which has elongated depressions (trenches). Figure 2 shows a cross-sectional side view.
Beschreibung der AusführungsbeispieleDescription of the embodiments
Figur la zeigt eine Leiterplatte 10 mit auf der Oberfläche des Substrates angeordneten Leiterbahnschichten 20, 21, 22, 23, 24 und 25. Auf den Leiterbahnschichten sind Bauelemente 30 beziehungsweise 40 aufgebracht, zum Beispiel Leistungsbausteine, Transistorchips oder Diodenchips. Diese Bauelemente stehen mit ihrer Unterseite mit der jeweiligen Leiterbahnschicht über eine Lotverbindung in elektrischem Kontakt. Die Bauelemente sind an ihren Ecken von Löchern (engl. „Dimples") 50 beziehungsweise 51 in der jeweiligen Leiterbahnschicht umgeben. Das Bezugszeichen 51 markiert hierbei sogenannte randständige Löcher, das heisst Löcher, die keine vollständige kreisförmige Ausformung aufweisen, da der Abstand ihres Zentrums vom Rand der Leiterbahnschicht kleiner als ihr Radius ist. Der Abstand 52 des Randes eines Bauelements von den Lochrändern beträgt hier 200 Mikrometer. Figur lb zeigt eine Leiterplatte 10 mit einer Leiterbahnschicht 26 analog zur Figur la. Das Bauelement 30 ist auf einer Seite von zwei Gräben 60 in derFIG. 1 a shows a printed circuit board 10 with conductor track layers 20, 21, 22, 23, 24 and 25 arranged on the surface of the substrate. Components 30 and 40, for example power modules, transistor chips or diode chips, are applied to the conductor track layers. The underside of these components is in electrical contact with the respective conductor track layer via a solder connection. The components are holes at their corners (English "Dimples") 50 and 51 surrounded in the respective conductor track layer. The reference symbol 51 marks so-called marginal holes, that is to say holes that do not have a completely circular shape, since the distance of their center from the edge of the conductor track layer is smaller than its radius The distance 52 of the edge of a component from the edges of the holes is 200 micrometers here Figure 1b shows a printed circuit board 10 with a conductor track layer 26 analogous to Figure la. The component 30 is on one side of two trenches 60 in the
Leiterbahnschicht benachbart. Der Abstand der Gräben vom Bauelement 30 entspricht ungefähr dem in Figur la illustrierten Abstand 52. Die zwei Gräben 60 sind durch einen Verbindungssteg 70 voneinander getrennt.Conductor layer adjacent. The distance between the trenches and the component 30 corresponds approximately to the distance 52 illustrated in FIG. 1a. The two trenches 60 are separated from one another by a connecting web 70.
Die Löcher beziehungsweise die Gräben dienen bei der Lötmontage zur Positionsdefinition von Bauelementen auf der Leiterplatte (allgemeiner dem Substrat) . Wird Lot auf die Schicht aufgebracht, auf der ein Bauelement befestigt werden soll, so stellen die Löcher/Gräben eine Barriere (schlecht benetzbarer Bereich) für das Lot dar, über die das Bauelement nicht hinausschwimmen kann. Das liegt an den Rückstellkräften, die für das Lot und das darauf „schwimmende" Bauelement auftreten, sobald das Bauelement bei der Montage durch „Wegschwimmen" an die Begrenzung herankommt. Dadurch wird eine definierteThe holes or the trenches are used in the solder assembly to define the position of components on the circuit board (more generally the substrate). If solder is applied to the layer on which a component is to be attached, the holes / trenches represent a barrier (poorly wettable area) for the solder, over which the component cannot swim. This is due to the restoring forces that occur for the solder and the “floating” component as soon as the component comes to the limit by “floating away” during assembly. This creates a defined
Bauelementplazierung gewährleistet. Diese Rückstellkräfte haben ihren Ursprung in der niedrigeren Benetzungsfähigkeit der Leiterplatte am Loch- bzw. Grabenboden im Vergleich zur Leiterbahnschicht und der Oberflächenspannung des Lotes. Ein an die Begrenzungsstruktur „heranschwimmendes" Bauelement wird an seiner Unterseite weiterhin vom Lot benetzt, während das Lot auf der Leiterplatte die als Lotbarriere wirkende Loch- bzw. Grabenstruktur nicht überwinden kann. - Die Leiterbahnschichten zwischen den Löchern beziehungsweise Gräben leiten den elektrischen Strom zur Lotkontaktierung des Bauelements und dienen gleichzeitig zur Wärmeableitung vom Bauelement. Je nach erforderlicher Stromtragfähigkeit und Wärmeleitfähigkeit der Leiterbahnschicht können Gräben oder Löcher unterschiedlicher Länge beziehungsweise Zahl verwendet werden, um die Platzierung der Bauelemente zu unterstützen. Der Abstand vom Rand des Bauelements zum Lochbzw. Grabenrand sollte einen gewissen Mindestabstand, beispielsweise 200 Mikrometer, nicht unterschreiten, um im Rahmen der gegebenen Montagetoleranz, die unter anderem durch den verwendeten Bestückungsautomaten gegeben ist, der die Bauelemente auf die Leiterplatte aufsetzt, die Begrenzungsstruktur (Löcher bzw. Gräben) bei der Anwendung eines Reflow-Verfahrens nach dem Umschmelzen nur teilweise mit Lot zu füllen. Je größer der Abstand gewählt wird, umso schlechter ist die durch die Begrenzungsstruktur erzielte Positioniergenauigkeit .Component placement guaranteed. These restoring forces have their origin in the lower wettability of the circuit board on the perforated or trench bottom compared to the conductor track layer and the surface tension of the solder. A component "floating" towards the boundary structure is still wetted by the solder on its underside, while the solder on the circuit board cannot overcome the hole or trench structure acting as a solder barrier. The conductor track layers between the holes or Trenches conduct the electrical current to solder the component and at the same time serve to dissipate heat from the component. Depending on the required current carrying capacity and thermal conductivity of the conductor layer, trenches or holes of different lengths or numbers can be used to support the placement of the components. The distance from the edge of the component to the hole or. The edge of the trench should not be less than a certain distance, for example 200 micrometers, in order to use the boundary structure (holes or trenches) within the given assembly tolerance, which is given, among other things, by the placement machine used, which places the components on the circuit board Reflow process only partially filled with solder after remelting. The greater the distance selected, the worse the positioning accuracy achieved by the delimiting structure.
Alternativ kann die Leiterplatte ein DBC (Direct bonded copper) -Substrat sein oder aus anderen Substratmaterialien, beispielsweise IMS (insulated metal Substrate) bestehen. Die Löcher 50, 51 können auch entlang der Seitenränder und nicht nur an den Ecken angeordnet werden, wobei der Effekt der Positionsdefinition durch die eckständigen Lochstrukturen bereits gewährleistet ist und die Ausfüllung derAlternatively, the circuit board can be a DBC (Direct bonded copper) substrate or consist of other substrate materials, for example IMS (insulated metal substrates). The holes 50, 51 can also be arranged along the side edges and not only at the corners, the effect of the position definition already being ensured by the corner hole structures and the filling of the
Seitenbereiche mit Löchern lediglich einer Erhöhung der Rückstellkraft dient. Die Gräben 60 können ebenso auf allen oder zumindest mehreren Seiten des Bauelements vorgesehen sein, alternativ können Verbindungsstege 70 auch teilweise entfallen. Begrenzt ist die Abgrenzung der unter dem Bauelement liegenden Metallschicht vom Rest der Leiterbahnschicht durch den maximal zu tragenden Strom, der über die Bereiche zwischen den Löchern beziehungsweise zwischen den Gräben fließen muß. Es sind auch umgekehrt mehrere Verbindungsstege 70 pro Seite des Bauelements wählbar, so daß letztlich Übergangsformen bis hin zu einer Anreihung von Löchern 50,51 auf jeder Seite realisierbar sind.Side areas with holes only serve to increase the restoring force. The trenches 60 can also be provided on all or at least several sides of the component, alternatively, connecting webs 70 can also be partially omitted. The boundary between the metal layer under the component and the rest of the conductor layer is limited by the maximum current to be carried, which must flow over the areas between the holes or between the trenches. Conversely, there are also a plurality of connecting webs 70 on each side of the component selectable, so that ultimately transitional forms up to a row of holes 50, 51 can be realized on each side.
Figur 2 stellt eine Querschnittsseitenansicht eines Teils eines DBC-Substrates 10 gemäß Figur 1 dar. Die Rückseite des Substrates ist mit einer Kupferschicht 80 versehen. Auf der Vorderseite ist die Leiterbahnschicht 22 (Figur la) beziehungsweise 26 (Figur lb) in der Umgebung eines Lochs 50 beziehungsweise eines Grabens 60 abgebildet. Das Loch 50FIG. 2 shows a cross-sectional side view of part of a DBC substrate 10 according to FIG. 1. The back of the substrate is provided with a copper layer 80. The conductor track layer 22 (FIG. 1 a) or 26 (FIG. 1 b) is shown on the front in the vicinity of a hole 50 or a trench 60. Hole 50
(der Graben 60) hat einen Durchmesser 500 (eine Ausdehnung senkrecht zum Rand des Bauelements) größer als 400 Mikrometer, vorzugsweise 800 Mikrometer (bedingt durch den Ätzprozeß) . Die Leiterbahnschicht besteht aus einer ersten Metallschicht 220 aus Kupfer, die direkt auf das Substrat aufgebracht ist; die Rückseitenmetallisierung ist aus dem gleichen Metall hergestellt. Die zweite auf der ersten Metallschicht aufgebrachte Schicht 221 ist eine Schichtung aus Gold und Nickel, wobei die Nickelteilschicht auf dem Kupfer und die Goldteilschicht auf der Nickelteilschicht aufgebracht ist. Die Rückseitenmetallisierung hat eine Schichtdicke von typischerweise 300 Mikrometern, die beispielsweise aus Keramik bestehende elektrische Isolationsschicht 10 eine Dicke von 600 Mikrometern, die erste Metallschicht 220 (Kupferschicht) eine Dicke von zirka 300 Mikrometern, die Nickelteilschicht eine Dicke von zirka 20 bis 70 Mikrometern und die Goldteilschicht eine Dicke von zirka 0,02 - 0,1 Mikrometern.(the trench 60) has a diameter 500 (an extension perpendicular to the edge of the component) greater than 400 micrometers, preferably 800 micrometers (due to the etching process). The conductor track layer consists of a first metal layer 220 made of copper, which is applied directly to the substrate; the backside metallization is made of the same metal. The second layer 221 applied to the first metal layer is a layer of gold and nickel, the nickel partial layer being applied to the copper and the gold partial layer being applied to the nickel partial layer. The rear side metallization has a layer thickness of typically 300 micrometers, for example the electrical insulation layer 10 consisting of ceramic has a thickness of 600 micrometers, the first metal layer 220 (copper layer) has a thickness of approximately 300 micrometers, the nickel partial layer has a thickness of approximately 20 to 70 micrometers and that Gold partial layer approximately 0.02 - 0.1 microns thick.
Die Löcher 50, 51 beziehungsweise Gräben 60 werden zusammen mit den Leiterbahnschichten auf dem Susbtrat strukturiert. Die schlechtere Benetzungsfähigkeit des Lots in der Begrenzungsstruktur als auf den Leiterbahnschichten rührt daher, daß der Boden der Begrenzungsstruktur aus nicht benetzbarem Substratmaterial (beispielsweise Keramik) besteht, so daß das Lot zwar die Wandung der Begrenzungsstruktur noch benetzen kann, aber aufgrund des dazwischenliegenden Bodens nicht die Struktur vollends füllt. In einer alternativen Ausführungsform können auch Teile der Seitenwandungen der Löcher beziehungsweise Gräben aus Substrat- bzw. Leiterplattenmaterial bestehen. Dann muß allerdings in einem separaten Arbeitsgang die Begrenzungsstruktur durch Materialabtrag eingebracht werden, wobei dieser Materialabtrag dann zumindest teilweise auch das Substrat 10 erfaßt. Zusätzlich können dieThe holes 50, 51 or trenches 60 are structured together with the conductor track layers on the substrate. The poorer wettability of the solder in the delimitation structure than on the conductor track layers stems from the fact that the bottom of the delimitation structure is made of non-wettable substrate material (for example ceramic). exists, so that the solder can still wet the wall of the boundary structure, but due to the intermediate floor does not completely fill the structure. In an alternative embodiment, parts of the side walls of the holes or trenches can also consist of substrate or printed circuit board material. Then, however, the delimiting structure must be introduced by material removal in a separate operation, this material removal then at least partially also covering the substrate 10. In addition, the
Leiterbahnwände der Begrenzungsstruktur noch selektiv oxidiert werden, wodurch sie schlecht benetzen. In einer solchen Ausführungsform, bei der auch die Wände oder zumindest auch ein Teil der Wandflächen der Begrenzungsstruktur nicht benetzt werden, kann aufgrund der somit erhöhten Barrierenwirkung der Durchmesser der Löcher auch kleiner als 400 Mikrometer gewählt werden. Conductor walls of the boundary structure are still selectively oxidized, making them poorly wetted. In such an embodiment, in which the walls or at least some of the wall surfaces of the boundary structure are also not wetted, the diameter of the holes can also be selected to be smaller than 400 micrometers due to the increased barrier effect.

Claims

Ansprüche Expectations
1. Elektrische Schaltung auf einem Substrat (10) mit mindestens einem auf einer Leiterbahnschicht (20; 21; 22; 23; 24; 25) befestigten Bauelement (30 ; 40), dadurch gekennzeichnet, daß das Bauelement von Vertiefungen (50; 51; 60) in der Leiterbahnschicht umgeben ist.1. Electrical circuit on a substrate (10) with at least one on a conductor layer (20; 21; 22; 23; 24; 25) attached component (30; 40), characterized in that the component of recesses (50; 51; 60) is surrounded in the conductor track layer.
2. Elektrische Schaltung nach Anspruch 1, dadurch gekennzeichnet, daß das Bauelement auf der Leiterbahnschicht angelötet oder aufgeklebt ist.2. Electrical circuit according to claim 1, characterized in that the component is soldered or glued to the conductor track layer.
3. Elektrische Schaltung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Vertiefungen in Form von insbesondere kreisrunden Löchern oder in Form von Gräben ausgebildet sind.3. Electrical circuit according to one of the preceding claims, characterized in that the depressions are designed in the form of, in particular, circular holes or in the form of trenches.
4. Elektrische Schaltung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß der Boden der Vertiefungen durch das Substrat gebildet wird.4. Electrical circuit according to one of the preceding claims, characterized in that the bottom of the depressions is formed by the substrate.
5. Elektrische Schaltung nach Anspruch 4, dadurch gekennzeichnet, daß die Seitenwände der Vertiefungen teilweise vom Substrat gebildet werden.5. Electrical circuit according to claim 4, characterized in that the side walls of the recesses are partially formed by the substrate.
6. Elektrische Schaltung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß das Substrat eine Leiterplatte oder eine Keramikplatte ist. 6. Electrical circuit according to one of the preceding claims, characterized in that the substrate is a printed circuit board or a ceramic plate.
7. Elektrische Schaltung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Leiterbahnschicht aus einer Kupferschicht, einer Nickel- und einer Goldschicht besteht, wobei die Kupferschicht auf dem Substrat, die Nickelschicht auf der Kupferschicht und die Goldschicht auf der Kupferschicht aufgebracht ist .7. Electrical circuit according to one of the preceding claims, characterized in that the conductor track layer consists of a copper layer, a nickel and a gold layer, the copper layer being applied to the substrate, the nickel layer to the copper layer and the gold layer to the copper layer.
8. Substrat mit mindestens einer Leiterbahnschicht zur Befestigung mindestens eines elektrischen Bauelements, dadurch gekennzeichnet, daß die Leiterbahnschicht8. substrate with at least one interconnect layer for fastening at least one electrical component, characterized in that the interconnect layer
Vertiefungen aufweist zur Bereitstellung einer Fließbarriere für ein Verbindungsmaterial, das zur Befestigung des Bauelements dient, wobei die Vertiefungen eine Fläche zur Befestigung des Bauelements umgeben und in einem solchen Abstand voneinander angeordnet sind, daß zwischen ihnen das Bauelement Platz hat, ohne daß durch das Bauelement die Vertiefungen verdeckt werden müssen.Has depressions to provide a flow barrier for a connecting material, which is used to fasten the component, the depressions surround a surface for fastening the component and are arranged at such a distance from one another that the component has space between them without the component Depressions must be covered.
9. Substrat nach Anspruch 8, dadurch gekennzeichnet, daß die Vertiefungen in Form von insbesondere kreisrunden Löchern oder in Form von Gräben ausgebildet sind.9. Substrate according to claim 8, characterized in that the depressions are in the form of in particular circular holes or in the form of trenches.
10. Substrat nach Anspruch 8 oder 9, dadurch gekennzeichnet, daß der Boden der Vertiefungen durch das Substrat gebildet wird.10. Substrate according to claim 8 or 9, characterized in that the bottom of the depressions is formed by the substrate.
11. Substrat nach Anspruch 8, 9 oder 10, dadurch gekennzeichnet, daß die Seitenwände der Vertiefungen teilweise vom Substrat gebildet werden.11. The substrate of claim 8, 9 or 10, characterized in that the side walls of the recesses are partially formed by the substrate.
12. Substrat nach einem der Ansprüche 8 bis 11, dadurch gekennzeichnet, daß die Leiterbahnschicht aus einer Kupferschicht, einer Nickel- und einer Goldschicht besteht, wobei die Kupferschicht auf dem Substrat, die Nickelschicht auf der Kupferschicht und die Goldschicht auf der Kupferschicht aufgebracht ist. 12. Substrate according to one of claims 8 to 11, characterized in that the conductor track layer consists of a copper layer, a nickel and a gold layer, the copper layer on the substrate, the nickel layer is applied on the copper layer and the gold layer on the copper layer.
PCT/DE2001/000766 2000-03-07 2001-03-01 Electrical circuit and substrate therefor WO2001067832A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
HU0300062A HUP0300062A2 (en) 2000-03-07 2001-03-01 Electrical circuit and substrate therefor
DE50110448T DE50110448D1 (en) 2000-03-07 2001-03-01 ELECTRICAL SWITCHING AND SUBSTRATE THEREOF
JP2001565716A JP2003526220A (en) 2000-03-07 2001-03-01 Electric circuit and substrate for the electric circuit
EP01915069A EP1269805B1 (en) 2000-03-07 2001-03-01 Electrical circuit and substrate therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10010979A DE10010979A1 (en) 2000-03-07 2000-03-07 Electrical circuit on substrate e.g. PCB, has component(s) mounted on conducting track layer on substrate and enclosed by recesses in conducting track layer in form of round holes or trenches
DE10010979.9 2000-03-07

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WO2001067832A1 true WO2001067832A1 (en) 2001-09-13

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KR (1) KR100836974B1 (en)
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4317697B2 (en) 2003-01-30 2009-08-19 パナソニック株式会社 Optical semiconductor bare chip, printed wiring board, lighting unit, and lighting device
DE102010027313A1 (en) * 2010-07-16 2012-01-19 Osram Opto Semiconductors Gmbh Carrier device for a semiconductor chip, electronic component with a carrier device and optoelectronic component with a carrier device
JP5652736B2 (en) 2011-08-11 2015-01-14 ホシデン株式会社 Terminal box
FR2985155B1 (en) * 2011-12-22 2014-10-31 Valeo Vision PRINTED CIRCUIT, IN PARTICULAR FOR AN LED OPTICAL DEVICE FOR A MOTOR VEHICLE

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2156315A1 (en) * 1971-10-12 1973-05-25 Bosch
US4793543A (en) * 1986-08-28 1988-12-27 Stc Plc Solder joint
US5291375A (en) * 1991-09-30 1994-03-01 Kabushiki Kaisha Toshiba Printed circuit board and electric device configured to facilitate bonding
US5872399A (en) * 1996-04-01 1999-02-16 Anam Semiconductor, Inc. Solder ball land metal structure of ball grid semiconductor package
EP0971569A1 (en) * 1998-06-08 2000-01-12 Ford Motor Company Enhanced mounting pads for printed circuit boards

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CS313989A3 (en) * 1989-05-25 1992-01-15 Tesla Vyzkumny Ustav Telekomun Printed circuit board for ceramic components soldering
JPH05291375A (en) * 1992-04-08 1993-11-05 Hitachi Ltd Wafer transport arm
US5596171A (en) * 1993-05-21 1997-01-21 Harris; James M. Package for a high frequency semiconductor device and methods for fabricating and connecting the same to an external circuit
US5383095A (en) * 1993-10-29 1995-01-17 The Whitaker Corporation Circuit board and edge-mountable connector therefor, and method of preparing a circuit board edge
JP2586344B2 (en) * 1994-09-30 1997-02-26 日本電気株式会社 Carrier film
US6465743B1 (en) * 1994-12-05 2002-10-15 Motorola, Inc. Multi-strand substrate for ball-grid array assemblies and method
US6388203B1 (en) * 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US6670222B1 (en) * 1997-06-14 2003-12-30 Jds Uniphase Corporation Texturing of a die pad surface for enhancing bonding strength in the surface attachment
JP3414663B2 (en) * 1999-02-08 2003-06-09 沖電気工業株式会社 Semiconductor device manufacturing method and substrate frame used therefor
US7451862B2 (en) * 2004-07-27 2008-11-18 Ford Global Technologies, Llc Ratcheting one-way clutch having rockers retained in closed pockets
JP4722652B2 (en) * 2005-09-29 2011-07-13 株式会社コナミデジタルエンタテインメント Audio information processing apparatus, audio information processing method, and program
JP4694936B2 (en) * 2005-09-30 2011-06-08 凸版印刷株式会社 Lottery verification management device, lottery verification management method, program thereof and recording medium
JP2007098007A (en) * 2005-10-07 2007-04-19 Akito Takemitsu Chair

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2156315A1 (en) * 1971-10-12 1973-05-25 Bosch
US4793543A (en) * 1986-08-28 1988-12-27 Stc Plc Solder joint
US5291375A (en) * 1991-09-30 1994-03-01 Kabushiki Kaisha Toshiba Printed circuit board and electric device configured to facilitate bonding
US5872399A (en) * 1996-04-01 1999-02-16 Anam Semiconductor, Inc. Solder ball land metal structure of ball grid semiconductor package
EP0971569A1 (en) * 1998-06-08 2000-01-12 Ford Motor Company Enhanced mounting pads for printed circuit boards

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EP1269805A1 (en) 2003-01-02
CZ20022953A3 (en) 2003-06-18
KR20020083170A (en) 2002-11-01
DE50110448D1 (en) 2006-08-24
EP1269805B1 (en) 2006-07-12
DE10010979A1 (en) 2001-09-13
JP2003526220A (en) 2003-09-02
KR100836974B1 (en) 2008-06-10
HUP0300062A2 (en) 2003-05-28
CZ301397B6 (en) 2010-02-17

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