WO2001065673A2 - Circuit servant a fournir une tension de sortie regulee - Google Patents

Circuit servant a fournir une tension de sortie regulee Download PDF

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Publication number
WO2001065673A2
WO2001065673A2 PCT/US2001/006298 US0106298W WO0165673A2 WO 2001065673 A2 WO2001065673 A2 WO 2001065673A2 US 0106298 W US0106298 W US 0106298W WO 0165673 A2 WO0165673 A2 WO 0165673A2
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WO
WIPO (PCT)
Prior art keywords
signal
response
voltage
input terminal
terminal
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PCT/US2001/006298
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English (en)
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WO2001065673A3 (fr
Inventor
Frank B. Jaworski
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Sipex Corporation
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Publication date
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Publication of WO2001065673A2 publication Critical patent/WO2001065673A2/fr
Publication of WO2001065673A3 publication Critical patent/WO2001065673A3/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Definitions

  • the invention relates generally to a circuit that provides a regulated output voltage and more specifically to a circuit that uses a pulse width modulated technique to generate the regulated output voltage.
  • DC-DC converters used to provide regulated voltage typically implement a fixed voltage gain stage and apply pulse frequency modulation (PFM) or pulse skipping techniques to regulate the voltage at the desired value.
  • PFM pulse frequency modulation
  • the power efficiency of such converters decreases as the voltage generated by the initial boost stage is increased beyond that necessary to provide the desired regulated output voltage.
  • the circuit includes a capacitor array that receives an input voltage and provides an output voltage across a load capacitor.
  • the load capacitor is discharged by a device consuming power.
  • the output voltage is regulated according to a control signal that modulates the amount of charge transferred from the capacitor array to the load capacitor.
  • the output voltage is compared with a reference voltage and a control signal responsive to the comparison is generated to terminate the charge transfer to the load capacitor.
  • the capacitor array is able to switch between two or more gain states, depending on the input voltage, to achieve improved efficiency.
  • the present invention provides a power efficient method for generating a substantially constant output voltage for a wide range of input voltages.
  • the battery life can be extended in portable electronic devices, such as cellular telephones and personal digital assistants.
  • the circuit includes a capacitor array, a comparator and an output control module.
  • the capacitor array includes a first array input terminal configured to receive a first control signal, a second array input terminal configured to receive a second control signal, a supply voltage terminal that receives a substantially DC voltage, and an array output terminal to provide the regulated output voltage.
  • the capacitor array generates an intermediate signal in response to the first control signal and the substantially DC voltage.
  • the capacitor array also generates the regulated output voltage at the array output terminal in response to the intermediate signal and the second control signal.
  • the comparator includes a first comparator terminal in communication with the array output terminal and a comparator output terminal that provides a comparator signal in response to the regulated output voltage.
  • the output control module includes a first control module input terminal in communication with the first array input terminal, a second control module input terminal in communication with the comparator output terminal, and a control module output terminal in communication with the second array input terminal.
  • the output control module generates the second control signal at the control module output terminal in response to the comparator signal.
  • the comparator includes a second comparator terminal configured to receive a first reference voltage. The comparator generates the comparator signal in response to the output voltage and the reference voltage.
  • the capacitor array is a switched capacitor array.
  • the invention includes a gain determination module.
  • the capacitor array includes a gain control terminal that receives a gain control signal.
  • the gain determination module includes a first gain determination input terminal in communication with the supply voltage terminal and a gain determination output terminal in communication with the gain control terminal.
  • the gain determination module generates the gain control signal in response to the substantially DC voltage.
  • the gain determination module includes a supply voltage comparator and a pump-switches configuration control module.
  • the supply voltage comparator includes a first input terminal in communication with the first gain determination module input terminal and a supply comparator output terminal. The supply comparator generates a supply comparator signal at the supply comparator output terminal in response to the substantially DC input voltage.
  • the pump-switches configuration control module includes a configuration input terminal in communication with the supply comparator output terminal and a configuration output terminal which is the gain determination module output terminal.
  • the pump-switches configuration control module generates the gain control signal at the configuration output terminal in response to the supply comparator signal.
  • the circuit includes a capacitor array, an error amplifier and an output control module.
  • the capacitor array includes a first array input terminal configured to receive a first control signal, a second array input terminal configured to receive a second control signal, a supply voltage terminal configured to receive a substantially DC voltage, and an array output terminal to provide the regulated output voltage.
  • the capacitor array generates an intermediate signal in response to the first control signal and the substantially DC voltage.
  • the capacitor array also generates the regulated output voltage at the array output terminal in response to the intermediate signal and the second control signal.
  • the error amplifier includes a first amplifier input terminal in communication with the array output terminal and an amplifier output terminal that provides an error signal in response to the regulated output voltage.
  • the output control module includes a first control module input terminal in communication with the first array input terminal, a second control module input terminal in communication with the amplifier output terminal, and a control module output terminal in communication with the second array input terminal.
  • the output control module generates the second control signal at the control module output terminal in response to the error signal and the first control signal.
  • the error amplifier includes a second input terminal configured to receive a first reference voltage.
  • the amplifier generates the error signal in response to the regulated output voltage and the reference voltage.
  • the circuit includes a filter.
  • the filter includes an input terminal in communication with the error amplifier output terminal, and a filter output terminal in communication with the second output control module input terminal. The filter generates a filtered error signal at its output terminal in response to the error signal.
  • the output control module generates the second control signal in response to the first control signal and the filtered error signal.
  • the circuit includes a gain determination module.
  • the capacitor array includes a gain control terminal that receives a gain control signal.
  • the gain determination module includes a first gain determination input terminal in communication with the supply voltage terminal, a second gain determination input configured to receive the regulated output voltage, a third gain determination input terminal configured to receive the error signal, and a gain determination output terminal in communication with the gain control terminal.
  • the gain determination module generates the gain control signal in response to the substantially DC voltage, the regulated output voltage, and the error signal.
  • the gain determination module includes a first comparator, a second comparator, and a gain setting module.
  • the first comparator includes a first input terminal which is the second gain determination input terminal, and an output terminal.
  • the first comparator generates a first gain change signal in response to the regulated output voltage.
  • the second comparator includes a first input terminal which is the third gain determination input terminal, and an output terminal.
  • the second comparator generates a second gain change signal in response to the error signal.
  • the gain setting module includes a first input terminal which is the first gain determination input terminal, a second input terminal in communication with the first comparator output terminal, a third input terminal in communication with the second comparator output terminal, and an output terminal which is the gain determination output terminal.
  • the gain setting module generates the gain control signal in response to the substantially DC voltage, the first gain change signal, and the second gain change signal.
  • the invention in another aspect, relates to a method for generating a regulated output voltage.
  • the method includes the steps of charging a capacitor array in response to a first control signal thereby generating an intermediate signal, and controlling the intermediate signal in response to a second control signal, thereby generating the regulated output voltage.
  • the method includes the additional step of generating the second control signal in response to the regulated output voltage.
  • the generating step includes comparing the regulated output voltage to a first reference voltage and generating the second control signal in response to the comparison.
  • the capacitor array is a switched capacitor array and the method includes the step of switching the capacitor array from a first gain state to a second gain state in response to an array control signal.
  • the method includes the step of generating the array control signal in response to the array input voltage.
  • the method includes the step of comparing an input array voltage to a second reference voltage and generating the array control signal in response to the comparison.
  • Another embodiment of the invention provides a method for dynamically controlling the gain of a capacitor array.
  • the method includes the steps of comparing an array output voltage to a first reference voltage and generating a first gain change signal in response to the comparison, and configuring the gain of the capacitor array in response to the gain change signal.
  • the method also includes the steps of generating a differential signal in response to the output voltage and a second reference voltage, comparing the differential signal to a third reference voltage and generating a second gain change signal in response to the comparison, and configuring the gain of the capacitor array in response to the second gain change signal.
  • Another embodiment of the method for generating a regulated output voltage includes the steps of charging the capacitor array in response to the regulated output voltage, and transferring charge from the capacitor to a load for a predetermined time.
  • the charging step includes generating a differential signal in response to the regulated output voltage and reference voltage, and terminating the charging of the capacitor in response to the differential signal.
  • FIG. 1 is a block diagram of an embodiment of a regulated output voltage circuit in accordance with the present invention
  • Fig. 2 is a block diagram of another embodiment of a regulated output voltage circuit constructed in accordance with the present invention.
  • Fig. 3 is a block diagram of another embodiment of a regulated output voltage circuit constructed in accordance with the present invention.
  • Fig. 4 is a block diagram showing in more detail an embodiment of the gain determination module disclosed in Fig. 3;
  • Fig. 5 is a block diagram of another embodiment of a regulated output voltage circuit constructed in accordance with the present invention;
  • Fig. 6 is a block diagram showing in more detail an embodiment of the gain determination module disclosed in Fig. 5;
  • Fig. 7 is a block diagram showing in more detail an embodiment of the oscillator circuit disclosed in Fig. 3;
  • Fig. 8 is a block diagram showing in more detail an embodiment of the capacitor array circuit disclosed in Fig. 3;
  • Fig. 9 is a schematic diagram showing in more detail an embodiment of the pump-switches module disclosed in Fig. 8;
  • Fig. 10 is a schematic diagram showing in more detail an embodiment of the pump- switches module disclosed in Fig. 8;
  • Fig. 11 is a flowchart representation of an embodiment of a method for providing a regulated output voltage in accordance with the present invention.
  • an embodiment of a regulated voltage supply constructed in accordance with the invention includes a capacitor array 20, a voltage monitor 22, and an oscillator 64.
  • the capacitor array 20 has a voltage input terminal 24 configured to receive an unregulated voltage Vin and a regulated output voltage terminal 28 to provide a regulated output voltage Vout.
  • the voltage monitor 22 includes a comparator 36 and an output control module 52. The output voltage Vout is applied to one input terminal 32 of the comparator 36.
  • the second comparator input terminal 40 is configured to receive a reference voltage Vrefl .
  • the comparator output terminal 44 provides a comparison signal COMP indicative of whether the output voltage Vout exceeds Vrefl.
  • the comparison signal COMP is supplied to a first input terminal 48 of the output control module 52.
  • a second input terminal 56 of the output control module 52 is in communication with the output terminal 60 of the oscillator 64.
  • the output terminal 68 of the output control module 52 provides a control signal CSl to a control terminal 72 of the capacitor array 20.
  • a second control terminal 76 of the capacitor array 20 is in communication with the output terminal 60 of oscillator 64.
  • the capacitor array 20 is charged by the input voltage Vin and supplies charge to load capacitor Cload 10 to generate the regulated output voltage Vout.
  • the output voltage Vout is compared to the reference voltage Vrefl in comparator 36 and the resulting comparator signal COMP is applied to the output control module 52 along with oscillator signal OSC from oscillator 64.
  • the output control module 52 generates control signal CSl in response to received input signals COMP and OSC.
  • Control signal CSl is applied to the capacitor array 20 to control the pulse width (i.e., the duration) of the current supplied from the capacitor array 20 to the load capacitor Cload 10 thereby maintaining the output voltage Vout in regulation.
  • another embodiment of the voltage monitor 22 includes an error amplifier 37, an optional loop filter 47 and the output control module 52.
  • the output voltage Vout is applied to one input terminal 33 of the error amplifier 37.
  • the second error amplifier input terminal 41 is configured to receive a reference voltage Vrefl.
  • the error amplifier output terminal 45 is in communication with input terminal 46 of the loop filter 47.
  • the loop filter output terminal 49 is in communication with the first input terminal 48 of the output control module 52.
  • the second input terminal 56 of the output control module 52 is in communication with the output terminal 60 of the oscillator 64.
  • the output terminal 68 of the output control module 52 is in communication with control terminal 72 of the capacitor array.
  • the capacitor array 20 is charged by the input voltage Vin and supplies charge to the load capacitor Cload 10 to generate the regulated output voltage Vout.
  • Error amplifier 37 generates a differential signal DIFF substantially proportional to the difference between the output voltage Vout and the reference voltage Vrefl .
  • the differential signal DIFF is applied to loop filter 47.
  • Loop filter 47 filters the differential signal DIFF to generate a time averaged signal LFLTR which is provided to the output control module 52.
  • the output control module 52 generates control signal CSl, in response to input signals LFLTR and OSC.
  • Control signal CSl is applied to capacitor array 20 to control the pulse width (i.e., the duration) of the current supplied from the capacitor array 20 to the load capacitor Cload 10, thereby maintaining the output voltage Vout in regulation.
  • a first gain Gi of 1.5 enables generation of the required output voltage Vout of 5.0V for small loads.
  • a second gain G 2 greater than the first gain G is required in order to generate the required output voltage Vout.
  • a second gain G 2 of 2 enables the circuit to supply the desired output voltage Vout for an input voltage Vin of at least 2.5V.
  • a gain determination module 100 is used to control the gain of the capacitor array 20.
  • a first gain determination module input terminal 104 is configured to receive the unregulated supply voltage Vin.
  • a second gain determination module input terminal 108 is configured to receive a second reference voltage Vref2.
  • the gain determination module 100 generates at its output terminal 112 a gain configuration signal
  • the gain configuration signal CONFIG is provided to a third control terminal 80 of the capacitor array 20 to control its gain dynamically.
  • the gain determination module 100 includes a supply comparator 99 and a pump-switches configuration control module 98.
  • the supply comparator 99 has a first input terminal 92 which is the first gain determination module input terminal 104, a second input terminal 88 which is the second gain determination module input terminal 108, and an output terminal 93.
  • the pump-switches configuration control module 98 has an input terminal 84 in communication with the supply comparator output terminal 93 and has an output terminal 96 which is the gain determination module output terminal 112. In operation, the unregulated input voltage Vin received at the first gain determination module input terminal 104 is compared to the second reference voltage Vref2 by the supply comparator 99.
  • the gain determination module 100 asserts a first state of the gain configuration signal CONFIG.
  • capacitor array 20 is configured to provide a first gain Gi.
  • the gain determination module 100 asserts a second state of the gain configuration signal CONFIG.
  • capacitor array 20 is configured to provide a second gain G 2 .
  • the gain determination module includes a windowing module (not shown) in place of the supply comparator 99.
  • the windowing module generates a signal indicative of which one of multiple voltage ranges includes the input voltage Vin.
  • a corresponding voltage gain is established in the capacitor array 20.
  • the multiple gain selectivity feature results in further improvement to the power conversion efficiency of the circuit and further extends the battery lifetime.
  • Vrefl is generated by a bandgap reference circuit.
  • Vref2 is generated by a bandgap reference circuit.
  • the reference voltages Vrefl and Vref2 are equal.
  • a scaled voltage representation of the output voltage Vout is generated by a voltage divider circuit (not shown) and supplied to comparator 36 of the voltage monitor 22.
  • a voltage divider circuit can be used to generate a scaled voltage representation of the unregulated input voltage Vin and is communicated to the supply comparator 99.
  • the gain determination module 100' is used to control the gain of capacitor array 20.
  • the gain determination module 100' includes a first input terminal 104 configured to receive the unregulated supply voltage Vin, a second input terminal 105 configured to receive a first reference voltage Vrefl, a third input terminal 106 configured to receive a second reference voltage Vref2, a fourth input terminal 107 configured to receive the regulated output voltage Vout, and a fifth input terminal 109 configured to receive the time average signal LFLTR.
  • the gain determination module 100' generates a gain configuration signal CONFIG at its output terminal 112.
  • the regulated output voltage Vout is applied to input terminal 107
  • the second reference voltage Vref2 is received at input terminal 106
  • the first reference voltage Vrefl is received at input terminal 105
  • the time average signal LFLTR is received at input terminal 109
  • the unregulated supply voltage Vin is received input terminal 104.
  • the gain determination module 100 In response to input signals Vin, Vout, LFLTR, Vrefl and Vref2, the gain determination module 100 generates the gain configuration signal CONFIG at its output terminal 112 and provides the gain configuration signal CONFIG to the third control signal input 80 of the capacitor array 20. In response to the gain configuration signal CONFIG the capacitor array 20 is configured to operate at the appropriate gain.
  • the gain determination module 100' includes an increment comparator 130, a decrement comparator 120, a gain setting module 190, and an optional filter 127.
  • the filter 127 has an input terminal 128 that is the gain determination module input terminal 107, and an output terminal 129.
  • the increment comparator 130 has first input terminal 134 which is the gain determination module input terminal 105, a second input terminal 132 in communication with the filter output terminal 129, and an increment comparator output terminal 136.
  • the decrement comparator 120 has a first input terminal 124 which is the gain determination module input terminal 106, a second input terminal 122 which is the gain determination module input terminal 109, and a decrement comparator output terminal 126.
  • the gain setting module 190 has a first input terminal 191 which is the gain determination module input terminal 104, a second input terminal 192 in communication with the increment comparator output terminal 136, a third input terminal 193 in communication with the decrement comparator output terminal 126, and an output terminal 194 which is the gain determination module output terminal 112.
  • filter input terminal 128 receives the regulated output voltage Vout and generates a time average signal GFLTR at its output terminal 129.
  • Increment comparator 130 receives the time average signal and generates gain increment signal INCREMENT at its output terminal 136 in response.
  • Decrement comparator 120 receives the time average signal LFTLR at input terminal 122 and the second reference voltage Vref2 at input terminal 124, and generates decrement signal DECREMENT at its output terminal 126 in response.
  • the gain setting module 190 receives the unregulated reference voltage Vin at input terminal 104, the gain increment signal INCREMENT at input terminal 192, and the gain decrement signal DECREMENT at input terminal 193. In response, the gain setting module 190 generates the gain configuration signal CONFIG at output terminal 194 which is the gain determination module output terminal 112.
  • the third control signal input terminal 80 of capacitor array 20 receives the gain configuration signal CONFIG and is configured to operate at the corresponding gain.
  • the gain determination module 100 provides a plurality of gain configuration signals CONFIG', CONFIG", CONFIG'" (generally CONFIG) at its output terminal 112 to the third control input terminal 80 of the capacitor array 20.
  • a first gain configuration signal CONFIG' is generated in response to Vin and provided to capacitor 20.
  • the capacitor 20 is configured to an initial gain state GI .
  • the gain determination module 100' generates the additional gain configuration signals CONFIG" and CONFIG'" in response to received signals INCREMENT and DECREMENT.
  • Gain configuration signals CONFIG' ' and CONFIG' ' ' are provided to the capacitor 20 and in response the gain of capacitor array 20 is either incremented or decremented to a new gain state G2 thereby providing an increased power efficiency relative to initial gain state GI.
  • the oscillator 64 includes a clock manager 200.
  • the clock manager 200 has a first input terminal 204, a second input terminal 208, a third input terminal 212, and an output terminal 202.
  • the output terminal 202 is the oscillator output terminal 60 and provides the oscillator signal OSC.
  • the clock manager 200 receives an input clock signal CLK of substantially fixed frequency f c i k at terminal 204.
  • Input terminals 208 and 212 accepts logic signals CLK/4 and CLK* 8 indicative of the desired frequency, f osc of the oscillator signal OSC, to the clock manager 200.
  • the oscillator frequency f osc is unchanged, increased by a factor of 8, or decreased by a factor of 1/4.
  • These logic signals CLK/4 and CLK*8 are generally determined by known circuit parameters (e.g. load value) and provided by the user externally.
  • the clock manager 200 monitors the output voltage Vout to internally determine the optimum oscillator frequency f osc . In this case the user would not need to externally control the clock frequency.
  • the clock is generated internally and is not synchronized or locked to a user supplied clock, thus eliminating the need for an additional I/O pin. Referring to Fig.
  • the capacitor array 20 includes a clock phase control module 224, a driver module 228, multiple fly capacitors Cfiyl ...CflyN, and a pump-switches module 232.
  • the clock phase control module 224 has an input terminal 221 which is the capacitor array input terminal 80, a second input terminal 222 which is the capacitor array input terminal 72, a third input terminal 223 which is the capacitor array input terminal 76, and terminals 225', 225", 225'" (generally 225) for providing phase adjusted control signals PCS1, PCS2, PCSN
  • the driver module 228 includes output terminals 230', 230", 230'" (generally 230) for providing low impedance control signals ACS1, ACS2, ACSN (generally ACS) capable of driving the switches in the pump-switches module 232.
  • the pump-switches module 232 includes a supply voltage input terminal 233 which is the capacitor array input terminal 24, input terminals 234', 234", 234" (generally 234) to receive amplified controls signals ACS1, ACS2, ACSN respectively, and an output terminal 235 which is the capacitor array output terminal 28.
  • the clock phase control module 224 generates the phase adjusted control signals PCS in response to the CONFIG, CSl and OSC signals.
  • the driver module 228 generates the low impedance control signals ACS from the phase adjusted control signals PCS.
  • the pump-switches module 232 is configured to a certain gain state in response to the amplified control signals ACS and generates the output voltage Vout across load capacitor Cload 10. As the control signal CSl and the configuration signal CONFIG change in response to the output voltage Vout and input voltage Vin, respectively, the phase adjusted control signals PCS change so that the pump-switches module 232 maintains the output voltage Vout in regulation.
  • the pump-switches module 232 includes four switches 250, 254, 258, 262 and a single fly capacitor Cfly 266. Hence this module contains only one gain state. Additional fly capacitors are required to achieve multiple gain states as previously discussed. However, this single gain state example is useful to illustrate how the output is regulated using the pulse width modulation control.
  • the switches 250, 254, 258, 262 can be metal oxide semiconductor field effect transistors (MOSFETs) or other devices capable of controlling the charge transferred to and from the fly capacitor Cfly 266.
  • Switch 250 controls the flow of current from source Vin through input terminal 233 to terminal 268 of fly capacitor Cfly 266 in response to low impedance control signal ACS2.
  • Switch 258 controls the flow of current from terminal 270 of fly capacitor Cfly 266 to ground in response to low impedance control signal ACS2.
  • Low impedance control signal ACS2 is inverted to ACS2 by inverter 272 and used to operate switch 254 to control the flow of current from terminal 268 of fly capacitor Cfly 266 to output terminal 235.
  • Switch 262 controls the flow of current between input terminal 233 and terminal 270 of fly capacitor Cfly 266, in response to low impedance control signal ACS1.
  • the load (not shown) generates a load current that discharges the load capacitor Cload 10. As discussed above, the charge on the load capacitor Cload 10 is refreshed periodically by the fly capacitor Cfly 266.
  • fly capacitor Cfly 266 is charged approximately to voltage Vin in response to the unregulated input voltage Vin applied to input terminal 233.
  • switches 250 and 258 transition to an open, and switches 254 and 262 transition to the closed state in response to a change in the low impedance control signals ACS. Consequently, the voltage at terminal 270 of fly capacitor Cfly 266 increases to the input voltage Vin and the voltage at terminal 268 of fly capacitor Cfly 266 increases to approximately twice the supply voltage Vin.
  • fly capacitor Cfly 266 transfers charge to the load capacitor Cload 10 through the pump-switches module output terminal 235.
  • Vout voltage across Cload 10
  • Vrefl the regulated value
  • low impedance control signal ACS1 opens switch 262 via the output control module 52 discussed earlier, thereby producing the pulse width modulated control. If the output voltage Vout never increases to match the regulated value (for example under heavy load conditions), then switch 262 remains closed for the full second half of period T.
  • switch 254 is opened and switch 262 is also opened (if not already open), thus terminating the charge transfer to load capacitor Cload 10 until the next clock cycle.
  • switch 250 controls the flow of current from input terminal 233 to terminal 268 of fly capacitor Cfly 266 in response to low impedance control signal ACS1.
  • Switch 258 controls the flow of current from terminal 270 of fly capacitor Cfly 266 to ground in response to low impedance control signal ACS2.
  • Low impedance control signal ACS2 is inverted by inverter 272 or 273 to generate low impedance control signal ACS2.
  • the inverted control signal ACS2 is used to operate switch 254 to control the flow of current from terminal 268 of fly capacitor Cfly 266 to output terminal 235.
  • Inverted control signal ACS2 is also used to operate 262 to control the flow of current between input terminal 233 and terminal 270 of fly capacitor Cfly 266.
  • the load (not shown) receives a load current that discharges the load capacitor Cload 10. As previously discussed, the charge on the load capacitor Cload 10 is refreshed periodically by the fly capacitor Cfly 266. In operation, for a portion of the first half of a clock cycle of period T, switches 250 and
  • fly capacitor Cfly 266 begins charging to the unregulated input voltage Vin applied to input terminal 233.
  • the charging time of fly capacitor Cfly 266 is pulse width modulated based on the magnitude of the load across to load capacitor Cload 10. For heavy loads, the charge time can reach a maximum of one half the clock cycle and the fly capacitor Cfly 266 is charged to approximately the input voltage Vin. For lighter loads, the charge time is terminated before the end of the first half of the clock cycle in response to low impedance control signals ACS, so that fly capacitor Cfly 266 is neither charging or discharging during a portion of the clock cycle.
  • the invention includes a method for generating a regulated output voltage.
  • a capacitor array 20 is charged in response to a first control signal.
  • an intermediate signal is generated by the charged capacitor array 20.
  • the intermediate signal is periodic and has an on time that does not exceed its off time.
  • the regulated output voltage Vout is compared to a first reference voltage Vrefl. If Vout does not exceed Vrefl, a determination as to whether the end of the clock cycle has occurred is determined in step 316. The charging of the load capacitor Cload 10 continues if time remains in the clock cycle, otherwise the method returns to step 300.
  • step 324 the method waits for the clock cycle to end before again charging the capacitor array 20 at the start of the next clock cycle in step 300.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention concerne un circuit et un procédé servant à fournir une tension de sortie régulée. Le circuit comprend un groupement de condensateurs, un comparateur et un module de commande de sortie. Le groupement de condensateurs reçoit une tension d'entrée, un premier et un deuxième signal de commande, et produit en réponse une tension de sortie régulée. Le comparateur compare la tension de sortie régulée à une tension de référence, et produit en réponse un signal de comparateur. Le module de commande de sortie reçoit le signal de comparateur et le premier signal de commande, et fournit en réponse le deuxième signal de commande au groupement de condensateurs.
PCT/US2001/006298 2000-02-29 2001-02-27 Circuit servant a fournir une tension de sortie regulee WO2001065673A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US18562700P 2000-02-29 2000-02-29
US60/185,627 2000-02-29
US09/789,853 2001-02-21
US78985301 2001-02-23

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WO2001065673A2 true WO2001065673A2 (fr) 2001-09-07
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0862260A2 (fr) * 1997-02-28 1998-09-02 Seiko Instruments Inc. Circuit pompe de charge

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06351229A (ja) * 1993-06-08 1994-12-22 Sony Corp 出力電圧安定化機能付チャージポンプ式昇圧回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0862260A2 (fr) * 1997-02-28 1998-09-02 Seiko Instruments Inc. Circuit pompe de charge

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 03, 28 April 1995 (1995-04-28) & JP 06 351229 A (SONY CORP), 22 December 1994 (1994-12-22) *

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