WO2001063663A1 - Structure d'isolation a planeite accrue et procede correspondant - Google Patents

Structure d'isolation a planeite accrue et procede correspondant Download PDF

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Publication number
WO2001063663A1
WO2001063663A1 PCT/US2000/032918 US0032918W WO0163663A1 WO 2001063663 A1 WO2001063663 A1 WO 2001063663A1 US 0032918 W US0032918 W US 0032918W WO 0163663 A1 WO0163663 A1 WO 0163663A1
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WO
WIPO (PCT)
Prior art keywords
substrate
insulating
isolation structure
trench
insulating structure
Prior art date
Application number
PCT/US2000/032918
Other languages
English (en)
Inventor
Frederick N. Hause
Thomas E. Spikes, Jr.
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO2001063663A1 publication Critical patent/WO2001063663A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Definitions

  • This invention relates generally to semiconductor processing, and more particularly, to an isolation structure and a method of fabricating the same on a substrate 2.
  • circuits The implementation of integrated circuits involves connecting isolated circuit devices through specific electrical pathways Where integrated circuits are implemented in silicon, it is necessary, therefore, to initially isolate the various circuit devices built into the silicon substrate from one another The circuit devices are thereafter interconnected to create specific circuit configurations through the use of global interconnect or metallization layers and local interconnect layers
  • LOCOS Local oxidation of silicon
  • MOS metal oxide semiconductor
  • a thin pad oxide layer is thermally grown on a silicon substrate surface and coated with a layer of chemical vapor deposition ("CVD") silicon nitride
  • CVD chemical vapor deposition
  • the active regions of the substrate are then defined with a photolithographic step
  • the nitride layer is then dry etched and the pad oxide layer wet or dry etched with the photoresist left in place to serve as a masking layer for a subsequent channel stop implant
  • field oxide regions are thermally grown by means of a wet oxidation step The oxidation of the silicon proceeds both vertically into the substrate and laterally under the edges of the nitride layer, resulting in the formation of structures commonly known as bird's beaks
  • bird's beak structures are problematic in a number of ways To begin with, bird's beak formation can create significant limitations on the packing density of devices in an integrated circuit Design rules for LOCOS processes must restrict the gaps between adjacent devices to account for the lateral encroachment of bird's beaks
  • the very shape of a bird's beak can result in the exposure of the substrate surface during subsequent overetching to open contacts for metallization This can result in the source of the transistor becoming shorted to the well region when the metal interconnect film is deposited This problem may be particularly acute in CMOS circuits where shallower junctions are used, due to the higher propensity for the exposure of the well regions While some improvement in the formation of bird's beak structures has occurred as a result of the introduction of techniques such as the etchback of portions of the field oxide structures, deposition of a silicon nitride layer without a pad oxide layer, and use of a thin pad oxide covered with polysilicon, the difficulties associated with bird's beak formation have not been completely eliminated
  • trench based isolation structures In trench based isolation structures, a damascene process is used to pattern and etch a plurality of trenches in the silicon substrate The trenches are then refilled with a CVD silicon dioxide or doped glass layer that is plana ⁇ zed back to the substrate surface using etchback plana ⁇ zation or chemical mechanical polishing ("CMP")
  • CMP chemical mechanical polishing
  • conventional trench and refill isolation techniques eliminate the difficulties associated with bird s beak formation in LOCOS processes, there are nevertheless difficulties associated with the trench and refill isolation techniques
  • One of these difficulties is the formation of unwanted insulating structures or "stringers" on the upper surfaces of transistor gate electrodes Stringer formation is largely the result of the topography of conventionally fabricated trench isolation structures
  • the isolation structure is formed with a vertical step projecting above an adjacent active region During gate electrode fabrication, a blanket film of polysilicon is deposited over the active region and the isolation structure step, resulting in a relatively vertical step in the polysilicon film The polysilicon film is thereafter directionally etched to
  • a method of fabricating an isolation structure includes forming an insulating structure on a substrate
  • the insulating structure has a step with a slope
  • the insulating structure is sputter etched to reduce the slope of the step
  • a method of fabricating a circuit device on a active area of a substrate includes forming an insulating structure around the active area
  • the insulating structure has a sloped step adjacent to the active area
  • the insulating structure is sputter etched to reduce the slope of the step
  • a conductor structure is formed over the step
  • a circuit device is provided that includes a substrate that has a trench therein adjacent to an active region
  • An insulating structure is positioned in the trench and has a step projecting above the substrate The step slopes away from the active region A conductor structure is positioned over the step
  • FIG 1 a plan view of a conventional field effect transistor circumscribed by a conventional isolation structure on a semiconductor substrate
  • FIG 2 is a pictorial view of the transistor and isolation structure shown in FIG 1
  • FIG 3 is a cross-sectional view of FIG 1 taken at section 3-3
  • FIGS 4-7 are cross-sectional views like FIG 3 depicting the sequential fabrication steps to build the isolation structure of FIGS 1-3,
  • FIG 8 is a cross-sectional view like FIG 3 of an exemplary embodiment of an isolation structure fabricated in accordance with the present invention
  • FIG 9 is a cross-sectional view like FIG 8, but depicting initial definition of the isolation structure in accordance with the present invention
  • FIG 10 is a cross-sectional view like FIG 9 depicting the sputter etching of the isolation structure in accordance with the present invention.
  • FIG 11 is a cross-sectional view like FIG 10 depicting gate electrode formation and spacer deposition in accordance with the present invention MODES FOR CARRYING OUT THE INVENTION
  • FIGS 1 and 2 depict, respectively, a plan view and a pictorial view of a conventional field effect transistor 10 fabricated on an active area 12 of a semiconductor substrate 14 Only a small portion of the substrate 14 is depicted
  • the active area 12 is circumscribed by a trench isolation structure 16
  • a trench isolation structure 16 As a result of the conventional process used to fabricate the isolation structure 16, to be described in more detail below, there exists a step 18 between the upper surface of the active area 12 and the upper surface 20 of the isolation structure 16
  • the transistor 10 consists of a polysilicon gate electrode 22 that has a central portion 24 positioned on the active area 12 and end portions 26 and 28 that extend over the step 18 and project short distances over the upper surface 20 of the isolation structure 16 as best seen in FIG 2
  • Source/drain regions 30 and 32 are fabricated in the substrate 14 on either side of the gate electrode 22
  • the gate electrode 22 is bracketed by a pair of insulating sidewall spacers 34 and 36
  • the step 18 has a relatively vertical slope
  • An unwanted byproduct of this vertical slope is the formation of insulating stringers 38 and 40 on the gate electrode 22
  • the stringers 38 and 40 are remnants of a blanket deposited insulating film that is thereafter anisotropically etched to leave the insulating sidewall spacers 34 and 36
  • the anisotropic etch of the blanket deposited insulating material used to define the spacers 34 and 36 does not remove all of the insulating material from the upper surfaces of the gate electrode 22, and leaves the stringers 38 and 40 behind
  • FIG 3 is a cross sectional view of FIG 1 taken at section 3-3
  • the isolation structure 16 is formed in a trench 42 etched m the substrate 14
  • the trench 42 is lined with a liner oxide film 44
  • the upper surface of the active area 12 is capped with a pad oxide film 46 that bridges to the isolation structure 16
  • FIGS 1 and 2 cannot completely remove all of the insulating material deposited adjacent to the step 48 Thus, the stringer 40 depicted in FIG 3 and the stringer 38 depicted in FIGS 1 and 2 are left behind as shown
  • the stringers 38 and 40 represent areas of the polysilicon gate electrode 22 that will remain covered during subsequent sihcide processing Accordingly, sihcide will not form on these covered portions of the gate 22 Non-si cided areas of the gate 22 may produce relatively high resistivities with later- formed contacts (not shown) to the gate 22 If the stringers 38 and 40 are large enough, they may completely insulate the underlying gate 22 from a subsequently formed contact and produce a device failure In addition, the stringers 38 and 40 simply increase the overall resistivity of the gate electrode 22 A conventional process flow for fab ⁇ cating the isolation structure 16 may be understood by referring now to FIGS 4, 5, 6 and 7 and initially to FIG 4 Initially, the pad oxide layer 46 is fabricated on the upper surface of the substrate 14 with a thickness of about 100 to 200 A by, for example, thermal oxidation in an oxygen containing ambient, CVD or the like Thereafter, a silicon nitride film 50 is formed on
  • the liner oxide layer 44 is next fabricated in the trench 42, again by thermal oxidation, CVD or the like
  • the substrate 14 is subjected to a blanket CVD of an oxide material to establish the isolation structure 16 with about 1000 to 2500 A projecting above the pad oxide film 46
  • CVD tetra-ethyl-ortho-si cate or silane may be used
  • the blanket CVD of the isolation structure 16 produces a bridging between the pad oxide layer 46 and the isolation structure 16 and a substantially vertical interface 52 between the edge of the silicon nitride film 50 and the isolation structure 16
  • the isolation structure 16 is plana ⁇ zed to the silicon nitride film 50 by etchback planarization, CMP or other well known planarization techniques
  • the nitride film 50 is stripped by a hot phosphoric acid dtp, leaving the exposed pad oxide film 46 and the isolation structure 16
  • the interface 52 that formerly existed between the isolation structure 16 and the edge of the silicon nitride film 50 is converted to the aforementioned step 18
  • the presence of the substantially vertical step 18 will produce a relatively non-planar blanket deposition of polysilicon for the gate electrode 22 depicted in FIGS 1 -3 and the deposited oxide spacer layer (not shown)
  • the subsequent anisotropic etch to define the spacers 34 and 36 in FIGS 1 and 2 may not remove all of the available oxide material adjacent to the step 48 in the polysilicon gate electrode 22 and result in the formation of the stringers 38 and 40
  • FIG 8 is a cross-sectional view like FIG 3
  • FIG 8 depicts an exemplary embodiment of an isolation structure 54 fabricated in accordance with the present invention and surrounding an active region 56 upon which a transistor 58 is formed
  • the transistor 58 is depicted as a field effect transistor
  • the isolation structure 54 is formed in a trench 60 fabricated in a semiconductor substrate 62
  • a pad oxide film 64 is formed on the upper surface of the active area 56 and generally bridges over to the isolation structure 54
  • the terms "formed on”, “disposed on” or “positioned on” should be construed to include the possibility that a given layer or structure may be formed on another given layer or structure with a third or other intervening layers or structures disposed between the two
  • the substrate 62 may be composed of n-doped silicon, p-doped silicon, sihcon-on-insulator, or other types of substrate materials
  • the trench 60 has sloping
  • FIGS 9, 10 and 11 An exemplary process flow for fab ⁇ cating the isolation structure 54 in accordance with the present invention may be understood by referring now to FIGS 9, 10 and 11 and initially to FIG 9
  • the substrate 62 may be generally processed as described above using the conventional process depicted in FIGS 1-7, or other well know techniques
  • the trench 60 is formed in the substrate 62 and an insulating structure is formed in the trench 60
  • the insulating structure consists of the isolation structure 54 with an initially substantially vertical step 66 as shown in FIG 9
  • the isolation structure 54 is subjected to a sputter etch to lessen the slope of the step 66 and thus yield a more gently sloping profile shown in FIG 8
  • the sputter etch will remove some of the upper surface of the isolation structure 54 and the pad oxide film 64 However, the sputter etch will exhibit a preferentially higher rate of film removal on the step 66, and thus produce the desired reduction in the slope of the step 66
  • the aforementioned etch tool includes an RF power coil and a power supply for applying bias to a chuck for holding the substrate 62
  • the sputter etch may be subdivided into four stages a purge stage, a stability stage, an ignition stage and an etch stage
  • the purge stage is designed to purge the chamber of unwanted contaminants lasts
  • a vacuum is drawn for approximately three seconds without power applied to either the RF coil or the wafer chuck
  • the stability stage which lasts approximately 5 seconds again without power applied to either the RF coil or the wafer chuck
  • argon is fed into the chamber in two streams, a low flow stream of about 5 seem and a high flow stream of about 50 seem
  • the ignition stage is next commenced and lasts for about 3 seconds during which about 225 watts is supplied by the RF power coil and the same to the wafer chuck
  • the argon high flow is cut off and the low flow of about 5 seem is maintained
  • the final or etch stage is next performed for about 7 to 9 seconds utilizing the same power settings for RF coil and wafer chuck as in the ignition stage and the same argon gas flow as in the ignition stage
  • the sputter etch yields a more gently sloping step 66 as depicted in FIG 10
  • a conductor structure 68 is formed over the step 66
  • the conductor structure 68 may the gate electrode 68 shown or another type of conductor structure Bulk polysilicon may be blanket deposited and subsequently anisotropically etched to yield the patterned gate electrode 68
  • other conducting materials may be used to fabricate the gate 68 as desired, such as tantalum, titanium, titanium nitride, tungsten or the like
  • the more gently sloping step 66 results in a more planar gate electrode 68 with a more gently sloping step 70
  • an insulating film 72 may be deposited over the polysilicon gate electrode 66 and thereafter anisotropically etched to yield spacers of the type depicted in FIG 1
  • the more gently sloping step 70 of the polysilicon gate 68 produces a more planar insulating film 72 that will not leave stringers during

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

La présente invention concerne, d'une part un dispositif de circuit (56) intégrant une structure d'isolation, et d'autre part divers procédés de fabrication correspondants. Pour un premier aspect, l'invention concernant un procédé de fabrication d'un dispositif de circuit (58) sur une zone active (56) d'un substrat (62). Le procédé comporte la formation d'une structure isolante (54) autour de la zone active (56). La structure active (54) comporte une banquette inclinée (66) contre la zone active (56). La structure isolante (54) est attaquée par étincelage de façon à réduire la pente de la banquette (66). Une structure conductrice (68) est réalisée sur la banquette (66). Le dispositif (58) et le procédé garantissent une meilleure planéité des structures d'isolation.
PCT/US2000/032918 2000-02-24 2000-12-04 Structure d'isolation a planeite accrue et procede correspondant WO2001063663A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51194500A 2000-02-24 2000-02-24
US09/511,945 2000-02-24

Publications (1)

Publication Number Publication Date
WO2001063663A1 true WO2001063663A1 (fr) 2001-08-30

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4389294A (en) * 1981-06-30 1983-06-21 International Business Machines Corporation Method for avoiding residue on a vertical walled mesa
US5672539A (en) * 1994-01-14 1997-09-30 Micron Technology, Inc. Method for forming an improved field isolation structure using ozone enhanced oxidation and tapering
US5981356A (en) * 1997-07-28 1999-11-09 Integrated Device Technology, Inc. Isolation trenches with protected corners

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4389294A (en) * 1981-06-30 1983-06-21 International Business Machines Corporation Method for avoiding residue on a vertical walled mesa
US5672539A (en) * 1994-01-14 1997-09-30 Micron Technology, Inc. Method for forming an improved field isolation structure using ozone enhanced oxidation and tapering
US5981356A (en) * 1997-07-28 1999-11-09 Integrated Device Technology, Inc. Isolation trenches with protected corners

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