WO2001058026A2 - Amplificateur de puissance ultra-lineaire a ondes porteuses multiples - Google Patents

Amplificateur de puissance ultra-lineaire a ondes porteuses multiples Download PDF

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Publication number
WO2001058026A2
WO2001058026A2 PCT/IL2000/000072 IL0000072W WO0158026A2 WO 2001058026 A2 WO2001058026 A2 WO 2001058026A2 IL 0000072 W IL0000072 W IL 0000072W WO 0158026 A2 WO0158026 A2 WO 0158026A2
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WIPO (PCT)
Prior art keywords
signals
amplifier
input
signal
digital
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PCT/IL2000/000072
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English (en)
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WO2001058026A3 (fr
Inventor
Yuval Shalom
Danny Arison
Kalman Kaufman
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Wiseband Communications Ltd.
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Priority to PCT/IL2000/000072 priority Critical patent/WO2001058026A2/fr
Priority to AU2000223178A priority patent/AU2000223178A1/en
Publication of WO2001058026A2 publication Critical patent/WO2001058026A2/fr
Publication of WO2001058026A3 publication Critical patent/WO2001058026A3/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
    • H03F1/3229—Modifications of amplifiers to reduce non-linear distortion using feed-forward using a loop for error extraction and another loop for error subtraction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers
    • H04B2001/0433—Circuits with power amplifiers with linearisation using feedback
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers
    • H04B2001/0441—Circuits with power amplifiers with linearisation using feed-forward

Definitions

  • the present invention relates generally to high-performance amplifiers for communications applications, and specifically to broadband, multi-carrier feedforward amplifiers
  • Fig 1 is a schematic block diagram showing the design of a base station transmitter 20, as is commonly used in cellular communications, based on a plurality of single-channel RF power amplifiers 30, 32 , 34 Signals are generated for transmission in a plurality of frequency channels by respective transceivers 22, 24 , 26
  • the typical bandwidth of a single channel can be anywhere from 10 kHz to 1 25 MHz
  • the signal in each channel is amplified by the respective amplifier 30, 32 , 34, so that frequency spreading and intermodulation between channels are avoided
  • the amplified signals are tvpically combined by a cavity combiner 36 and transmitted via an antenna 38
  • the use of single-channel power amplifiers 30, 32 are
  • the portion of the circuit that generates the error signal is known as the signal-cancellation loop.
  • the error signal is then amplified, phase-adjusted and subtracted from the amplifier output to give a corrected RF output with reduced distortion effects.
  • This portion of the circuit is known as the error-cancellation loop.
  • the amplitude and phase adjustments in the signal- and error-cancellation loops are set by injecting a "pilot tone” and then varying the amplitude and phase until a desired output is obtained.
  • the adjustments made in this manner are inherently narrowband and give optimal amplifier performance only at a certain frequency.
  • U.S. Patent 4,412,185 which is incorporated herein by reference, describes a feedforward amplifier using such an approach.
  • a reference signal is injected into a main amplifying element in the feedforward amplifier so that it appears at an output terminal of the amplifier as through it were an amplifier-induced distortion.
  • the characteristics of the amplifier are adaptively modified to eliminate the reference signal from the output signal.
  • a different approach that has been proposed to improve linearity of feedforward amplifiers is non-linear predistortion of the amplifier input, to compensate for the non-linear disto ⁇ ion introduced by the power amplifier itself. Because the amplifier characteristics change over time and in response to changing operating conditions, the predistortion is often applied adaptively. Typically, feedback from the amplifier output is used to control predistortion parameters.
  • Fig. 2 is a block diagram illustrating a multi-channel feedforward amplifier 40, as is known in the art, using pre-adjustment of the input signals to reduce distortion.
  • Amplifier 40 is described in U.S. Patent 5, 157,345, which is incorporated herein by reference.
  • Signals from multiple transceivers 22, 24..., 26 are fed to an input phase adjustment block 44 and gain adjustment block 48, which include a separate, respective phase adjuster 46 and variable gain component 50 for gain adjustment of each channel.
  • the adjusted inputs are then summed together after adjustment by an adder 52 and are fed to a wideband power amplifier 54.
  • a portion of the input at each channel is split off by an input splitter 42. and these portions are summed by an adder 64.
  • the summed input signals are subtracted at an adder 70 from a portion of the output of power amplifier 54, which is split off by a directional coupler 56, thus generating the feedforward error signal.
  • the error signal is delayed by a delay 72, adjusted in phase and gain by phase adjuster 74 and variable gain component 76, and amplified by an amplifier 78
  • the output of power amplifier 54 is combined with the error signal by a directional coupler 82 to generate the amplified and corrected output signal.
  • phase adjusters 46 and 74 and variable gain components 50 and 76 is adaptively controlled by a respective feedback network to suppress the distortion interference in the output signal.
  • a single feedback network 86 receives sampled error signals from a directional coupler 80 and sampled output signals from a directional coupler 84 and generates control signals accordingly.
  • a separate feedback network 88, 90 .. , 92 is required for each of the transceiver channels.
  • feedforward amplifier 40 attempts to overcome the limitations of narrowband feedforward amplifiers by correcting each of the input signals separately, effectively providing a separate signal cancellation loop for each input channel A similar approach is described in U S Patent 4,560.945
  • a multi-carrier feedforward amplifier comprises a main radio frequency (RF) power amplifier, coupled to signal cancellation and error cancellation loops
  • a digital correction block in the signal cancellation loop receives signals from one or more transceivers for input to the power amplifier and digitally equalizes the signals to correct for gain and phase distortions introduced by the power amplifier, as well as other elements of the feedforward amplifier
  • the digital correction block is controlled adaptively using feedback signals received from the signal and/or error cancellation loops so that the equalization compensates in real time for amplitude and phase distortions in a transfer function of the feedforward amplifier
  • the feedforward amplifier provides highlv-linear amplification over a broad frequency band, with strong suppression of intermodulation products
  • RF input signals on a plurality of carrier frequencies typically originating from a plurality of respective transceivers are summed and input to the feedforward amplifier
  • the digital correction block receives and digitallv equalizes the RF signals before they are input to the power amplifier
  • the RF signals are down-converted to an intermediate frequency and are then A/D converted to a stream of digital samples
  • a finite-impulse-response (FIR) filter convolves the stream of samples with a vector of coefficients calculated so as to equalize the amplitude and phase distortions in the transfer function of the main power amplifier, as well as by other components in the signal cancellation loop
  • the feedback signals received from the signal and/or error cancellation loops are preferably down-converted and digitized for use by a digital signal processor (DSP) in adaptively calculating the filter coefficients After filtering, the signals are converted back to analog form and up-converted to the RF frequency for input to the power amplifier.
  • DSP digital signal processor
  • the feedforward amplifier of the present invention achieves superior wideband performance to feedforward amplifiers known in the art.
  • a single digital correction block effectively corrects for signal distortions over the entire operating band of the amplifier.
  • the feedforward amplifier of the present invention can be substituted in base station transmitters in place of the multiple single-channel RF amplifiers that are currently in common use, without requiring substantial changes other base station components.
  • a super-linear feedforward amplifier for amplifying radio-frequency input signals produced in one or more frequency channels over an input band, including: a radio-frequency power amplifier, which amplifies the signals; a signal cancellation circuit loop, which generates an error signal responsive to distortion products in the amplified signals; a digital correction block, which digitally equalizes the input signals responsive to a transfer function of the amplifier, whereby the input signals are substantially canceled out of the error signal over the entire input band; and an error cancellation circuit loop, which subtracts the error signal from the amplified signals to generate a linearized output signal.
  • the digital correction block equalizes an amplitude and phase response of the amplifier over substantially the entire input band and corrects linear distortions in the amplified signals.
  • the input signals include a plurality of signals in different, respective channels, which are summed together for input to the amplifier.
  • the digital correction block receives feedback signals sampled at one or more points in at least one of the signal and error cancellation loops and processes the feedback signals to determine characteristics of the transfer function.
  • the digital correction block includes a digital signal processor, which calculates a correlation of the feedback signals and determines the characteristics of the transfer function based on the correlation.
  • the digital signal processor finds eigenvalues and eigenvectors of a matrix based on the correlation, and applies the eigenvalues and eigenvectors to generate processing coefficients for use in equalizing the signals.
  • the digital correction block includes a receiver for receiving and digitizing the feedback signals, the receiver having a transfer function, and wherein the digital signal processor calibrates the receiver responsive to the transfer function thereof before receiving and processing the feedback signals.
  • the feedback signals include samples of the amplified signal output by the power amplifier and of a delayed input signal in the signal cancellation loop, and the digital correction block adaptively controls operation of the amplifier substantially without passing a pilot signal therethrough.
  • the amplifier includes a down-converter, which converts the input signals from the radio frequency to an intermediate frequency for input to the digital correction block, and an up-converter, which converts the equalized signals to the radio frequency for amplification thereof.
  • the equalized signals from the up-converter are input to the power amplifier.
  • a super-linear feedforward amplifier for amplifying radio-frequency input signals produced in one or more frequency channels over an input band, including: a radio-frequency power amplifier, which amplifies the signals; a signal cancellation circuit loop, which generates an error signal responsive to distortion products in the amplified signals; a time-domain correction block, which processes the input signals in the time domain, responsive to a transfer function of the amplifier, such that the input signals are substantially canceled out of the error signal over the entire input band; and an error cancellation circuit loop, which subtracts the error signal from the amplified signals to generate a linearized output signal.
  • the time-domain correction block equalizes the input signals responsive to the transfer function.
  • the correction block includes: an analog-to-digital converter, which digitizes the input signals to generate a stream of digital samples; a finite impulse response filter, which convolves the digital samples with a vector of coefficients determined responsive to the transfer function, and a digital-to-analog converter, which converts the equalized signals to analog form for output from the block
  • an analog-to-digital converter which digitizes the input signals to generate a stream of digital samples
  • a finite impulse response filter which convolves the digital samples with a vector of coefficients determined responsive to the transfer function
  • a digital-to-analog converter which converts the equalized signals to analog form for output from the block
  • determining a characte ⁇ stic of the transfer function of the amplifier and the associated circuitry equalizing the signals responsive to the characte ⁇ stic, amplifying the signals using the amplifier, generating an error signal responsive to distortion in the amplified signals, and subtracting the error signal from the amplified signals to generate a linearized output signal in which the distortion is reduced
  • Preferablv equalizing the signals includes equalizing an amplitude and phase response of the amplifier over substantially the entire input band, and processing the input signals to compensate for linear distortions in the amplified signals introduced by the power amplifier and associated circuitrv
  • amplifying the signals includes amplifying the processed signals
  • the method includes summing a plurality of signals in different, respective channels for input to the amplifier
  • Preferablv determining the characte ⁇ stic includes receiving and processing feedback signals sampled at one or more points in circuitry associated with the amplifier Most preferably, processing the feedback signals includes calculating a co ⁇ elation of the feedback signals and determining the characteristic of the transfer function based on the correlation
  • Preferablv processing the feedback signals includes finding eigenvalues and eigenvectors of a matrix based on a vector indicative of the correlation and generating processing coefficients for use in equalizing the signals based on the eigenvalues and eigenvectors Further preferablv equalizing the signals includes convolving the signals with a vector of the processing coefficients Preferably, generating the coefficients includes calculating coefficients dependent on the eigenvalues, wherein calculating the coefficients includes eliminating eigenvalues that are below a given threshold
  • calculating the correlation includes determimng an initial estimate of the correlation based on feedback signals received du ⁇ ng a first time slot, receiving additional feedback signals du ⁇ ng a second, subsequent time slot, and iteratively updating the initial estimate of the correlation based on the additional feedback signals
  • calculating the correlation includes de ⁇ ving a signal parameter from the feedback signals and, responsive to a substantial change in the parameter, determining a new estimate of the correlation vector instead of iteratively updating the initial estimate
  • receiving the feedback signals includes using signal receivers having an amplitude and phase transfer function
  • processing the signals includes calibrating the receivers to determine calibration coefficients responsive to the transfer function thereof and applying the calibration coefficients to the signals
  • receiving the feedback signals includes sampling the amplified signals and sampling the input signals following a delay thereof
  • the method includes down-converting the input signals from the radio frequency to an intermediate frequency for equalization thereof, and up-converting the equalized signals to the radio frequency
  • amplifying the signals including amplifying the equalized signals following up-conversion thereof
  • equalizing the signals includes processing the input signals in the time domain
  • equalizing the signals includes digitizing the input signals to generate a stream of digital samples, processing the digital samples responsive to the transfer function, and convening the equalized signals to analog form for output from the block
  • processing the digital samples comprises convolving the digital samples with a vector of coefficients determined responsive to the transfer function
  • generating the error signal includes controlling the circuitry substantially without passing a pilot signal therethrough
  • Fig 1 is a schematic block diagram illustrating a base station transmitter, as is known in the art
  • Fig 2 is a schematic block diagram that illustrates a feedforward amplifier, as is known
  • Fig 3 is a schematic block diagram illustrating a base station transmitter including a feedforward amplifier with digital equalization, in accordance with a preferred embodiment of the present invention
  • Fig 4 is a schematic block diagram showing details of the circuitry of the feedforward amplifier of Fig 3, in accordance with a preferred embodiment of the present invention.
  • Fig 5 is a schematic block diagram showing details of digital equalization circuitry in the feedforward amplifier of Fig 3, in accordance with a preferred embodiment of the present invention
  • Fig 6 is a flow chart that schematically illustrates a method for determining equalization coefficients, for use in the equalization circuitry of Fig 5, in accordance with a preferred embodiment of the present invention.
  • Fig 7 is a flow chart that schematically illustrates a method for calibrating control signal inputs in the feedforward amplifier of Figs 3-5, in accordance with a preferred embodiment of the present invention
  • Fig 3 is a simplified block diagram that schematically illustrates a base station transmitter 98, including a wideband feedforward amplifier 100, in accordance with a preferred embodiment of the present invention
  • RF inputs from multiple transceivers 22, 24 , 26 are summed together by a combiner 102 to generate a multi-earner input to a signal cancellation loop 103 of the amplifier
  • the RF inputs are in a cellular band in the 800-900 MHz range and cover a total bandwidth of about 25 MHz, but those skilled in the art will appreciate that amplifier 100 can easily be adapted for other frequency bands and bandwidths
  • Loop 103 comprises a digital equalization circuit 104 in an upper arm of the loop and a delay circuit 106 in a lower arm thereof.
  • the equalized signals in the upper arm are input to power amplifier 108.
  • a loop subtractor 110 subtracts the delayed lower-arm signal from the equalized and amplified upper-arm signal to generate an enor signal for input to an enor cancellation loop 105 of amplifier 100.
  • the enor signal contains substantially only distortion components, resulting from inter-modulation products of the carriers and other spurious signals.
  • the effect of equalization circuit 104 is such that the desired signal portions (i.e., the portions not due to distortion) of the upper- and lower-arm signals that are input to subtractor 110 are substantially equal.
  • Loop 105 comprises an amplitude and phase adjustment circuit 114, which adjusts the amplitude and phase of the enor signal, as well as the delay of the enor signal relative to the amplified output signal from power amplifier 108.
  • the output of the power amplifier is delayed by a delay circuit 112.
  • the error signal from circuit 114 is then amplified by an error amplifier 115 and subtracted from the power amplifier output by a directional coupler 116 to generate the linearized RF output for transmission via antenna 38.
  • the output may be coupled directly to the antenna, or via a duplexer, as is known in the art.
  • a control circuit 118 preferably based on a digital signal processor (DSP), as described further hereinbelow, samples the amplified RF signal at the output of power amplifier 108 and the delayed input signal at the output of delay circuit 106. Based on the sampled signals, control circuit 1 18 calculates and outputs equalization coefficients for use in equalization circuit 104.
  • the coefficients correspond to a vector with which the signals are convolved, or filtered, in circuit 104 so as to pre-distort the input to power amplifier 108, thereby compensating for linear distortion introduced by the power amplifier and other elements in the circuitrv- of amplifier 100.
  • signal cancellation loop 103 achieves superior cancellation of the signal carriers over substantially the entire transmission bandwidth.
  • control circuit 1 18 performs other functions and controls other elements of amplifier 100 in both signal cancellation loop 103 and error cancellation loop 105. Further preferably, circuit 118 receives and operates on other inputs from different points in the circuitry of amplifier 100, such as points in the enor cancellation loop.
  • Fig. 4 is a schematic block diagram showing details of feedforward amplifier 100, in accordance with a prefened embodiment of the present invention.
  • Amplifier 100 preferably comprises three major functional blocks: an RF processing block 120, an RF power block 122 and a digital processing block 124. It will be understood that the amplifier also includes auxiliary circuitry, such as power supplies, microcontroller circuitry, clock and timing circuits and control lines, preferably linked to digital block 124, which are not shown in the figure for the sake of clarity, but whose design and use will be clear to those skilled in the art.
  • Equalization circuit 104 comprises a down-converter 128, which converts RF signals that are input from combiner 102 to an intermediate frequency (IF) of about 40 MHz.
  • IF intermediate frequency
  • the level of the input signals is preferably adjusted by a variable attenuator 126 so as to ensure that the signal is properly scaled for sampling.
  • the IF signals are input to a digital correction circuit 130, which performs the equalization, together with filtering, interpolation and digital up-conversion, as described further hereinbelow.
  • An up-converter 132 converts the conected IF output signals from circuit 130 back to the original RF input frequency and passes the equalized RF signals to power amplifier 108.
  • delay circuit 106 comprises a delay line 136, along with an input amplifier 134 and an output amplifier 140.
  • a variable attenuator 138 adjusts the signal amplitude, under the control of DSP and logic circuits 1 18.
  • Delay line 136 preferably comprises a surface acoustic wave (SAW) delay line, as is known in the art, such as those produced by Andersen Labs of Bloomfield, Connecticut, or by Sawtek, Inc., of Orlando, Florida. Delay line 136 matches the absolute signal delays of the upper and lower arms.
  • SAW surface acoustic wave
  • Attenuators 138 and 144 are set so as to provide full cancellation of the input signal components from the upper and lower arms of loop 103 at subtractor 1 10, leaving substantially only the enor component to be input to amplitude/phase adjustment circuit 114 in enor cancellation loop 105.
  • Circuit 114 comprises a variable vector attenuator 148 and a delay line 150, which optionally comprises a variable delay line, both preferably controlled by DSP and logic.
  • the vector attenuator preferably comprises an integrated device, such as a NM-A01S device, produced by KD I/Triangle Corp., of Whippany, New Jersey, or a 81 OVA device, produced by Micro-Precision Technologies, Inc., of Salem, New Hampshire. Alternatively, it may be constructed using discrete components, as is well known to those skilled in the art.
  • the vector attenuator controls the amplitude and phase of the RF error signal which passes through it, and is controlled by the DSP using a pair of digital to analog converters (not shown).
  • An error amplifier 154 amplifies the error signal, which is then passed via an isolator 156 to directional coupler 1 16.
  • the RF output of RF power block 122 to antenna 38 thus comprises the multi-channel signal at the plurality of canier frequencies, substantially without inter-channel interference.
  • the output is fed to the antenna via an output isolator 164, which isolates main amplifier 108 and other RF circuitry from power reflected back from the antenna or from other external devices.
  • the output isolator preferably includes a reverse power indication (illustrated by the arrow coming out of the isolator down and leftwards), which is used to generate an alarm in the case of excessive reverse power.
  • DSP and logic circuits 118 set various circuit parameters and coefficients in amplifier 100, preferably including:
  • the DSP alternates among the different control tasks, so as to alternately set parameters in signal cancellation loop 103 and error cancellation loop 105, for example
  • the DSP receives, digitizes and processes signals sampled from various points in the circuitry of amplifier 100, as noted above.
  • Splitters 146 and 142 respectively provide po ⁇ ions of the output signals from power amplifier 108 and of delay circuit 106, which signals are used by the DSP primarily in setting the digital correction coefficients and other parameters in loop 103.
  • a splitter 152 and a directional coupler 158 respectively provide portions of the adjusted enor signal from circuit 114 and of the amplified signal for output to antenna 38, for use mainly in controlling loop 105.
  • the signal portions are input to a multiplexer 160, which preferably selects two of the signals for down- conversion to IF by first and second down-converters 162.
  • the selected IF signals are received and digitized by DSP and logic circuits 118, preferably at a sampling frequency in the range of 50-70 MHz, and are then used by the DSP in calculating the parameters and coefficients mentioned above.
  • Fig. 5 is a schematic block diagram showing details of digital conection circuit 130, in accordance with a prefened embodiment of the present invention.
  • IF signals from down- converter 128 are digitized, preferably by a high-speed 12-bit A/D converter 170, such as a CLC5956, produced by National Semiconductor Corp. of Arlington, Texas, or an AD6640 converter, produced by Analog Devices.
  • A/D converter 170 preferably operates at the same basic sampling clock rate as is used in the digitization of the feedback signals described above.
  • the output of the A/D converter is held by a 12-bit latch 172 and is then input via a bus- connection switch 174 to a digital equalizer 176.
  • switch 174 is normally set to convey digitized signals from the latch to the equalizer, it can be shifted to enable DSP 118 to receive samples of the input to equalizer 176 from A/D converter 170 or to inject test signals into the equalizer, typically for calibration and testing of amplifier 100.
  • Equalizer 176 preferably comprises two finite impulse response (FIR) filters 178, most preferably GC201 1 filters produced by Graychip, Inc., Palo Alto, California, each comprising a 32-tap pipeline.
  • FIR finite impulse response
  • a sequence of input samples, at the basic sampling rate, is input to the filters.
  • one of the samples is multiplied by a respective coefficient, loaded into equalizer 176 by DSP 1 18.
  • the coefficients are calculated and set by the DSP so as to correct for linear distortion in the circuits of amplifier 100.
  • a preferred method for calculating the coefficients is described further hereinbelow.
  • a variable-length FIFO 180 which preferably holds up to 64 samples.
  • the length of the FIFO is preset by DSP 118 so that the upper and lower arms of loop 103 have precisely equal throughput delays.
  • Digital upconversion and interpolation are performed using an input stage 182 and a bus switch 188, to provide a high sample-rate digital signal for conversion to analog form. This process effectively increases the frequency of the digital signals before they are input to a D/A converter (DAC) 190, preferably an AD9754 converter, produced by Analog Devices, returns the signals to IF analog form for input to up-converter 132.
  • DAC D/A converter
  • Input stage 182 comprises a pair of multipliers 184, which multiply the input samples alternately by +1 and -1, switching between the alternate multiplicands at the above- mentioned sample rate.
  • the two multipliers do not switch simultaneously between the positive and negative values, but rather with a relative 90° phase shift therebetween, so that the stream of pairs of samples has the form of a stream of complex values.
  • the pairs of samples are input to a pair of low-pass filters 186, preferably using Graychip, Inc., GC2011 devices, as described hereinabove, having 32 taps each.
  • the filter coefficients are loaded by DSP 118.
  • the combined pair of filters realize a 64 tap interpolation filter, at a sampling rate that is double the basic rate.
  • Bus switch 188 preferably comprises a FPGA, most preferably of the type produced by
  • Switch 188 receives inputs from low-pass filters
  • Digital conection block 130 thus has an effective output sample rate which is twice the input sample rate from A/D converter 170. Since the full bandwidth of the RF signals input via combiner 102 is typically 25 MHz, as noted above, there is no danger of loss of information in the digital equalization process.
  • Fig. 6 is a flow chart that schematically illustrates a method for calculating the coefficients to be loaded into FIRs 178 by DSP 118, in accordance with a preferred embodiment of the present invention.
  • the coefficients are determined so as to provide the best linear estimate of the transfer function between the signals in the upper and lower arms of signal cancellation loop 103, as provided by splitters 146 and 142, respectively.
  • the calculation is based on vectors f and g , which are defined respectively as the auto-conelation of the upper- arm signal (from splitter 146) and the cross-correlation of the upper- and lower-arm signals (from splitters 146 and 142).
  • the auto- and cross-correlations are calculated to order L, wherein L is the total number of FIR taps in equalizer 176.
  • L is the total number of FIR taps in equalizer 176.
  • vectors of samples are shifted by up to ⁇ (L-l) samples relative to one another and are then multiplied entry-by- entrv and summed to get each of the entries in the auto- and cross-correlation vectors.
  • the correlation calculations are preferably repeated over an interval of several thousand signal samples
  • Vector f is used to generate a matrix R, defined as the estimated Toeplitz autocorrelation matrix of the upper-arm signal R is a symmetric Toeplitz matrix, whose first row and column are the elements of vector r , ⁇ , ri , r2,
  • a Toeplitz matrix is completely defined by its first row and column, since by definition the elements along any of its diagonals are equal
  • the eigenvalues and corresponding eigenvectors of matrix R are calculated
  • Methods of determining the eigenvalues and eigenvectors of a matrix are well known in the art of linear algebra
  • each eigenvalue ⁇ t is assigned an inverse value ⁇ ;
  • T is set to a value of approximately 50, which is equivalent to eliminating eigenvalues that are at least 50 dB down from the maximum.
  • a new diagonal matrix is defined:
  • ⁇ diag( ⁇ Q, ⁇ , ..., ⁇ L_ ⁇ )
  • the vector of FIR coefficients for equalizer 176 is given by:
  • O is a matrix whose columns are the eigenvectors of matrix R.
  • Calculation of vectors r and g can be performed in a batch process, from time to time, but is preferably updated iteratively while amplifier 100 is operating.
  • the first step in iterative determination of the equalization coefficients is to calculate an initial estimate of the vectors.
  • a certain time slot duration is defined, and the coefficients are recalculated after each time slot using iterated values of r and g If the nature of the input signals has not changed substantially since the preceding time slot, the iterated values of the vectors are calculated by averaging in the correlations of the signals in the cunent time slot with the old values. If there has been a substantial change, however, a new initial estimate of r and g is made, and the coefficients are recalculated
  • a preferred method for determining whether the signals have changed substantially is for DSP 1 18 to calculate an average power of a difference taken between the upper- and lower- arm signals (from splitters 146 and 142) If the power is above a predetermined threshold, a new initial calculation of r and g is made
  • Fig 7 is a flow chart that schematically illustrates a method for calibrating the upper- and lower-arm inputs to DSP 118, in accordance with a prefened embodiment of the present invention Such calibration is necessary if the DSP is to accurately generate optimal coefficients for equalizer 176
  • multiplexer 160 is switched so that both down-converters 162 receive a common signal, preferably from splitter 146 Bus-connection switch 174 is positioned to enable a digital test signal to be injected into equalizer 176
  • the test signal is then received at the DSP and logic circuits via both down-converters simultaneously Therefore, any differences in the received signals must be due to differences in the respective transfer functions
  • equalizer calibration coefficients are determined, corresponding to the difference in the transfer functions
  • the signals received by DSP 118 from splitter 142 which are passed to the DSP via the second down-converter 162
  • the filtered signal values are then used in calculating g.
  • a novel method of signal equalization has been disclosed for use in lineanzation of RF amplifier 100
  • Fig 5 illustrates a certain design of digital correction circuit 130, and particularly of equalizer 176
  • the methods described hereinabove may also be applied to find equalization coefficients for use in different, digital or analog, hardware configurations Similarlv, DSP 1 18 may calculate equalization coefficients using frequency-domain analysis of the signals, rather than the correlation-based method described hereinabove
  • DSP 1 18 may calculate equalization coefficients using frequency-domain analysis of the signals, rather than the correlation-based method described hereinabove
  • equalizer 176 processes the signals in the time domain
  • digital frequency-domain equalization could similarly be used
  • digital correction block 130 and associated down-converter 128 and up-converter 132 process the signals in the upper arm of loop 103, for input to power amplifier 108, it
  • down-converter 128, digital conection block 130 and up- converter 132 may be placed in the lower arm of signal cancellation loop 103, so as to pre- distort the cancellation signal before subtraction from the amplified signal at subtractor 110.
  • Similar equalization schemes may be employed to perform equalization of enor-cancellation loop 105 of the amplifier.
  • digital equalization of the signals may take place in baseband processing circuitry (not shown in the figures), so as to generate a suitably equalized baseband signal.
  • This baseband signal is then converted to analog form and up-converted to RF for input to either the upper or lower arm of signal cancellation loop 103 (while the other arm receives the input signal without equalization). All such alternative embodiments are considered to be within the scope of the present invention.
  • the following listing comprises FORTRAN source code for carrying out the TRED2 and TQL2 algorithms, used in tri-diagonalizing and finding the eigenvalues and eigenvectors of the Toeplitz autoconelation matrix R, as described hereinabove. These algorithms, which are in the public domain, are incorporated herein in their entirety.
  • the listing and notes on the source code are described by Smith, et al., in “Matrix Eigensystem Routines - EISPACK Guide. " vol 6 in Lecture Notes m Computer Science, second edition, Springer- Verlag (1976), which is incorporated herein by reference.
  • this subroutine is a translation of the algol c procedure tred2, c num math 11, 181-195(1968) by martin, reinsch, c and Wilkinson c handbook for auto comp , vol n-linear algebra, c 212-226(1971)
  • c c this subroutine reduces a real symmet ⁇ c mat ⁇ x to a c symmetric t ⁇ diagonal mat ⁇ x using and accumulating c orthogonal similanty transformations c c on input c c nm must be set to the row dimension of c two-dimensional c array parameters as declared in the calling c program c
  • c c e contains the subdiagonal elements of the c tridiagonal c matrix in its last n-1 positions e(l) is set c to zero
  • c c z contains the orthogonal transformation matrix c produced in the reduction.
  • c c a and z may coincide if distinct, a is c unaltered c c questions and comments should be directed to burton c s garbow, c mathematics and computer science div, argonne c national laboratory c c this version dated august 1983
  • c c n is the order of the matrix.
  • c d contains the diagonal elements of the input c mat ⁇ x
  • c c e contains the subdiagonal elements of the mput c matnx c in its last n-1 positions e(l) is arbitrary
  • c c z contains the transformation mat ⁇ x produced in c the c reduction by tred2, if performed if the c eigenvectors c of the tridiagonal mat ⁇ x are desired, z must c contain c the identity mat ⁇ x c c on output c c d contains the eigenvalues in ascending order c error exit is made, the eigenvalues are c conect but c unordered for indices 1,2, , ⁇ en-l c c e has been destroyed
  • c c z contains orthonormal eigenvectors of the c symmet ⁇ c c tridiagonal (or full) mat ⁇ x if an enor

Abstract

L'invention concerne un amplificateur ultra-linéaire à correction précursive (100), qui amplifie des signaux d'entrée de fréquence radioélectrique émis dans une ou plusieurs voies de fréquence d'une bande d'entrée. L'appareil comprend un amplificateur de puissance de fréquence radioélectrique (108) qui amplifie les signaux. Une boucle de circuit d'annulation de signaux (103) génère un signal d'erreur en réaction à une distorsion dans les signaux amplifiés. Un bloc de correction numérique (104) égalise numériquement les signaux d'entrée en réaction à une fonction de transfert de l'amplificateur et les signaux d'entrée sont sensiblement éliminés du signal d'erreur dans la totalité de la bande d'entrée. Une boucle de circuit d'annulation d'erreurs (105) soustrait le signal d'erreur des signaux amplifiés afin de générer un signal de sortie linéarisé.
PCT/IL2000/000072 2000-02-03 2000-02-03 Amplificateur de puissance ultra-lineaire a ondes porteuses multiples WO2001058026A2 (fr)

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AU2000223178A AU2000223178A1 (en) 2000-02-03 2000-02-03 Super-linear multi-carrier power amplifier

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2992502A1 (fr) * 2012-06-26 2013-12-27 Ecam Rennes Louis De Broglie Procede et dispositif de linearisation d'un amplificateur de puissance, programme d'ordinateur correspondant.
US9094067B2 (en) 2012-09-12 2015-07-28 Mediatek Singapore Pte. Ltd. Method and apparatus for calibrating an envelope tracking system
GB2624195A (en) * 2022-11-09 2024-05-15 Qinetiq Ltd Signal processor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334946A (en) * 1990-04-25 1994-08-02 British Technology Group Limited Apparatus and method for reducing distortion in amplification
JP2746107B2 (ja) * 1994-03-31 1998-04-28 日本電気株式会社 フィードフォワード増幅器
US5929704A (en) * 1998-02-20 1999-07-27 Spectrian Control of RF error extraction using auto-calibrating RF correlator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2992502A1 (fr) * 2012-06-26 2013-12-27 Ecam Rennes Louis De Broglie Procede et dispositif de linearisation d'un amplificateur de puissance, programme d'ordinateur correspondant.
US9094067B2 (en) 2012-09-12 2015-07-28 Mediatek Singapore Pte. Ltd. Method and apparatus for calibrating an envelope tracking system
US9118366B2 (en) 2012-09-12 2015-08-25 Mediatek Singapore Pte. Ltd. Method and apparatus for calibrating an envelope tracking system
GB2624195A (en) * 2022-11-09 2024-05-15 Qinetiq Ltd Signal processor

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