WO2001054197A1 - Dispositif de protection contre les surtensions de courant inverse par repartition - Google Patents

Dispositif de protection contre les surtensions de courant inverse par repartition Download PDF

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Publication number
WO2001054197A1
WO2001054197A1 PCT/US2000/022206 US0022206W WO0154197A1 WO 2001054197 A1 WO2001054197 A1 WO 2001054197A1 US 0022206 W US0022206 W US 0022206W WO 0154197 A1 WO0154197 A1 WO 0154197A1
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WO
WIPO (PCT)
Prior art keywords
conductive
region
layer
type
surge guard
Prior art date
Application number
PCT/US2000/022206
Other languages
English (en)
Inventor
Walter R. Buchanan
Roman J. Hamerski
Wayne A. Smith
Original Assignee
Fabtech, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP00102771A external-priority patent/EP1119055A1/fr
Application filed by Fabtech, Inc. filed Critical Fabtech, Inc.
Priority to AU2000267698A priority Critical patent/AU2000267698A1/en
Publication of WO2001054197A1 publication Critical patent/WO2001054197A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Definitions

  • This invention relates to electrical components and, more particularly, to semiconductor devices, such as Schottky diodes, which include surge guard protection material to inhibit damage from electrostatic discharge.
  • two layers of preferably N-type conductive material are provided with a rectifying barrier metal.
  • the two layers include an epitaxial layer grown on a highly doped, single crystal semiconductor substrate layer.
  • the rectifying metal is deposited on the epitaxial layer to form a semiconductor junction which provides the rectifying property of conducting current in one direction when the barrier metal is under positive bias and blocking current flow when the barrier metal is under the opposite bias.
  • the dominant type of current across the barrier is the thermionic emission current.
  • a back, metal contact is formed on the N + substrate layer side of the diode.
  • the function of the metal contact is to conduct current with minimal resistance in either direction, that is, under any bias applied to the diode. This is primarily achieved by the high doping level of the N + -type substrate, which makes field emission or tunneling a prevalent mechanism of the current flow through the metal contact.
  • a perimeter ring of P + -type material is diffused into the "top" N " -type conductive layer around the perimeter termination of the barrier metal.
  • the P + - type ring minimizes reverse current leakage and provides a reverse current path for reverse current surge to protect the barrier metal and N-type conductive layers from exposure to critical electrical fields generated by transient threats and during electrical testing.
  • the avalanche breakdown voltage is lowest at the P/N junction formed by the P-type ring, so that when ESD occurs sufficient to exceed the avalanche breakdown voltage at the P N junction, the P-type ring directs the reverse flow of current through the P/N junction and away from the central area of the barrier metal.
  • the protection provided by the P-type ring is effective until the reverse voltage drop across the P/N junction rises to the breakdown voltage of the Schottky diode or the reverse current causes localized heating of the barrier metal adjacent the P-type ring; it is not definitively known which affect is controlling. When the reverse current reaches a sufficiently high level, the barrier metal and "top" N-type layer are melted rendering the diode inoperable for its intended function.
  • a variety of guard ring features are optimized to find the best combination of features and enhance reverse surge capability.
  • the width and/or the depth of the ring can be increased, the concentration of dopant in the ring can be increased, and/or the thickness and resistivity of the "top" N-type layer can be reduced. While optimization of these features achieves incremental improvements in reverse surge capability, continuous progress in the electronics area and higher consumer expectations of product reliability and performance have prompted higher reverse surge performance standards, which are nearly beyond the incremental improvements previously achieved. Further, modifying the diode in these ways can undesirably degrade the operational parameters of the diode. BRIEF SUMMARY OF THE INVENTION
  • the electrical component broadly includes a conductive pad with a primary conductive area edge.
  • a first region of surge guard material is positioned adjacent the primary conductive area perimeter edge, and a second region of surge guard material is positioned adjacent the conductive pad and spaced from the primary conductive area edge.
  • the second region has first and second sides, which are positioned within the primary conductive area edge.
  • the first region is a substantially continuous perimeter loop of P + -type material
  • the second region is a grid of perpendicular P + -type material lines extending between opposite sides of the perimeter loop.
  • the grid forms a plurality of substantially rectangular, preferably square, inner loops of substantially the same size extending within the perimeter loop, and some of the inner loops overlap in part with the perimeter loop.
  • the distributed reverse surge guard is used in a diode having first and second conductive layers of unique conductive types with the conductive pad in electrical communication with one of the conductive layers. At least a single region of surge guard material including a first side and a second side is positioned adjacent the conductive pad with each of the first and second sides within the perimeter of the conductive area.
  • the diode is constructed by forming a monocrystalline substrate layer of semiconductor material having a first conductive type and depositing an epitaxial layer on the substrate.
  • the epitaxial layer having a second conductive type.
  • a first region of surge guard material is formed on an outer surface of a selected one of the substrate layer and the epitaxial layer, and the first region has extremities and an opposite conductive type.
  • a second region of surge guard material is also formed on the outer surface of the selected layer. The second region is also of the opposite conductive type and is positioned within the extremities of the first region.
  • a conductive pad is also placed over the outer surface of the selected layer
  • the conductive pad on the outer surface of the selected layer covers at least a portion of the second region and is deposited on the outer surface after the first and second regions are formed by diffusing a P-type dopant into the epitaxial layer.
  • the conductive pad covers all of the second region and at least part of the first region. In constructing the diode the first and second regions are formed substantially simultaneously, and the conductive pad is deposited after the first and second regions are formed.
  • an object of the present invention to provide an improved electrical component with a distributed reverse surge guard providing increased protection from ESD and other transient threats. It is a further object of the present invention to provide an improved method of constructing an electrical component with a distributed reverse surge guard providing increased protection from ESD and other transient threats.
  • Fig. 1 is an enlarged, schematic top view of a diode with a top layer removed for illustration and having a distributed reverse surge guard according to the present invention
  • Fig. 2 is an enlarged, schematic cross-sectional view of the diode of Fig.1 taken along line 2-2 in Fig. 1.
  • Figs. 1 and 2 show a Schottky diode
  • the diode 20 having a distributed surge guard 22 constructed in accordance with a preferred embodiment of the present invention.
  • the diode 20 broadly includes first and second conductive layers 24, 26 and a conductive pad 28.
  • the surge guard 22 is formed in the first conductive layer 24 and operates to protect the conductive pad 28 and conductive layers 24,26 from damage due to transient threats electrostatic discharge (ESD) to electrical testing .
  • ESD electrostatic discharge
  • the first conductive layer 24 of the diode 20 has a first conductive type, which is preferably N " type.
  • the first and second conductive type are actually the same conductive type with the distinction being the dopant concentration.
  • the first layer is formed by depositing an epitaxial layer on the second substrate layer, which is formed by growing a monocrystalline ingot.
  • the substrate layer is heavily doped, so that it has a low resistivity to conductivity current.
  • the epitaxial layer has a lower dopant concentration, so that it has a high resistivity.
  • the first layer is preferably formed as an epitaxial layer using the second layer 26 as a substrate.
  • the second layer 26 has a second conductive type, which is preferably N + type.
  • the second layer is preferably a monocrystalline semiconductor material.
  • the first and second layers are in electrical communication and are preferably juxtaposed and in direct physical contact at an N7N + junction 30.
  • N-type material is preferred
  • P-type material can also be used for the first and second layers.
  • the particular dopants used to achieve the conductivity regions of the present invention will not be described particularly, it should be understood that boron can be used a P-type dopant while phosphorous, arsenic, and antimony can be used as N-type dopants for silicon.
  • the semiconductor material can be silicon, germanium, or any compound semiconductor material such as gallium arsenide with appropriate changes to the dopant material.
  • the conductive pad 28 is preferably a rectifying metallic pad in electrical communication with the first conductive layer and opposite the second conductive layer.
  • the pad 28 has a centrally located, primary conductive area 32.
  • the primary pad area 32 is in direct physical contact with the first conductive layer to form a Schottky barrier.
  • the primary pad area terminates at primary conductive area edge 34 located at an inner step of the pad.
  • the primary edge 34 extends around the perimeter of the pad 28 and is surrounded by an edge margin 36, which is separated from the first conductive layer 24 by a passication/dielectric layer, which preferably comprises an oxide layer 38.
  • An electrical contact 40 is juxtaposed the second conductive layer 26 opposite the first layer 24 and the pad 28.
  • the pad 28 can also operates as an electrical contact for the opposite side of the diode 20, but it is preferred that an additional contact material (not shown) is deposited over the pad 28.
  • the surge guard 22 includes a first, outer region 42 of surge guard material adjacent the primary conductive edge 34 and a second region 44 of surge guard material within the extremities of the first region 42 and spaced from the edge 34.
  • the first and second regions are preferably joined to integrally form the surge guard 22.
  • the surge guard material is formed with a conductive type opposite the first and second layers and preferably comprises a P + -type conductive material.
  • the P-type material which is diffused into the outer/exposed surface of the first conductive layer 24, so that the surge guard regions 42, 44 are in electrical communication and direct physical contact with the conductive pad 28 to form an Ohmic contact which conducts current in both directions.
  • the first region 42 preferably comprises a substantially continuous and closed outer loop 42A of surge guard material.
  • the outer loop 42A extends around the perimeter conductive edge 34, and the edge is generally centrally positioned within the width of the outer loop 42A. That is, the outer loop 42A is positioned, so that it extends beyond and inside of the perimeter edge 34 as best illustrated in Fig. 2.
  • the second, inner region 44 comprises a grid of intersecting linear sections 46, 48 forming a plurality of substantially continuous inner loops, which extend, at least in part, inside the perimeter loop 42A.
  • the linear sections 46, 48 extend in transverse, preferably perpendicular, directions between opposite sides of the perimeter loop to divide the pad into sixteen (16) areas. Other patterns can be used which divide the pad into more or fewer areas.
  • Each of the linear sections 46, 48 has a first side 50 and a second side 52 which are positioned within the primary perimeter edge 34.
  • the linear sections 46, 48 are also preferably equally spaced, so that the inner loops are substantially the same size and preferably square.
  • the inner loops adjacent the perimeter loop 42 A overlap the perimeter loop in part. In the configuration shown, the inner corner loops overlap along two sides, and the inner side loops overlap along one side.
  • the distributed reverse surge guard 22 distributes the flow of reverse current across the primary conductive area 32 of the conductive pad 28, and thus, it provides superior protection from reverse current surges caused by transient threats such as ESD.
  • the diode 20 incorporating the distributed reverse surge guard 22 satisfies even the rigorous European test standards.
  • the depth of the diffusion of P + -type material is substantially the same.
  • the amount of dopant used is not excessively increased because the perimeter loop 42A and linear sections (46,48) are not as wide as the conventional guard ring.
  • the distributed reverse surge guard 22 provides increase protection without appreciably degrading the operational parameters of the electrical component. It is understood that the depth, dopant concentration, and other features can be agents to optimize the diode for specific applications.
  • an electrical component which utilizes a distributed reverse surge guard to protect the component from reverse current surges. While preferred embodiments and particular applications of this invention have been shown and described, it is apparent to those skilled in the art that many other modifications and applications of this invention are possible without departing from the inventive concepts herein. For example, a cluster of smaller chips each having their own guard ring would achieve a similar benefit. Further, by way of example, in non-power applications, the first and second layers could be replaced by a single layer of lightly doped substrate. In this application, the first and second conductive types would be the same in the meaning of the claims.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne une diode (20), comprenant une première couche conductrice (24) et une seconde couche conductrice (26), une plaquette conductrice (28) et un dispositif de protection contre les surtensions de courant inversé par répartition (22). Cette diode assure une protection améliorée contre les surtensions de courant inversé. Le dispositif de protection contre les surtensions (22) comprend une boucle externe (42), constituée de matériau de protection contre les surtensions de type P+, et une grille interne (44), constituée de sections linéaires (46, 48) qui forment plusieurs boucles internes s'étendant à l'intérieur de la boucle externe (42). Le dispositif de protection contre les surtensions (22) répartit tout courant inversé sur la zone de la plaquette conductrice (28), afin d'assurer une protection améliorée contre des menaces transitoires, telles qu'une décharge électrostatique (ESD), et lors d'essais électriques.
PCT/US2000/022206 2000-01-19 2000-08-11 Dispositif de protection contre les surtensions de courant inverse par repartition WO2001054197A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2000267698A AU2000267698A1 (en) 2000-01-19 2000-08-11 Distributed reverse surge guard

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US48702200A 2000-01-19 2000-01-19
US09/487,022 2000-01-19
EP00102771A EP1119055A1 (fr) 2000-01-19 2000-02-10 Dispositif antisurcharge inverse réparti
EP00102771.3 2000-02-10

Publications (1)

Publication Number Publication Date
WO2001054197A1 true WO2001054197A1 (fr) 2001-07-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/022206 WO2001054197A1 (fr) 2000-01-19 2000-08-11 Dispositif de protection contre les surtensions de courant inverse par repartition

Country Status (2)

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AU (1) AU2000267698A1 (fr)
WO (1) WO2001054197A1 (fr)

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USH40H (en) * 1984-07-18 1986-04-01 At&T Bell Laboratories Field shields for Schottky barrier devices
US4646115A (en) * 1983-12-20 1987-02-24 U.S. Philips Corporation Semiconductor devices having field-relief regions
US4862229A (en) * 1985-06-10 1989-08-29 U.S. Philips Corp. Semiconductor Schottky devices having improved voltage blocking characteristics
US5017976A (en) * 1988-12-02 1991-05-21 Kabushiki Kaisha Toshiba Semiconductor device having intermediate layer for pinching off conductive path during reverse bias application
US5081509A (en) * 1989-09-20 1992-01-14 Hitachi, Ltd. Semiconductor rectifying diode with pn geometry
US5148241A (en) * 1989-12-15 1992-09-15 Kabushiki Kaisha Toshiba Method of manufacturing a schottky diode device
US5233209A (en) * 1989-06-08 1993-08-03 Bt&D Technologies Ltd. Guard ring structure with graded be implantation
US5278443A (en) * 1990-02-28 1994-01-11 Hitachi, Ltd. Composite semiconductor device with Schottky and pn junctions
US5430311A (en) * 1991-09-20 1995-07-04 Hitachi, Ltd. Constant-voltage diode for over-voltage protection
US5561313A (en) * 1993-04-22 1996-10-01 Fuji Electric Co., Ltd. Protective diode for transistor
US5691554A (en) * 1995-12-15 1997-11-25 Motorola, Inc. Protection circuit
US5850095A (en) * 1996-09-24 1998-12-15 Texas Instruments Incorporated ESD protection circuit using zener diode and interdigitated NPN transistor
US5923079A (en) * 1996-11-29 1999-07-13 Nec Corporation Single-chip system having electrostatic discharge (ESD) protective circuitry including a single bipolar transistor portion

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646115A (en) * 1983-12-20 1987-02-24 U.S. Philips Corporation Semiconductor devices having field-relief regions
USH40H (en) * 1984-07-18 1986-04-01 At&T Bell Laboratories Field shields for Schottky barrier devices
US4862229A (en) * 1985-06-10 1989-08-29 U.S. Philips Corp. Semiconductor Schottky devices having improved voltage blocking characteristics
US5017976A (en) * 1988-12-02 1991-05-21 Kabushiki Kaisha Toshiba Semiconductor device having intermediate layer for pinching off conductive path during reverse bias application
US5233209A (en) * 1989-06-08 1993-08-03 Bt&D Technologies Ltd. Guard ring structure with graded be implantation
US5081509A (en) * 1989-09-20 1992-01-14 Hitachi, Ltd. Semiconductor rectifying diode with pn geometry
US5148241A (en) * 1989-12-15 1992-09-15 Kabushiki Kaisha Toshiba Method of manufacturing a schottky diode device
US5278443A (en) * 1990-02-28 1994-01-11 Hitachi, Ltd. Composite semiconductor device with Schottky and pn junctions
US5430311A (en) * 1991-09-20 1995-07-04 Hitachi, Ltd. Constant-voltage diode for over-voltage protection
US5561313A (en) * 1993-04-22 1996-10-01 Fuji Electric Co., Ltd. Protective diode for transistor
US5691554A (en) * 1995-12-15 1997-11-25 Motorola, Inc. Protection circuit
US5850095A (en) * 1996-09-24 1998-12-15 Texas Instruments Incorporated ESD protection circuit using zener diode and interdigitated NPN transistor
US5923079A (en) * 1996-11-29 1999-07-13 Nec Corporation Single-chip system having electrostatic discharge (ESD) protective circuitry including a single bipolar transistor portion

Also Published As

Publication number Publication date
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