WO2001051993A1 - Systeme, procede et masque de photogravure destines a corriger les aberrations dans un systeme de photogravure - Google Patents

Systeme, procede et masque de photogravure destines a corriger les aberrations dans un systeme de photogravure Download PDF

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Publication number
WO2001051993A1
WO2001051993A1 PCT/US2000/024932 US0024932W WO0151993A1 WO 2001051993 A1 WO2001051993 A1 WO 2001051993A1 US 0024932 W US0024932 W US 0024932W WO 0151993 A1 WO0151993 A1 WO 0151993A1
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WO
WIPO (PCT)
Prior art keywords
photomask
aberrations
features
mask
patterning system
Prior art date
Application number
PCT/US2000/024932
Other languages
English (en)
Inventor
Edward E. Ehrichs
Michael G. Mcintyre
Carroll W. Webb
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO2001051993A1 publication Critical patent/WO2001051993A1/fr

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70241—Optical aspects of refractive lens systems, i.e. comprising only refractive elements
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70591—Testing optical components
    • G03F7/706—Aberration measurement

Definitions

  • TITLE SYSTEM, METHOD AND PHOTOMASK FOR COMPENSATING ABERRATIONS IN A PHOTOLITHOGRAPHY PATTERNING SYSTEM
  • This invention relates to semiconductor processing and. more particularly, to a method, system, and photomask for compensating for aberrations in a photolithography patterning system
  • MOS metal-oxide-semiconductor
  • MOSFET MOS field-effect transistor
  • a gate dielectric typically composed of silicon dioxide, is formed on the semiconductor substrate
  • a gate conductor is formed over the gate dielectric and a source and drain are formed by introducing dopant impurities into the semiconductor substrate
  • Conductive interconnect lines are then formed to connect the MOSFETs to each other and to the terminals of the completed integrated circuit
  • Modern high-density integrated circuits typically include multiple interconnect levels to provide all of the necessary connections Multiple interconnect levels are stacked on top of each other with intervening dielectric levels providing electrical insulation between interconnect levels
  • Photolithography is a process whereby a pattern may be transferred from a photomask onto the semiconductor topography
  • a layout design defines the size and shape of the circuit features for each processing layer
  • Computer aided design packages exist which enable design lavout by, among other things, taking into consideration the design rules within and between the various processing layers
  • a photomask is created by writing photomask geometry data to a photoblank using a photomask writing system, or PG
  • a photoblank substrate is typically quartz, but may be soda lime, borosihcate. or white crown
  • the photoblank may vary in size For example, it may be from 2 to 7 inches square or it may have a diameter of 7 25 inches
  • a typical photoblank is a quartz plate with a layer of chrome on one side The chrome is generally covered with an anti-reflective coating and a photosensitive material, often called photoresist
  • a photomask writing svstem may be, for example, an electron beam ("e-beam") tool or a laser tool which transfers the desired circuit features to the photoblank by exposing the photoresist The exposed photoresist may then be removed with a developer, assuming a positive photoresist is used The photoblank is subsequently etched to remove the anti-reflective coating and chrome wherever the resist has been removed
  • One commonly used photolithographic patterning system is the step and repeat projection system in which the photomask can pattern only a portion of the photoresist
  • a step-and-repeat system projects a pattern of the photomask onto a portion of the semiconductor substrate
  • the step-and-repeat system then moves, or "steps", the semiconductor substrate and projects the pattern of the photomask onto a different portion of the semiconductor substrate
  • the entire photomask field may be projected in a single flash while the photomask plane and the wafer plane are stationary relative to one another
  • This type of step-and-repeat system is commonly referred to as a "stepper”
  • Another type of step-and-repeat system is commonly referred to as a "scanner"
  • a scanner a portion of the photomask field is projected while the photomask plane and the wafer plane move with respect to the exposing radiation Either process is repeated until a photomask's pattern has been projected onto each area of the semiconductor substrate where a die is to be formed
  • each photolithography patterning system l e scanner or stepper
  • aberrations which may prevent the system from transferring the photomask pattern exactly as printed on the photomask
  • An aberration is broadly defined as any deviation of the real performance of a system from its ideal performance
  • An aberration in a photolithography patterning system may be attributed to any number of factors, e g , one or more lenses of the system or the stage Aberrations may be repeatable under similar exposure conditions, therefore they may be mapped for a particular patterning system and process layer
  • the corresponding portion of the photoresist may be improperly patterned, resulting in an incorrect or incomplete photomask pattern transfer onto the photoresist
  • the developed photoresist will not have the desired pattern and the photoresist may not protect the proper portions of the underlying semiconductor substrate when the photoresist is used as a mask in subsequent processing For example, if the photoresist is used to mask a metal layer which will be etched to form inter
  • a photolithography patterning system is evaluated to characterize its aberrations Evaluation of the patterning system may be performed, for example, by patterning a semiconductor substrate with a test photomask, thus creating test patterns on the semiconductor substrate Images of the test patterns may be evaluated to characterize aberrations present in a photolithography patterning system Aberrations may be attributed to. for example, the illumination source, the lens(es) or the stage of. e g . an exposure processing step Characterization ot the aberrations will indicate the size and location of an aberration-affected area, and the aberrations' effects on various types ot design features
  • the characterization of a photolithography patterning system's aberrations may be used to identify which design features will be susceptible to distortion
  • Design features may be part of an intended integrated circuit pattern for a specific processing layer for one or more die
  • Design features have dimensions and positions which are proportional to intended substrate feature dimensions and positions
  • the design features which would be affected by the aberrat ⁇ on(s) are modified by changing their s ⁇ ze(s) and or shape(s) to form mask features configured to compensate for the aberration-induced distortions
  • a photomask having the modified mask features may then produce substrate features having the intended dimensions and positions in the aberration- affected areas, rather than distorted dimensions and positions
  • the mask features may be included in a set of photomask geometry data
  • the photomask geometry data would be stored on some type of carrier or memory medium, I e a hard drive
  • the geometry data would then be transferred to a photomask manufacturing area
  • a photoblank such as a quartz plate having one or more opaque materials coated with photoresist
  • I e an e-beam or laser system may be exposed using some type of photomask writing tool, I e an e-beam or laser system, to create a photomask which uses the photomask geometry data to compensate for aberrations in a photolithography patterning system
  • the resultant photomask when used in the characterized patterning system, may have mask features which project substrate features that are proportional to the sizes and positions of (undistorted) design features
  • a system comprising a storage medium containing programming instructions for evaluating patterning system data, thus characterizing aberrations of a photolithography patterning system
  • the system also comprises programming instructions for modifying design feature data to compensate for aberrations, thus generating mask feature data
  • the system may further comprise a photolithography patterning system associated with the characterized aberrations, a metrology tool associated with the patterning system data, and/or a photomask writing tool associated with transfer of the mask feature data to a photoblank
  • a svstem contemplated herein comprises a storage medium containing mask feature data which includes design feature data modified to compensate for aberrations
  • the storage medium mav further comprise the design feature data and/or patterning system data used to characterize the aberrations
  • the system may further comprise a photolithography patterning system associated with the characterized aberrations a metrology tool associated with the patterning system data and/or a photomask writing tool associated with transfer of the mask feature data to a photo
  • the photomask comprises at least one mask feature which has been altered with respect to a corresponding design feature to correct for a patterning system aberration Specifically, at least one of the mask features on the photomask differs in relative dimensions and/or positions from a corresponding feature found on a semiconductor topography by exposure of the topography through the photomask, where the location of this differing mask feature corresponds to a position affected by an aberration associated with a photolithography patterning system used for the exposure
  • Fig 1 is an exemplary cross-sectional side-view schematic of a photolithographic system for transferring a pattern located on a photomask onto a photoresist layer located on a semiconductor substrate,
  • Fig 2 is an exemplary top plan view of a photomask and an upper surface of the semiconductor substrate with circuit patterns affected by an aberration in a photolithographic system
  • Fig 3 is an exemplary plan view of an aberration's effect on a design feature, and a modified mask feature which compensates for the aberration's effect,
  • Fig 4 is an exemplary top plan views of a test photomask and an upper surface of the semiconductor substrate with test features
  • Fig 5 is a block diagram of a scanning electron microscope
  • Fig 6 is a flow diagram for an exemplary procedure for generating photolithography patterning system data
  • Fig 7 is a flow diagram for an exemplary procedure for generating photomask geometry data
  • Fig 8 is an exemplary top plan view of a photomask compensated to correct for a photolithographic patterning aberration and an upper surface of a semiconductor substrate patterned on the aberrant patterning system
  • Fig 7 is a flow diagram for an exemplary procedure for generating photomask geometry data
  • Fig 8 is an exemplary top plan view of a photomask compensated to correct for a photolithographic patterning aberration and an upper surface of a semiconductor substrate patterned on the aberrant patterning system
  • Fig 9 is a block diagram of a system for compensating for aberrations
  • Fig 1 shows an exemplary side-view schematic ot a photolithographic system and a portion of a semiconductor substrate on which patterns are being printed
  • the photolithography patterning systems may include many elements not shown in Fig 1, e g , more lenses
  • Photolithography patterning system 10 is preferably a step and repeat projection system, i e a "stepper" or scanner" Prior to placing a semiconductor substrate in photolithography patterning system 10.
  • photoresist 24 is applied to the semiconductor substrate 22 by, for example, spin coating
  • semiconductor substrate 22 occupies wafer stage 26
  • Light source 12 projects light through photomask 16 and lens 20 onto photoresist 24 that is located on an upper surface of semiconductor substrate 22
  • the light from light source 12 is preferably from the ultraviolet portion of the electromagnetic spectrum
  • Light source 12 may be, for example, a mercury-vapor lamp or an excimer laser
  • other radiation wavelengths may also be suitable, such as x-ray radiation
  • Photomask 16 includes clear and opaque regions that define a pattern to be created in photoresist 24 Exposure of portions of photoresist 24 to the light changes the solubility of those portions in a developer Photomask stage 14 is occupied by a photomask 16
  • the pattern of photomask 16 may include geometry data which may be used to produce integrated circuit features
  • the pattern of photomask 16 may also include test patterns which may be used to verify proper operation of photolithography patterning system 10
  • Lens 20 may reduce the size of the pattern of photomask
  • photolithography patterning system 10 moves, or "steps", wafer stage 26 upon which semiconductor substrate 22 is arranged and projects the pattern onto a different portion of photoresist 24 This procedure is repeated until the pattern has been projected onto all areas of photoresist 24 where a pattern is desired After every area of photoresist 24 where a pattern is desired has been patterned, the semiconductor substrate 22 is removed from photolithography patterning system 10.
  • photoresist 24 is typically developed by spraying developer onto photoresist 24
  • the developer removes portions of photoresist 24 that have been exposed to light by photolithographic system 10 If photolithography patterning system 10 has an aberration, portions of photoresist 24 may be improperly defined due to the aberration.
  • Improper definition may result in improper transfer of the pattern of photomask 16 onto photoresist 24 and may ultimately lead to failure of the integrated circuit being fabricated
  • An aberration of patterning system 10 is any deviation of the real performance of the patterning system from its ideal performance
  • An aberration may result from a localized defect on an optical component of the photolithography patterning system, for example, the lens 20
  • Some circumstances that may produce a lens aberration include incorrect lens construction (I e incorrect shape or thickness of glass elements) or improper lens use (l e incorrect environmental conditions)
  • an aberration may result from a localized defect of a physical component of the photolithography patterning system, for example, inconsistent movement of the wafer stage 26, or alternatively, localized defects of a consistently moved stage
  • Fig 2 depicts an improper transfer of a pattern from a photomask 30 onto a wafer surface 40 due to a photolithography patterning system aberration
  • Integrated circuit photomask 30 is shown in Fig 2a with patterns for four separate vet identical die regions. 32a, 34a, 36a, and 38a
  • the patterns for all four circuits 32, 34, 36, and 38 are transferred to the wafer 40 each time the photolithography patterning system "steps" the wafer and exposes the wafer surface Wafer 40 is shown in Fig 2b with multiple patterns of photomask 30
  • Fig 2c and 2d each illustrate one of the projections of photomask 30 transferred to the wafer 40
  • FIG. 3 illustrates the approach of the method described herein to compensate for aberrations
  • Fig 3a illustrates a portion of a desired design feature 50 as it may appear, for example, on a screen of a Computer Aided Design ("CAD") system
  • Area 51 indicates an area of feature 50 corresponding to an area of a corresponding photomask having exposure distorted by a patterning system aberration
  • Fig 3b illustrates an exemplary distorted substrate feature 52 obtained from a photomask with a mask feature having the same relative size and position as the design feature 50 when a projection of this feature is coincident with aberration-affected area 51
  • Fig 3c illustrates an exemplary mask feature 54 derived from a modification of design feature 50 which has
  • Fig 4a illustrates a test photomask 42 which may be used to analyze the performance of a photolithography patterning system
  • Test photomask 42 may contain a plurality of pattern areas 43 each having a plurality of features 44 patterned on a topography using the same optical system that applies production features onto a customer-destined die
  • the features 44 will include lines at the minimum allowable feature size printable by photolithography patterning system 10
  • the minimum allowable feature size may be, for example, 0 18 ⁇ m
  • the pattern area 43 may contain either dense lines and/or isolated lines, and may contain either horizontal and/or vertical lines
  • the pattern area 43 may be
  • Fig 4b illustrates a test wafer 46 which may be used to analyze the performance of a photolithography patterning system
  • the pattern of test photomask 42 is projected onto the surface of a wafer 46 multiple times using photolithography patterning system 10 and subsequently developed to form features 48 on wafer 46
  • Exposure region 47 represents the pattern transferred from photomask 42 with a single exposure In a preferred embodiment, the exposure region 47 will span the entire printable field area of photolithography patterning system 10
  • the exposure region 47 may be transferred to the entire surface of wafer 46 or may be transferred to only one or more areas of the water surface
  • Exposure region 47 may contain a plurality of pattern regions 49
  • Pattern region 49 represents the pattern transferred from pattern area 43 With pattern region 49 is a plurality of test features 48
  • images of the test features 48 are analyzed to determine the presence of system aberrations
  • System aberrations may indicate that test features 48 in the area of an aberration are distorted in such a way that an integrated circuit having the distorted feature would not function optimally Alternatively,
  • test patterns 48 on the wafer surface are examined by a metrology tool, for example, a scanning electron microscope, an optical microscope, a laser confocal imaging system, or a profilometer
  • the device tor magnifying the test patterns is a scanning electron microscope which uses a focused electron beam to create a magnified image of a surface
  • Fig 5 depicts a cross-sectional side-view schematic ot a scanning electron microscope 60
  • Scanning electron microscope 60 is enclosed by vacuum chamber 62
  • Load lock 64 allows semiconductor substrate 22 to be introduced into vacuum chamber 62 and placed on stage 70
  • Electron column 66 generates a focused electron beam and deflection system 68 may raster the electron beam across a portion of semiconductor substrate 22
  • Typical electron beam energies may range from approximately 05 to 40 keV
  • Secondary electrons emitted from the surface of semiconductor substrate 22 are detected by detector 72
  • detector 72 The output of detector 72 is used to modify an
  • Fig 6 shows a flow diagram for a procedure for characterizing aberrations of a photolithography patterning system according to some embodiments of the method recited herein
  • a metrology tool e g
  • the metrology tool may be under the control of a computer system
  • the images measured by the scanning electron microscope are then sent to a computer system (box 82)
  • the computer system then stores a copy of the image in an appropriate storage medium such as a hard disk (box 84)
  • the computer system may assess the images to determine whether the patterned image is acceptable or unacceptable (box 86)
  • the computer system may compare the measured images of each test pattern to a reference image of the test pattern
  • the computer system calculates the difference between the measured images and the reference image
  • the differences are predetermined to be either acceptable or unacceptable If a difference is determined to be unacceptable, the computer svstem finds a function that converts the unacceptable measured image
  • the write systems typicallv use rectangles and trapezoids so the photomask geometry data is divided up, or fractured, into these shapes
  • the formatted data may also include fiducials or other reference marks and or instructions tor the placement of all the different patterns on the photomask
  • the formatted data is transferred to a photomask writing tool to create a photomask
  • the photomask writing tool e g an e-beam or laser system, will write the data to a photoblank to create a compensated photomask
  • Fig 8 illustrates a compensated photomask 90 and resultant substrate features on wafer surface 100
  • Compensated photomask 90 is shown in Fig 8a including patterns for four separate circuits. 92a.
  • circuits 94a, 96a, and 98a The four circuits are intended to be identical on the wafer surface
  • an aberration exists in the photolithography patterning system which affects the exposure of the portion of the photomask containing circuit 36
  • the corresponding portion of the compensated photomask contains the pattern for circuit 96
  • the pattern for circuit 96 has been compensated to correct for the aberration
  • the circuit 96a shown on photomask 90 has a feature which is larger than the corresponding features shown in circuits 92a 94a and 98a
  • the patterns 96c and 96d are essentially identical to the corresponding patterns of circuits 92c, 92d, 94c, 94d.
  • Fig 9 depicts an embodiment of system 90 for compensating photolithography patterning system aberrations
  • Fig 9 illustrates the functionality, and not necessarily the specific structure, of the system Included within the svstem 90 is storage medium 94
  • Storage medium 94 may take many forms It may be a volatile or non-volatile memory (e g , read-only memory or random access memory), a magnetic or optical disk, a magnetic tape, or a transmission path
  • Storage medium 94 includes programming instructions 96 for evaluating photolithography patterning system data and programming instructions 98 for modifying design feature data
  • Also included within storage medium 94 may be mask feature data 100 and photomask geometry data 102
  • Storage medium 94 may be a singular storage medium, or it may be a plurality of storage mediums
  • Storage medium 94 is accessible by a computer system such as computer system 92 but may not actually be included within the computer system as shown in Fig 9
  • Computer system 92 may be a singular processing system, or it may be a plurality of processing systems
  • This invention is suitable for a number of industrial applications including, but not limited to, the fields of integrated circuit manufacture It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to provide a method, system, and photomask for compensating photolithography patterning system aberrations
  • the system or method compensates for aberrations by evaluating patterning system data and thereafter modifying design features to thereby produce a photolithography mash which can compensate for such aberrations
  • Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description For example, this invention would apply not only to semiconductor manufacturing, but also to any micro thography application, e g , printed circuit board manufacturing It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be resarded in an illustrative rather than a restrictive sense

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

L'invention concerne un procédé, un système et un masque de photogravure servant à corriger les aberrations dans un système de photogravure et à améliorer le processus général de contrôle des caractéristiques des substrats formés à l'aide d'un masque de photogravure corrigé. Ledit masque de photogravure est établi de manière que les caractéristiques du substrat soient corrigées de manière à compenser les aberrations du système de photogravure. Des caractéristiques test renfermées dans un masque de photogravure peuvent être imprimées, par un système de photogravure, dans une résine photosensible située sur une surface supérieure d'un substrat de semiconducteur. Les images de ces motifs test sont évaluées par un outil de métrologie : elles sont, par exemple, mesurées par un microscope à balayage électronique, puis évaluées en vue de la caractérisation des aberrations du système. La caractérisation desdites aberrations indique la taille et l'emplacement d'une zone touchée par les aberrations, ainsi que les effets de ces aberrations sur divers types de caractéristiques de conception. On modifie donc les caractéristiques de conception qui pourraient être touchées par lesdites aberrations en changeant leur taille et/ou leur forme afin de former des caractéristiques de masque configurées pour corriger les défauts induits par les aberrations.
PCT/US2000/024932 2000-01-14 2000-09-11 Systeme, procede et masque de photogravure destines a corriger les aberrations dans un systeme de photogravure WO2001051993A1 (fr)

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EP1424595A2 (fr) * 2002-11-26 2004-06-02 Lsi Logic Corporation Calibrage automatique d'un simulateur de masques
KR100483515B1 (ko) * 2000-12-06 2005-04-15 에이에스엠엘 마스크툴즈 비.브이. 광학시스템내의 수차를 검출하는 방법 및 장치
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US10820952B2 (en) 2013-03-15 2020-11-03 Auris Heath, Inc. Rotational support for an elongate member
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US11241559B2 (en) 2016-08-29 2022-02-08 Auris Health, Inc. Active drive for guidewire manipulation
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