WO2001048819A2 - Structure d'interconnexion et procede de fabrication associe - Google Patents

Structure d'interconnexion et procede de fabrication associe Download PDF

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Publication number
WO2001048819A2
WO2001048819A2 PCT/US2000/035483 US0035483W WO0148819A2 WO 2001048819 A2 WO2001048819 A2 WO 2001048819A2 US 0035483 W US0035483 W US 0035483W WO 0148819 A2 WO0148819 A2 WO 0148819A2
Authority
WO
WIPO (PCT)
Prior art keywords
hole
pth
forming
conductive material
pth via
Prior art date
Application number
PCT/US2000/035483
Other languages
English (en)
Other versions
WO2001048819A3 (fr
Inventor
Bob Sankman
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to AU24618/01A priority Critical patent/AU2461801A/en
Publication of WO2001048819A2 publication Critical patent/WO2001048819A2/fr
Publication of WO2001048819A3 publication Critical patent/WO2001048819A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates generally to microelectronic structures and fabrication methods, and more particularly to interconnect structures and methods of fabricating the same.
  • patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as silicon dioxide or organic polymers. Connections between the conductive material at the various interconnect levels are made by forming openings in the insulating layers and providing an electrically conductive structure such that the patterned conductive material from different interconnect levels are brought into electrical contact with each other. These structures are often referred to as contacts, vias or interconnect structures.
  • PTH plated through hole
  • FIG. 1 is a representation of an electrical circuit 10 that simulates the effective power supply inductance, L cfj . This schematic applies in the context of very high frequency switching.
  • the circuit includes a capacitor 12 connected to the V cc and V ss pads on an integrated circuit chip.
  • An inductor 14, 18 and a resistor 16, 20 are present on both the supply and return paths from the capacitor
  • the effective power supply inductance, L eff is related to the number, N, of PTH vias by the equation:
  • L PTH is the inductance of a PTH via.
  • the effective power supply inductance is inversely proportional to the number of PTH vias. Because of this relationship, one common prior art method for reducing power supply inductance involves placing extra PTH vias in the package. This has the effect of reducing the value of inductors 14, 18 ( Figure 1). Essentially, each signal-carrying via is surrounded by vias that carry the ground. In some cases, the vias are arranged in a face-centered square configuration, where the central dot would represent the power supply via, and the four outer dots would represent the ground-carrying vias. Unfortunately, the practice of adding PTH vias solely for the purpose of reducing power supply inductance results in larger package designs and/or more complicated fabrication techniques.
  • a method for fabricating an interconnect structure involves forming a first PTH via through a core material, where the first PTH via is electrically connected to a first conductive material layer. Then, a second PTH via is formed so that it is concentrically located inside the first PTH via. The second PTH via has a diameter that is smaller than a diameter of the first PTH via, and the second PTH via is electrically isolated from the first PTH via and electrically connected to a second conductive material layer.
  • the interconnect structure includes the first PTH via formed through the core material, where the first PTH via is electrically connected to the first conductive material layer.
  • the structure also includes the second PTH via concentrically located inside the first PTH via, where the second PTH via has a diameter that is smaller than a diameter of the first PTH via.
  • the second PTH via is electric ally isolated from the first PTH via and electrically connected to the second conductive material layer.
  • Figure 2 is a schematic cross-section of an interconnect structure in accordance with one embodiment of the present invention.
  • Figure 3 illustrates a flowchart of a method for fabricating an interconnect structure in accordance with one embodiment of the present invention
  • Figures 4-1 1 are schematic cross-sections illustrating various stages of fabrication of an interconnect structure in accordance with one embodiment of the present invention
  • Figure 12 illustrates an example of an integrated circuit housed by a package having via structures in accordance with one embodiment of the present invention.
  • Figure 13 illustrates a general purpose computer system that includes a printed circuit board having a microprocessor housed by a package having via structures in accordance with one embodiment of the present invention.
  • via commonly refers to structures for electrical connection of conductors from different interconnect levels. This term is sometimes used in the art to describe both an opening in an insulator in which an interconnect structure will be completed, and the completed structure itself. For purposes of this disclosure, “via” refers to the opening and “interconnect structure” refers to the completed structure itself.
  • horizontal as used herein, means substantially parallel to the surface of a substrate, and the term “vertical,” as used herein, means substantially orthogonal to the surface of a substrate.
  • interconnect structures that have the ground potential reference closer to the power supply source.
  • interconnect structures that allow signals to maintain their reference when traveling through the interconnect structure, thus reducing signal integrity problems such as overshoot, undershoot, ringback and crosstalk.
  • embodiments of the present invention both reduce inductance of the power supply and allow signals to better maintain their shielding and reference, thus improving signal integrity.
  • FIG. 2 is a schematic cross-section of an interconnect structure 100 in accordance with one embodiment of the present invention.
  • interconnect structure 100 includes a first PTH via 104 formed through a core material 102, and a second PTH via 106 concentrically located inside the first PTH via 104, but electrically isolated from the first PTH via 104.
  • Figure 3 illustrates a flowchart of a method for fabricating the interconnect structure shown in Figure 1 in accordance with one embodiment of the present invention.
  • Figures 4-1 1 include schematic cross-sections illustrating various stages of fabrication of an interconnect structure in accordance with one embodiment of the present invention.
  • the method begins, in block 202, by providing a core material layer 102 (FIG. 4), which has an upper surface 304 and a lower surface 306.
  • core material layer 102 is an organic substrate, such as an epoxy material.
  • epoxy material such as FR-4, BT, Teflon, other epoxy resins, or the like could be used in various embodiments.
  • Both the upper and lower surfaces 304, 306 of core material layer 102 are substantially horizontal.
  • the thickness of core material layer 102 is within a range of 600-1000 microns, with it being approximately 800 microns in one embodiment. Core material layer 102 could be thicker or thinner than this range in other embodiments.
  • first hole 402 (FIG. 5) is formed through the core material layer 102.
  • the diameter of first hole 402 is within a range of 200-500 microns, with it being approximately 350 microns in one embodiment. The diameter could be larger or smaller than this range in other embodiments.
  • First hole 402 is defined by first sidewalls 404, which are substantially vertical, or orthogonal, to the upper and lower surfaces 304, 306 of core material layer 102.
  • the hole is mechanically drilled, although the hole may also be drilled using a laser or other drilling technologies in various other embodiments.
  • first conductive layer 502 (FIG. 6) is formed on the first sidewalls 404 of the first hole 402, and on upper and lower surfaces 304, 306 of core material layer 102.
  • first conductive layer 502 is a copper layer, although other conductive metals or materials could be used in other embodiments.
  • a first PTH via is defined by portions 104 of the first conductive layer 502 that are disposed on first sidewalls 404. Other portions 506 of the first conductive layer are horizontally-disposed on the upper and lower surfaces 304, 306 of core material layer 102, resulting in an electrical connection between the first PTH via 104 and the horizontally disposed portions 506 of the first conductive layer.
  • first conductive layer 502 is within a range of 5-15 microns, with it being approximately 10 microns in one embodiment.
  • First conductive layer 502 could be thicker or thinner than this range in other embodiments.
  • the first hole 402 is substantially filled with non- conductive material 602 (FIG. 7).
  • First hole 402 could be screen-filled, for example, with the non-conductive material 602.
  • non- conductive material 602 is an epoxy fill material, although other non- conductive materials also could be used in other embodiments.
  • Non-conductive material 602 has a top surface 604 and a bottom surface 606, where the top surface 604 is substantially parallel to the upper surface 304 of core material 102, and the bottom surface 606 is substantially parallel to the lower surface
  • dielectric layers 702, 704 are formed on the substantially horizontal portions 506 of the first conductive layer 502, and on the top and bottom surfaces 604, 606 of the non-conductive material 602.
  • these dielectric layers 114, 116 are made of a non-conductive material that is the same as, or similar to the material used for core layer 102 or non-conductive material 602, although different dielectric materials could be used in other embodiments.
  • the thickness of dielectric layers 702, 704 is within a range of 20-40 microns, with it being approximately 30 microns in one embodiment. Dielectric layers 702, 704 could be thicker or thinner than this range in other embodiments.
  • the flowchart of Figure 2 shows first hole 402 being filled in block 208, and dielectric layers 702, 704 being applied in block 210.
  • the dielectric layers' non-conductive material could be allowed to flow into first hole 402 in order to fill first hole 402 with non- conductive material. In this embodiment, it would not be necessary to perform block 208.
  • a second hole 802 (FIG. 9) is formed within the filled first hole through the dielectric layers 702, 704 and non-conductive material 602.
  • Second hole 802 can be formed in the same or a different manner as first hole 402.
  • the second hole 802 has a diameter 804 that is smaller than a diameter 806 of the first PTH via 104.
  • the diameter of second hole 802 is within a range of 100-200 microns, with it being approximately 150 microns in one embodiment. This diameter could be larger or smaller than this range in other embodiments.
  • the second hole 802 is concentrically located within the first PTH via 104. In other embodiments, the second hole 802 could be slightly off center with respect to the first PTH via 104.
  • second hole exists within the first PTH via, not necessarily that the second hole is located exactly at the center of the first PTH via.
  • the second hole is defined by second sidewalls 808, which are substantially vertical to the upper and lower surfaces 304, 306 of core material 102.
  • a second conductive layer 902 (FIG. 10) is formed on the second sidewalls 808 of second hole 802, and on upper and lower surfaces 904, 906 of dielectric layers 702, 704.
  • Second conductive layer 902 could be made of the same or a different material as first conductive layer 502.
  • the thickness of second conductive layer 902 is within a range of 5-15 microns, with it being approximately 10 microns in one embodiment. Second conductive layer 902 could be thicker or thinner than this range in other embodiments.
  • a second PTH via is defined by portions 106 of the second conductive layer 902 that are disposed on second sidewalls 808. Other portions 910 of the second conductive layer are horizontally-disposed on the upper and lower surfaces 904, 906 of dielectric layers 702, 704, resulting in an electrical connection between the second PTH via 106 and the horizontally disposed portions 910 of the second conductive layer.
  • the second hole is located in such a manner that second conductive layer 902 does not come into contact with first conductive layer 502.
  • the second PTH via 106 is electrically isolated from the first PTH via 104.
  • second hole 802 is filled with a non-conductive material 1002 ( Figure 11) in block 216.
  • Second hole 802 could be screen-filled, for example, or a next dielectric layer could be allowed to flow into second hole 802. After filling second hole 802, the method ends. The package can then be completed by adding one or more new conductive and non-conductive layers.
  • Figure 12 illustrates an integrated circuit 1 102 housed by a package 1 104 having interconnect structures in accordance with one embodiment of the present invention.
  • the integrated circuit is located on a top surface 1106 of the package 1104, and contains a circuit which is electrically connected to one or more interconnect structures within the package.
  • integrated circuit 1102 is an microprocessor, although integrated circuit 1102 could be other devices in other embodiments.
  • a single interconnect structure or a series of interconnect structures within package 1104 provide an electrical path between the top surface 1106 and the bottom surface Package 1104 has a plurality of connectors 1110 affixed to the bottom surface 1 108.
  • connectors 1106 form contacts with metal pads (not shown) on a printed circuit (PC) board 1112, and thereby couple the package 1 104 to the PC board 1 112.
  • Connectors 1110 could be, for example, solder balls that make contact with the PC board's metal pads, or the connectors could be pins that are insertable into sockets (not shown) on PC board 1112.
  • connectors 1110 could connect to one or more intermediate layers, rather than connecting directly to PC board 1112.
  • connectors 1110 could connect to an interposer (not shown) that acts as a dimensional interface between connectors 1 1 10 and the metal pads on PC board 11 12.
  • Figure 13 illustrates a general purpose computer system 1200 that includes a PC board 1202 having a microprocessor 1204 housed by a package 1206 having via structures in accordance with one embodiment of the present invention.
  • Computer system 1200 is housed on PC board 1202, and includes bus 1208, microprocessor 1204, package 1206, power supply signal generator 1210, and memory 1212.
  • Package 1206 couples micorprocessor 1204 to bus 1208 in order to communicate power supply signals and non-power supply signals between microprocessor 1204 and devices coupled to bus 1208.
  • bus 1208 couples microprocessor 1204 to memory 1212 and power supply signal generator 1210.
  • microprocessor 1204 can be coupled to memory 1212 and power supply signal generator 1210 through two different busses.
  • power supply signal generator 1210 is not positioned on PC board 1202, but instead is positioned elsewhere.
  • Interconnect structures in accordance with the present invention both reduce inductance of the power supply and allow the signal integrity to be optimal by minimizing crosstalk and allowing signals to maintain their reference by providing a first PTH via formed through a core material, and a second PTH via concentrically located inside first PTH via, but electrically isolated from the first PTH via.
  • the embodiments of the present invention have the effect of further reducing the value of inductors 14, 18 than what is possible using prior art methods.
  • the first PTH via provides the ground and/or power plane, and also acts as a shielding conductor to contain the magnetic field produced by current through the second PTH via.
  • the second PTH via acts as the current-carrying via, either for power supply or logic signals. Because the signals carried by the second PTH via are completely surrounded by the shielding conductor (i.e., the first PTH via), the second PTH via has low inductance characteristics, resulting in better signal quality. Also, additional PTH vias used solely for the purpose of bringing the ground potential reference closer to the signal via are unnecessary. Thus, the low-inductance interconnect structure of the present invention uses less package real estate than prior art packages that have the signal-carrying via surrounded by ground-carrying vias. In addition, the shielding characteristics of the interconnect structure result in improved signal quality.
  • Embodiments of the present invention provide an interconnect structure that includes a first PTH via formed through a core material, and a second PTH via concentrically located inside first PTH via, but electrically isolated from the first PTH via.
  • Embodiments of the present invention describe herein are beneficial in that inductance of the power supply to a chip attached to an organic package is substantially reduced. This is accomplished by placing the ground potential reference much closer to the power supply source. In addition, electrical signals maintain their reference and shielding while traveling through the interconnect structure, thus reducing signal integrity problems such as overshoot, undershoot, ringback, and crosstalk.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne une structure d'interconnexion destinée à des dispositifs microélectroniques, qui comprend un premier trou d'interconnexion métallisé (PTH) formé à travers une scorie, et un deuxième PTH concentrique situé à l'intérieur du premier PTH mais électriquement isolé de celui-ci. Un procédé de production de la structure d'interconnexion consiste à former un premier trou à travers une couche de scorie, puis à former une première couche conductrice sur des parois latérales du premier trou et sur des surfaces supérieure et inférieure de la couche de scorie. Le premier trou est sensiblement rempli d'un matériau non conducteur, et des couches diélectriques sont formées sur des parties sensiblement horizontales de la première couche conductrice et sur des surfaces supérieure et inférieure du matériau non conducteur. Un deuxième trou dont le diamètre est inférieur à celui du premier trou est formé à travers les couches diélectriques et le matériau non conducteur dans une relation concentrique par rapport au premier trou. Une deuxième couche conductrice est ensuite formée sur les parois du deuxième trou et sur les surfaces supérieure et inférieure des couches diélectriques.
PCT/US2000/035483 1999-12-28 2000-12-28 Structure d'interconnexion et procede de fabrication associe WO2001048819A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU24618/01A AU2461801A (en) 1999-12-28 2000-12-28 Interconnect structure and method of fabrication therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47327299A 1999-12-28 1999-12-28
US09/473,272 1999-12-28

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WO2001048819A2 true WO2001048819A2 (fr) 2001-07-05
WO2001048819A3 WO2001048819A3 (fr) 2002-03-07

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003073506A3 (fr) * 2002-02-26 2003-11-06 Legacy Electronics Inc Porte-puce a circuit integre modulaire
US7102892B2 (en) 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
CN104519658A (zh) * 2013-09-30 2015-04-15 北大方正集团有限公司 一种电路板跳层盲孔的制作方法及电路板
CN106653318A (zh) * 2017-02-28 2017-05-10 华为技术有限公司 电感器件和交错并联直流变换器

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4675788A (en) * 1984-07-17 1987-06-23 Schroff Gesellschaft Mit Beschrankter Haftung Multi-layer circuit board
JPH0294693A (ja) * 1988-09-30 1990-04-05 Nec Corp 同軸形スルーホールを有するプリント配線板
US5257452A (en) * 1991-05-27 1993-11-02 Hitachi, Ltd. Methods of recovering a multi-layer printed circuit board
EP0591887A2 (fr) * 1992-10-09 1994-04-13 International Business Machines Corporation Plaquette de circuits imprimés
US5421083A (en) * 1994-04-01 1995-06-06 Motorola, Inc. Method of manufacturing a circuit carrying substrate having coaxial via holes
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US5949030A (en) * 1997-11-14 1999-09-07 International Business Machines Corporation Vias and method for making the same in organic board and chip carriers

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4675788A (en) * 1984-07-17 1987-06-23 Schroff Gesellschaft Mit Beschrankter Haftung Multi-layer circuit board
JPH0294693A (ja) * 1988-09-30 1990-04-05 Nec Corp 同軸形スルーホールを有するプリント配線板
US5257452A (en) * 1991-05-27 1993-11-02 Hitachi, Ltd. Methods of recovering a multi-layer printed circuit board
EP0591887A2 (fr) * 1992-10-09 1994-04-13 International Business Machines Corporation Plaquette de circuits imprimés
US5421083A (en) * 1994-04-01 1995-06-06 Motorola, Inc. Method of manufacturing a circuit carrying substrate having coaxial via holes
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US5949030A (en) * 1997-11-14 1999-09-07 International Business Machines Corporation Vias and method for making the same in organic board and chip carriers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 292 (E-0944), 25 June 1990 (1990-06-25) & JP 02 094693 A (NEC CORP), 5 April 1990 (1990-04-05) *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7102892B2 (en) 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
WO2003073506A3 (fr) * 2002-02-26 2003-11-06 Legacy Electronics Inc Porte-puce a circuit integre modulaire
CN104519658A (zh) * 2013-09-30 2015-04-15 北大方正集团有限公司 一种电路板跳层盲孔的制作方法及电路板
CN106653318A (zh) * 2017-02-28 2017-05-10 华为技术有限公司 电感器件和交错并联直流变换器

Also Published As

Publication number Publication date
AU2461801A (en) 2001-07-09
WO2001048819A3 (fr) 2002-03-07

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