WO2001042903A1

WO2001042903A1 - Data processing apparatus and data processing system

Info

Publication number: WO2001042903A1
Application number: PCT/JP1999/006837
Authority: WO
Inventors: Koji Yamada
Original assignee: Hitachi, Ltd.
Priority date: 1999-12-07
Filing date: 1999-12-07
Publication date: 2001-06-14

Abstract

A data processor (1) executes a specific load instruction, and a converter circuit (42) converts integer data, whose bit length is shorter than the bit length of a floating-point register, into the floating-point data, which is loaded into the floating-point register. The bit length of the integer data is specified in an integer data bit length information area of the specific load instruction. In accordance with the results decoded by an instruction control circuit (2), the conversion circuit (42) expands the bit length depending on the difference in bit length between the integer data and the mantissa of the floating-point format and converts the integer data into the floating-point data. Since there is no need for referring to the register setting to obtain the bit length information on integer data required for such conversion, a single instruction is sufficient to load data involving the conversion even in the case of conversion of data of different bit lengths. The access to the register each time the bit length of integer data changes is thus eliminated, increasing data processing efficiency.

Description

Description Data processing system and data processing system

The present invention relates to a data processing device and a data processing system that support floating point arithmetic. For example, a data processor that supports a data transfer instruction from a memory to a floating-point register, a graphic board that uses the data processor for processing a geometry, a three-dimensional image processing system, or a three-dimensional graphic display It relates to technology that is effective when applied to possible game machines. Background art

In 3D graphics, etc., matrix operations using a 4 × 4 transformation matrix are frequently used for rotation, enlargement, reduction, perspective projection, and translation of figures, and the brightness of the light receiving surface is determined. Uses inner product operation. For example, in order to represent a 3D model using a polygonal model that approximates a 3D shape, generally, the vertex coordinate data of a polygon, the vertex normal data of a polygon (vertex normal vector), etc. are expressed according to the polygon array. Will be prepared.

For the movement of the three-dimensional model, affine transformation such as rotation and parallel movement of polygon vertex coordinates may be performed using a transformation matrix. The brightness of the vertices of the polygon can be obtained by the inner product of the ray vector and the vertex normal vector.

Such a matrix operation or inner product operation requires repeated product-sum operations. Also, high-end systems have traditionally used floating-point numbers as data handled in three-dimensional graphics. Game consoles and mobile information Even in fields where cost constraints are severe, such as terminals, the data handled tends to shift from integers to floating point numbers. This is because using floating-point numbers is more suitable for advanced processing.

However, when a 3D model is represented using polygon data as described above, a large amount of data such as vertex coordinate data and vertex normal data is required. If data is stored in memory as data, even if it is a single-precision floating-point format, the data will be 32 bits for each component, and the amount of data in the entire 3D model will be enormous.

At this time, the data processing speed of the data processor that performs the inner product or the product-sum operation is remarkably increased today, but the access speed of the memory remains relatively slow. Even if a cache memory is used, since the amount of data is large, a cache miss always occurs on the way, and it has been clarified by the present inventor that there is a limit to speeding up by itself. Therefore, the present inventor expresses all or a part of the polygon data as an integer, transfers the data from the memory to the floating-point operation unit as integer data, and then converts the data to a floating-point number to perform the inner product operation or the like. We examined the use of multiply-accumulate operations.

First, the inventor focused on the accuracy of data required for drawing. The vertex coordinates of the polygons of the 3D model undergo an affinity transformation corresponding to rotation and translation. The polygons moved by this transformation undergo a perspective transformation for projection onto screen coordinates. The vertices of the perspective transformed figure will indicate the pixel locations on the screen when the figure is actually drawn in the frame buffer. Focusing on the affine transformation, it is generally said that it is preferable to express the vertex coordinates of a polygon with a floating-point number that is less likely to overflow. At this time, VGA (Video Graphics Taking into account the display accuracy on a screen of the order of SVG A (Super Video Graphics Array) or SVG A, each component of the vertex coordinates has a mantissa of a floating-point number conforming to IEEE 754, with a 4-bit mantissa of 23 bits. The present inventor has found that it is not always necessary to represent the value with a byte floating point number, and that a 16-bit integer may be sufficient.

Also, the vertex normal data undergoes rotation transformation, and is interpolated with the ray vector to obtain a value related to brightness. The value will ultimately be the intensity of the three primary colors RGB (red, green, blue). It is said that these values are ergonomically enough to have 8 bits each. For example, each of the three primary colors of RGB can represent a full color of 16 777 2 16 (^ 25 6 * 25 6 * 25 6) colors by 8 bits. Therefore, it has been clarified by the present inventors that each component of the normal vertex vector is almost sufficient with 8 bits.

According to the above study, even if the vertex coordinate data of the polygon and the normal vector data are integer data, there is no problem in accuracy, and the number of data bits in the latter is further reduced compared to the former to reduce the amount of data. It was clarified that reduction could be possible.

Further, the present inventor has searched the prior art and found Japanese Patent Laid-Open No. 5-100822. This is a digital signal processor which converts integer format data at high speed in two's complement floating point format, and employs dedicated hardware for performing such conversion. In particular, the conversion uses a constant register that specifies the number of integer digits to specify the bit length of the integer data. Therefore, when changing the bit length of the integer data to be processed, an instruction for loading a different value into the constant register must be executed each time.

According to the study of the above prior art by the present inventors, the bit length is The inventor has found that when a large number of different integers are used, the number of executions of the load instruction for the constant register is increased and the overhead may be increased. That is, when the data bit lengths are made different from each other, such as the vertex coordinate data of the polygon and the normal vector data, and the effect of reducing the amount of data is maximized, the setting value of the constant register data is used. The inventors of the present invention have clarified that change processing frequently occurs, the overhead of data processing increases, and the data amount reduction effect may be offset or reduced.

An object of the present invention is to provide a method for making the data length even if it is intended to maximize the effect of reducing the amount of data by making the bit length of the data different from the vertex coordinate data of the polygon and the normal vector data. An object of the present invention is to provide a data processing device and a data processing system capable of fully exhibiting the effect of reducing the amount of data without increasing processing overhead.

Another object of the present invention is to improve the data processing speed in a data processing system in which the data transfer cost rather than the operation cost determines the overall data processing speed.

It is another object of the present invention to provide a data processing device capable of converting 1-byte or 2-byte integer data into floating-point data and loading the data into a floating-point register at high speed.

Still another object of the present invention is to provide a recording medium in which an information processing apparatus stores a program capable of easily realizing a reduction in data capacity for floating-point arithmetic and an increase in efficiency of data processing, and a storage medium storing such a program. It is to provide a transmission medium for transmitting a program.

The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings. Disclosure of the invention

[1-1] The data processing apparatus according to the present invention in terms of a semiconductor integrated circuit or a semiconductor device such as a microcomputer or a single-chip data processor has a bit length shorter than the bit length of the floating-point register. Can be converted to a floating-point number data and loaded into a floating-point register, and the bit length of the integer data is determined by the bit length information area of the integer data in the instruction indicating the load. In accordance with the result of the decoding, the bit length extension processing is performed according to the difference between the bit length of the integer data and the bit length of the mantissa of the floating-point format, and the integer data is floated. It is converted to decimal point data.

Specifically, the data processing device includes: an instruction control means for decoding a fetched instruction to generate a control signal; a floating-point arithmetic circuit, a floating-point register and a conversion means, each of which is controlled by the control signal; Have. The conversion means inputs integer data represented by a bit length shorter than the bit length of the floating-point register, and converts the input integer data into floating-point number data in a predetermined floating-point number format. In addition, the first processing of outputting the type-converted floating-point number data to the floating-point register is possible. The bit length information of the integer data required for the type conversion is obtained by the instruction control means decoding the bit length information area of the integer data included in the first instruction instructing the first process. is there.

According to the above-described means, data shorter than the bit length of the floating-point register is input and processed. Therefore, when inputting data having the same bit length as the bit length of the floating-point register, In comparison, the data amount or the data memory capacity can be reduced. For example, in three-dimensional image processing, if each of six data items including X, Y, 、 coordinate values and normal vector components is stored as a 32-bit single-precision floating-point number, 2 points per vertex 4-byte data Amount. On the other hand, according to the above means, in the three-dimensional image processing, the values of the X, Y, and 座標 coordinates can be represented by 2-byte integers, and each component of the normal vector can be represented by 1-byte integer. The amount of data can be reduced to bytes. In addition, if the data amount is reduced by the above means, the data transfer cost is also reduced. Therefore, in a system where the data transfer cost determines the overall processing speed rather than the calculation cost, the data processing speed is reduced. Can be improved.

Since integer data can be converted to floating-point data by the conversion means and loaded into the floating-point register, the type of integer data can be converted to floating-point data by one instruction and converted to the floating-point register. can do.

In the type conversion, a bit length extension process is performed according to a difference between the bit length of the integer data and the bit length of the mantissa of a predetermined floating-point format. Is obtained from the decoded result of the first instruction, such as the above-mentioned spoken instruction. Therefore, even when integer data having different bit lengths are mixed, processing such as the load processing involving the type conversion is performed by one instruction. Can do so. Even if the bit length of the integer data to be processed changes, the extra register access operation is not performed each time the bit length of the integer data to be processed changes as compared with the case where the bit length information of the integer data to be processed is specified in the control register. And data processing efficiency is improved.

[1-2] The conversion means further receives integer data represented by a bit length shorter than the bit length of the floating-point register, and converts the input integer data bit number into the floating-point value. A second process of extending the bit length of the decimal point register and outputting the extended integer data to the floating point register may be enabled. At this time, the bit length information of the integer data necessary for the bit length extension of the integer data in the second process is a bit length information area of the integer data included in the second instruction instructing the second process. The command control means decodes and obtains it. In the second process, the floating-point register is an integer. Gives you the freedom to load the data and convert it to floating point data.

[1-3] The conversion means further inputs floating-point data from the floating-point register, and expresses the input floating-point data with a bit length shorter than the bit length of the floating-point register. It may be possible to perform a third process of performing inverse conversion to integer data and outputting the inversely converted integer data. From the result of the instruction control means decoding the bit length information area of the integer data included in the third instruction instructing the third process, the bit length information of the integer data required for the inverse conversion is obtained. obtain. The third process converts the floating-point number data of the floating-point register into integer data to give a degree of freedom to store the data in a memory or the like.

[1-4] The bit length information area includes a second bit length shorter than the first bit length of the floating point register and a third bit length shorter than the second bit length. Either length may be selectively designated. For example, the first bit length is 32 bits, the second bit length is 16 bits, and the third bit length is 8 bits. This is especially useful when mixing data with different bit lengths.

[1-5] The data processing device may be configured as a single-chip data processor further including an integer unit whose operation is controlled by a control signal output from the instruction control means.

From the viewpoint of speeding up data access by an integer unit constituting a part of a central processing unit, a cache memory device connected to the integer unit and the floating point register is connected to a single-chip processor. It may be built in.

In this case, it is advantageous that the conversion means is connected to a data bus to which the cache memory device is connected. At this time, the floating point number The bit length of the point register is 4 n bytes (where n is a positive integer), and the integer byte is mixed with a bit length of n bytes or 2 n bytes. When the byte width is set to 8 n bytes and the cache memory device can output a plurality of consecutive integer data in a range of 8 n bytes in parallel to the data bus, the conversion means includes the type conversion function. The length of the integer data included in the first instruction such as a load instruction with a length, based on the result of decoding by the data reporter, the first integer data on the data bus and the second integer data next to the first integer data. Then, the first processing may be performed in parallel. The efficiency of the first processing such as the above-described data loading processing involving type conversion is further improved.

Although the access speed is lower than that of the built-in cache memory device, the system may be configured by connecting the cache memory device to the outside of the single-chip data processor.

[2-1] From the viewpoint of focusing on an instruction format such as the first instruction, the data processing device according to the present invention decodes the fetched instruction and generates a floating-point register based on the decoding result. The floating-point operation used is possible. The instruction using the floating-point register includes an operation code field indicating the type of the instruction, a register setting field for specifying a floating-point register used for processing, and a first information field having other information fields. Including instructions. In the first instruction, the operation code field indicates that integer data is to be converted to floating-point data in a predetermined floating-point format and stored in a floating-point register. The register setting field indicates the type of the floating-point register storing the converted floating-point number. Part of the other information field indicates the location of the integer data to be converted to floating point data. Another part of the other information field is an integer represented by a bit length shorter than the bit length of the floating-point register. Indicates the bit length information of the data.

According to the invention of this aspect, similarly to the above, the amount of data or data memory to be read as a floating-point operation processing object can be reduced, and in addition, the data transfer can be performed by reducing the data amount. Since the cost is also reduced, the data processing speed can be improved in a system where the overall processing speed is determined by the data transfer cost rather than the computational cost. In addition, integer data can be converted to floating-point data by one instruction and loaded into the floating-point register, and when integer data having different bit lengths are mixed, the same type conversion can be performed with one instruction. The data load process can be performed with data, and the data processing efficiency is improved.

When the floating-point register has a bit length of 32 bits, the bit length information of the integer data may selectively indicate 8 bits or 16 bits. This is particularly useful when mixing data with different bit lengths.

[2-2] The instruction using the floating-point register may include a second instruction. The second instruction has an operation code field indicating the type of the instruction, a register setting field for specifying a floating-point register used for processing, and other information fields. In the second instruction, the operation code field indicates that the integer data is to be extended in bit length and stored in the floating-point register. The register setting field indicates the type of the floating-point register storing the converted floating-point data. Part of the other information field indicates the location of the integer data to be converted to floating-point data. Another part of the other information field indicates the bit length information of the integer data represented by a bit length shorter than the bit length of the floating point register. According to this, after fetching integer data in floating point register Gives the freedom to convert to floating point data.

[3-1] The present invention from the viewpoint of a data processing system such as a graphic board or a three-dimensional image processing system is connected to a first data processing device such as a data processor and the data processing device. And a second data processing device such as the Ixellale. The data processor decodes the fetched instruction, performs integer arithmetic and floating-point arithmetic based on the decoded result, and decodes the fetched instruction to generate a control signal.Instruction control means, an integer unit, It has a floating-point arithmetic circuit, a floating-point register, and conversion means. The conversion means inputs an integer value represented by a bit length shorter than the bit length of the floating-point register, and converts the input integer data to floating-point number data in a predetermined floating-point format. The first process of performing type conversion and outputting the type-converted floating-point number data to the floating-point register is possible. In the type conversion, the bit length information of the integer data necessary for the bit length extension according to the difference between the bit length of the integer data and the bit length of the mantissa of the floating point format is obtained by performing the first processing. The instruction control means decodes the bit length information error of the integer data included in the specified instruction. The accelerator can input a result of the floating-point operation by the data processor and perform data processing.

The data processing system of the above viewpoint can also reduce the amount of data to be read or the amount of data memory to be read as a target of floating-point arithmetic processing, and also reduce data transfer costs by reducing the amount of data. Therefore, in a system where the overall processing speed is determined by the data transfer cost rather than the operation cost, the data processing speed can be improved. In addition, integer data can be converted to floating-point data by one instruction and loaded into the floating-point register, and integer data with different bit lengths can be mixed. In addition, the data loading process involving the type conversion can be performed with one instruction, and the data processing efficiency is further improved.

[3-2] In the data processing system, a main memory shared by the data processor and the accelerator may be provided. A cache memory capable of holding a part of the storage information held by the main memory may be incorporated in the processor.

Focusing on three-dimensional graphics, the integer data may be vertex coordinate data for approximating a three-dimensional shape and polygon data including vertex normal data.

When the floating-point register has a bit length of 32 bits, the vertex coordinate data of the polygon data has a 16-bit length for each component, and the vertex normal data has an 8-bit length for each component. May be. The bit length information of the integer data may selectively indicate an 8-bit length or a 16-bit length. The data processing system handles polygon data in which integer data having different bit lengths coexist, and can perform processing such as loading with the type conversion with one instruction, and has a high data processing efficiency.

At this time, the data processor may perform a geometry operation using the polygon data, and the data processing may perform a process of drawing the data obtained by the geometry operation in a frame buffer.

[4-1] A data processing system according to another aspect of the present invention includes a central processing unit, a floating-point unit, a memory connected to the central processing unit and the floating-point unit, And The floating-point unit has a floating-point register, a floating-point arithmetic circuit, and conversion means. The converting means inputs the integer data represented by a bit length shorter than the bit length of the floating-point register into the memory, and converts the input integer data into a floating-point number in a predetermined floating-point number format. Decimal point data The first processing is possible in which the type conversion is performed in the evening and the type-converted floating-point number data is output toward the floating-point register. The bit length information of the integer data required for the type conversion is obtained from the value of the bit length information error of the integer data included in the predetermined instruction instructing the first process. The accelerator is capable of performing data processing by inputting a floating-point calculation result obtained by the floating-point unit.

The data processing system of the above viewpoint can also reduce the amount of data to be read or the amount of data memory to be read as a floating-point operation target, and also reduce the data transfer cost by reducing the amount of data. Data processing speed can be improved in a system where the overall transfer speed is determined by the overnight transfer cost rather than the cost. In addition, integer data can be type-converted to floating-point number data and loaded into a floating-point register with one instruction.If integer data with different bit lengths are mixed, the type conversion can be performed with one instruction. The load processing can be performed, and the data processing efficiency is further improved.

[5] The invention from the viewpoint of providing a program for realizing the function of converting the type to the floating-point number conversion is a recording medium for the program and a transmission medium for the program.

The recording medium of the program is a medium such as a CD-ROM for statically recording the program. The transmission medium is a communication medium for dynamically transmitting or distributing the program electronically, electromagnetically, or optically through a network connected by a wired line or a wireless line. The recording medium stores a program for causing the information processing device to realize a data processing function by floating-point arithmetic. The program converts integer data represented by a bit length shorter than a bit length of a floating-point register inside the information processing device into floating-point data in a predetermined format. It is possible to realize a first process of performing type conversion and loading the data in the floating-point register. In the first process, the bit length information of the integer data required for the type conversion is obtained from a bit length information register held by a first instruction instructing the first process. The information processing device can install the program via the recording medium, or can execute the program directly from the recording medium. Therefore, the information processing device can easily realize a reduction in the data capacity for the floating-point operation and an increase in the efficiency of the data processing.

The transmission medium transmits a program for causing the information processing device to realize a data processing function by floating-point arithmetic. The program converts the integer data represented by a bit length shorter than the bit length of a floating-point register inside the information processing device into a floating-point number data of a predetermined format, and It is possible to implement the first process to load the floating point register. In the first process, the bit length information of the integer data required for the type conversion is obtained from a bit length information error held by a first instruction instructing the first process. The information processing device can easily acquire the program on the network via the transmission medium. Therefore, the transmission medium enables the information processing device to easily realize a reduction in the data capacity for the floating-point operation and an increase in the efficiency of the data processing. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a single-chip data processor which is an example of a data processing device according to the present invention.

FIG. 2 is a block diagram showing an example of a conversion circuit and an alignment / extension circuit included in the data processor.

Figure 3 shows the floating-point load instruction of the data processor "FMOV. FIG. 4 is an instruction format diagram illustrating SW 2 S @Rm, FR n ". FIG. 4 is a description illustrating a data flow when the floating-point load instruction" FMOV. SW2 S @R 1, FR 4 "is executed. FIG.

FIG. 5 is a block diagram of a single-chip processor which is another example of the data processing device according to the present invention.

FIG. 6 is a block diagram of a graphic chip which is still another example of the data processing device according to the present invention.

FIG. 7 is a block diagram showing an example of a graphics system using the data processor of FIG.

FIG. 8 is an explanatory diagram exemplifying a three-dimensional model based on polygon data.

FIG. 9 is an explanatory diagram showing the data structure of a polygon string in C language notation.

FIG. 10 is a flowchart showing an example of the geometry operation processing using the data processor.

FIG. 11 is a flowchart illustrating a processing procedure that requires a change in the setting of the control register in order to switch the size of the data to be changed from the viewpoint of comparison with the processing in FIG.

FIG. 12 is a block diagram showing an example of an information processing apparatus employing the data processor of FIG. 1 and an information processing network including the same. BEST MODE FOR CARRYING OUT THE INVENTION

《Configuration of data processor》

FIG. 1 shows a single-chip data processor (hereinafter also simply referred to as a data processor) which is an example of a data processing apparatus according to the present invention. Although the data processor 1 shown in the figure is not particularly limited, it has a 32-bit reduced instruction set computer (RISC) architecture. And its instruction set includes 16-bit fixed-length floating-point instructions. The example described here is effective for controlling embedded devices that need to support 3D graphics, such as game consoles. The data processor 1 includes an instruction control circuit 2, an integer unit 3, a floating-point unit 4, an instruction cache 5, and a data cache 6.

The instruction control circuit 2 is connected to an instruction cache unit 5 via an instruction address bus 8 and an instruction bus 9. The integer unit 3 and the floating point unit 4 are connected to the data cache unit 6 via the data bus 10. Addressing for data access via data bus 10 is exclusively performed by integer unit 3, and address bus 11 is converted from integer unit 3 to data cache unit 6. It is connected.

The instruction control circuit 2 fetches an instruction from the instruction cache 5 in accordance with the execution order of the program, decodes the instruction, generates a control signal, and controls the operations of the integer unit 3 and the floating-point unit 4, etc. I do. The execution order of the programs is determined based on a value of a program counter (not shown) or an interrupt request. The instruction address is supplied from the instruction address bus 7 to the instruction cache 5, and the instruction of the instruction address is supplied from the instruction cache 5 to the instruction control circuit 2 via the instruction bus 8.

The integer unit 3 has an integer operation circuit 30, a general-purpose register file 31, and an alignment and extension circuit 32. The integer operation circuit 30 includes an arithmetic logic unit, an arithmetic unit, a shifter, and the like, and enables arithmetic operation, logical operation, and address operation of integer data. Although the general-purpose registry file 32 is not particularly limited, it has a plurality of 32-bit general-purpose registry files, and has a byte (8 bytes). It is used as a bit register, word register (16 bits), and long word (32 bits). The data bus 10 is 64 bits, though not particularly limited. The alignment / expansion circuit 32 has an aligner function for matching the bit positions of the data transmitted to the data bus having a width of 64 bits and the general-purpose register according to the data size and the like, and sign extension or logic of the data. Value "0" Has an extended function to extend. Note that a circuit configuration combining all or part of the functions of the integer unit 3 and the instruction control circuit 2 may be regarded as a so-called CPU.

The floating point unit 4 includes a floating point arithmetic circuit 40, a floating point register file 41, and a conversion circuit 42. The floating-point arithmetic circuit 40 includes a multiplier, an adder, a normalizer, and the like that enable a product-sum operation of floating-point number data. The floating-point register file 41 has a plurality of 32-bit floating-point registers. The floating-point register is used for the source data register and the destination register in floating-point operations. The floating point register is connected to the data bus 10 via the conversion circuit 42. Each floating-point register is 32 bits, and one floating-point register is used for each single-precision floating-point data. Two floating-point registers are assigned to double-precision floating-point data in pairs.

The conversion circuit 42 has an aligner function for matching the bit positions of the data transmitted to the data bus 10 having a width of 64 bits and the floating-point register according to the data size, etc. It has an extension function for sign extension or logical value "0" extension, a type conversion function for converting integer data to floating-point number data, and an inverse type conversion function for performing the reverse conversion. Details of those functions will be described later.

The data cache 6 and the instruction cache 5 are: Each is provided with a cache controller and a cache memory (not shown). The instruction cache unit 5 and the data cache unit 6 are connected to a bus controller 12 via a cache bus 11 including a data signal and a control signal. An instruction address for external access due to a cache miss or the like in the instruction cache unit 5 is given to the bus controller 12. In addition, a data address for external access caused by a cache miss in the data cache 6 is given to the path controller 12. The bus controller 12 starts an external bus cycle to access an external memory (not shown) connected to the bus interface buffer 13 via the external bus 14 in accordance with the instruction address or the data address. Control. Further, a peripheral circuit 15 such as an image controller or a serial communication interface controller is connected to the bus controller 12 via a peripheral bus 16. The data processor 1 shown in FIG. 1 is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon.

The instruction set of the data processor 1 is roughly divided into fixed-point transfer instructions, arithmetic operation instructions, logical operation instructions, branch instructions, system control instructions, floating-point instructions, and the like. As mentioned above, integer unit 3 is responsible for all addressing functions for overnight access and instruction fetching. Therefore, if the decoded instruction is a floating-point instruction (an instruction that needs to operate a floating-point unit), the instruction control circuit 2 stores the source or destination data in the integer unit 3. The floating point unit 4 instructs an addressing operation or the like for accessing the data.

As shown in Fig. 5, instruction cache unit 5 and data The nighttime processor 1B may be configured without the nighttime cache unit 6. The cache unit 17 may be used outside the processor 1B.

《Conversion circuit》

FIG. 2 shows an example of the conversion circuit 42 and the alignment / expansion circuit 32. The data input / output port of the data cache unit 6 is 64 bits, and a data access of 64 bits appears on the path 10 in the data access. The alignment and extension circuit 32 includes an aligner 33 and an extension circuit 34. The conversion circuit 42 has an aligner 43, a type conversion / inversion conversion circuit 44, and an extension circuit 45. The circuit connection state in FIG. 2 is shown assuming that data is loaded from the data cache 6 to the general-purpose register file 31 and the floating-point register file 41. The connection state in the data transfer direction where the value of the floating-point register is stored in the cache unit 6 is not shown.

When loading data into the general-purpose registry file 3 1

33 is the corresponding least significant bit in the 32-bit output of one-byte data, two-byte data, or four-byte data within the six-bit data supplied from the data bus 10. To the field. The extension circuit 34 receiving the 32 bits performs zero extension (logical value “0” extension) of the least significant one byte or the least significant two bytes of the input 32 bits to 32 bits. , Or sign extension.

When restoring data from the general-purpose registry file 31 to the data cache memory 6, although not shown in FIG. 2, the aligner 33 receives the output of the general-purpose registry Register 1 or 2, or 4 bytes in the 32-bit data supplied from the register file 31 are shifted to the corresponding least significant bit field in the 64-bit output. At this time, the extension circuit receives the 64 bits, and zero-extends, or sign-extends, one, two, or four bytes of the input 64 bits to the data bus 10. Output.

When loading data from the data cache memory 6 to the floating-point register file 41, the aligner 43 sets one byte out of the 64 bits input from the data bus 10 and 2 knots. , Or 4 bytes are shifted to the corresponding least significant bit field of the upper 32 bits or lower 32 bits of the output 64 bits. The type conversion 'reverse conversion circuit 44 receiving the 64 bits is composed of the least significant one byte or the least significant two bytes of the upper 32 bits and lower 32 bits of the input 64 bits. The upper and lower two integer data can be converted to single-precision floating-point data in parallel. The extension circuit 45 is operated in place of the operation of the type conversion / inversion conversion circuit 44, and the least significant one byte or the least significant 32 bits of the input 64 bits and the lower 32 bits of the integer data is operated. The upper two bytes from the bottom are extended (Zero extension of logical value "0") or sign extended, and transferred to the floating-point register file 41 as integer data.

When restoring data from the floating-point register file 4 1 to the data cache memory 6, although not particularly shown in FIG. 2, the type conversion / inverse conversion circuit 4 4 It converts the 4-bit upper 32-bit floating-point data and the lower 32-bit floating-point data to 1-byte or 2-byte integer data, respectively. Alternatively, it converts the input 64 bit double precision floating point number into a 32 bit integer number. The converted integer data is input to the aligner as a 64-bit data, and is placed at the lower side of the corresponding upper 32 bit and lower 32 bit bit fields, respectively. Output to cache unit 6. The operations of the conversion circuit 42 and the alignment 'extension circuit 32 are transmitted to the instruction control circuit 2. Is controlled according to the result of the instruction decoding.

FIG. 3 exemplifies "FM 0 V. SW 2 S @Rm, FRn" as a floating-point load instruction of the processor 1. The floating-point load instruction shown in the figure gives the 2-byte integer data from the cache memory of the data cache 6 to the conversion circuit 42, which converts it to single-precision floating-point data. This instruction instructs a process to load the data into a single-precision floating-point register.

In the floating-point load instruction "FMOV. SW2 S @ Rm, FR n" exemplified in FIG. 3, 50 is a main opcode (main operation code) field, 51 is an addressing mode field, and 52 is a main operation code field. Subop code (suboperation code) field, 53 is a reserve field, 54 is a source operand size field, 55 is a base register setting field, 56 is a destination register setting field, 57 is a field designated as a destination registry evening. In the example of FIG. 3, the main opcode field 50 is assigned a main opcode f1 oad indicating a floating-point load, and the addressing mode field 51 is assigned an addressing mode ri indicating a register address indirect. The subopcode field 52 is assigned the subopcode i2f, which indicates a conversion from a signed integer to a single-precision floating-point number, and the reserved field 53 is set to the zero field. A logical value "0" is assigned, a size w indicating two bytes (wo rd) is assigned to the source operand size designation field 54, and the base register evening designation field is a general-purpose register serving as a base register evening. The base register evening number m is assigned to indicate the evening number, and the destination register evening size is set in the destination register evening size field. Size s of several points cashier scan evening is assigned, the destination register evening fee Field is assigned a destination register number n. FIG. 4 illustrates a data flow when the floating-point load instruction “FMOV. SW2 S @R 1, FR 4” is executed. In the example shown in Fig. 4, the 2-byte integer 0x0003 stored at address 0x0104 (Ox means hexadecimal) is loaded into floating-point register 4 (FR4). The instruction to be executed is "FMOV. SW 2 S @R 1, FR4" as an example.

The contents of the general-purpose register 1 (R1) are the address Ox0104 of the source operand. Address 0x0100 stores a 2-byte integer 0x0001, address 0x0102 stores 0x0002, and address 0x0106 stores 0x0004.

As the first step, first, the floating-point load instruction "FMOV. SW

When 2 S @ R 1, FR 4 "is issued, the data cache unit 6 is accessed with the contents of general register R 1 as Ox 0 104 as an address, and the least significant 4 bits of 0 X 0 104 are set to zero. 8-byte (64-bit) integer data from address 0X0100 0x000 1 0002 000

3 0004 is read.

As a second step, the aligner 43 controls the alignment of the 8-byte data read from the data cache unit 6 with the value of the least significant bit 4 of the address 0 X 0 1 X4. (32 bits) is set as the offset for 8 bytes of input data (offset 4), the access size 2 (16 bits) specified by the instruction is set as the size (size 2), and the output is 64 bits. As the output position finger bit indicating whether to shift to the upper 32 bits or the lower 32 bits, 0, which is the value of the least significant bit of register number 4 of the destination register (FR4), is taken as an up-narrow. / 1 0 w 0) is input. This allows input data of 8 bytes The lower 2 bytes Ox003 from the 4 bytes (32 bits) of the offset during the output are shifted by 2 bytes from the offset 4 during the 8 bytes to the upper side. For the other output values, the 8-bit data sequence 0 X 0 0 0 1 0 0 0 3 0 0 0 3 0 0 04 is output from the aligner 43 while keeping the input values of the corresponding bit positions as they are.

As a third step, the data type conversion / inversion circuit 44 converts the 8-byte output of the aligner 43 and the conversion method from a signed 2-byte integer to a 32-bit single-precision floating-point number. A meaningful control signal is input from the instruction control circuit 2, and two 2 bytes based on the least significant bit of the upper 4 bytes and the lower 4 bytes of the input 8 bytes 0 X 0 0 3 , 0x00004 as two signed 2-byte integers, each of which is converted to a 32-bit single-precision floating-point number 0x404040000, 0x4080000 And outputs 8 bytes, two 32 bit single precision floating point numbers.

As the fourth step, finally, the upper 4 bytes of the 8 bytes output by the type conversion / inversion circuit 44 are 0x4 04 0 0 0 0 0 is the single precision floating point register 4 in the floating point register file. No. (FR4). By the above procedure, the 2-byte integer 0 X 0 0 0 3 at address 0 x 0 104 is converted to 32-bit single-precision floating-point data 0 x 4 04 0 0 0 0 0 (3.0). Is written to FR4.

In the third step, a known method is used for converting the integer data into floating-point number data, and this may be reflected in the conversion algorithm or conversion logic of the type conversion / inversion conversion circuit. For example, the sign of integer data is the sign (S) of floating-point data. Calculate the binary representation (bo b! Bb L) of the absolute value of the integer data so that the number of digits in the binary representation (L + 1) is the number of digits of the mantissa. At this time, the size information of the integer data is The instruction control circuit 2 decodes and obtains the instruction size specification field. The binary representation of the absolute value is assumed to be the mantissa before normalization (M = b _0. Bib '-b L), and normalized from the number of digits (L) of the binary representation and the exponent _value (E ₀ ). Determine previous exponents (E = E. + L) and use them to determine the unnormalized floating-point number. By normalizing this, the conversion of the integer data to a floating-point number is completed.

It should be noted that a known method may be adopted as a method of converting floating-point data into integer data in the type conversion / inversion conversion circuit 44. For example, the number of significant digits L of the mantissa M of the floating-point number is adjusted to the number of digits of the integer data, and the mantissa is transformed into M = 1. bibzbsbt. The number of digits of the integer data is obtained from the result of decoding the information indicating the bit length of the integer data included in the instruction. Exponent E Said floating Gets the value E _Q + L of the sum of the number of significant digits L of point number mantissa, if E rather E _D + L and, E = E. Shift mantissa M one digit right until + L, E + 1 and = £. Value when +! Let t ^ bgbL be the absolute value of the integer. If the sign of a floating-point number is negative, convert its absolute value to two's complement. This completes the inverse conversion.

Parallel processing of other addressing modes, other data sizes, data loading without conversion to floating-point numbers, and data loading with conversion according to the code assignment of each field of the instruction format in Fig. 3. , Etc. can be specified.

The processing when the data loading processing without conversion to the floating-point number is designated is as follows. When a code indicating that the type of the data code is a load from integer data to integer data is set in the sub code field 52 in the instruction code of FIG. This is a data load process without conversion. For example, in this case, the processing of the first and second steps is the same as that of the instruction code of FIG. The processing of the step is the processing by the extension circuit 45. That is, the data extension circuit 45 performs sign extension of, for example, the 8-byte data 0 X 000 1 000 2, 0 x 003 0004, which is the output of the aligner 43 in FIG. A control signal is input, meaning that the lower 4 bytes of the upper 4 bytes and the lower 4 bytes of the lower 8 bytes of the input 8 bytes are 0 x 00 03 and 0 x 00 04 Are two signed 2-byte integers, each of which is sign-extended to 32 bits, and outputs integer data 0 x 000 0 0 00 3 and 0 x 000 0004. Then, as a fourth step, finally, the upper 4 bytes of the 8 bytes output by the extension circuit 45 0 X 0 000 0000 3 are transferred to the single-precision floating-point register 4 (FR 4) in the floating-point register file. It is written, and the integer data of the floating-point register number 4 (FR 4) is converted to floating-point number data later by software processing or the like.

If the value of the destination register size specification field 56 is 64 bits in the instruction format shown in FIG. 3, the parallel processing of the data loading with conversion can be specified. That is, in the fourth step described in the data flow of FIG. 4, finally, the upper 4 bytes 0 x 4040 00 00 of the 8 bytes output by the type conversion / inversion circuit 44 are the floating-point register file 4 1 In the single-precision floating-point register number 4 (FR 4), and the lower 4 bytes 0 X 4 08 0 0000 are in the single-precision floating-point register number 4 (FR 5). Is written to

Another addressing mode that the floating-point load instruction can take is not limited to the above-mentioned register indirect mode, but basically the CPU's addressing mode in the data processor 1 can be freely used. The effective address is the value obtained by adding the values of the two general-purpose registers. Index indirect register indexing, post-registration register indirect mode in which the value of the general-purpose register is sequentially incremented by a predetermined value, or immediate mode in which the address is specified by an immediate value. It is possible.

《Graphic chip》

FIG. 6 shows a graphic chip which is another example of the data processing apparatus according to the present invention. The graphic chip 1C shown in the figure is composed of a processor chip 20, a program memory 21, a renderer 22, a display controller 23, a memory controller 24, a data memory 25, and a processor unit 20 in one semiconductor chip. And an external interface controller 26. The renderer 22 and the display controller 24 can be positioned as an accelerator unit for reducing the load on the processor unit 20.

The processor unit 20 includes the instruction control circuit 2, the integer unit 3, and the floating-point unit 4 of FIG. 1, and is stored in the program memory 21 constituted by an electrically rewritable flash memory or the like. The host control and the geometry operation control using floating point data are performed according to the installed program. The renderer 122 controls the image buffer rendering for the frame buffer. The display controller 23 controls the display of the image data drawn in the frame buffer. The memory controller 24 arbitrates data memory access requests from the processor unit 20, the renderer 22, and the display controller 23, and has a memory access right to the data memory 25 and a memory access interface. Control. The data memory 25 is an embedded memory composed of, for example, a synchronous DRAM, and is used as a frame buffer memory, a texture memory, a work memory, or the like. One The evening bus 10 and the data address bus 11 can be connected to the outside of the graphic chip 1C via an external interface controller 26.

《Graphic system》

FIG. 7 illustrates a graphics system configured using the data processor 1 illustrated in FIG. In FIG. 7, the main processor 60 is connected to the data processor 1, the main memory 61, a three-dimensional graphics (3DG) renderer 62, and a peripheral controller 63. The main memory 61 is used as a memory for storing data and programs required for graphics processing. The data processor 1 controls the geometry operation using floating point data. At this time, as described above, the polygon data of the three-dimensional model is stored in the main memory 61 in units of, for example, 8-bit, 16-bit, and 32-bit integer data. The data processor 1 supports the instruction shown in FIG. 3 as an instruction for loading the integer data into the floating-point register, and converts the integer data into floating-point data by the conversion circuit 42. Has a function. 3 The DG renderer 6 2 receives the result of the geometry operation from the data processor 1 and draws the display data to the frame buffer memory 70, and reads the data again in synchronization with the display timing. It also has a display control function for converting the video coder 71 into a video signal. The 3D renderer-62 can be positioned as an excel to reduce the load on the data processor 1 or to improve the processing speed.

The peripheral controller 63 controls peripheral circuits such as a audio processor 73, a DVD-ROM driver 74, and a modem 75 connected via a peripheral bus 72 based on instructions from the processor 1. Control. External control information is input to the peripheral controller 63 via the input port. Aude The audio processor 73 controls the audio synthesis processing using the audio data stored in the sound memory 76, and converts the digital audio signal into an analog signal using the digital / analog converter (DAC) 77. Convert and output to speaker etc. A DVD-ROM disk device (not shown) is connected to the DVD-ROM driver 74, and a telephone line or the like is connected to the modem 75.

Next, an example of the geometry calculation processing in the three-dimensional graphics processing using the data processing processor in FIG. 1 or the data processing system in FIG. 7 will be described.

The data processor 1 operates on polygon data that approximates a three-dimensional shape, and performs geometry operations such as affine transformation and perspective transformation for dynamically changing and displaying the three-dimensional shape. The calculation result is drawn in the frame buffer memory.

Fig. 8 shows an example of a 3D graphics model. This model data has a data format in which a three-dimensional object is approximated by a large number of polygons. (1) to (16) indicate the coordinate points of the polygon, and STRIP 80 is a generic term for the polygon row.

Fig. 9 shows the data structure of the polygon sequence in C language notation. In the figure, vx, vy, and vz are the vertex coordinates of the polygon, nx, ny, and nx are the vertex normal vectors of the polygon, a RGB is the reflectance of the surface and the intensity of the three primary colors RGB, u, V is data indicating the base coordinates of the texture data. These data exist for each coordinate point. Here, the vertex coordinate data of the polygon and the base coordinates of the texture pattern are 16-bit integer data for each component. The vertex normal vector of the polygon is 8-bit integer data for each component. The reflectance of the aRGB surface and the three primary colors of RGB The intensity of RGB is 8-bit integer data for each component. Is done.

FIG. 10 is a flowchart showing an example of the geometry calculation processing using the data processor 1. In FIG. 10, in each vertex of the polygon row, a vertex coordinate data load S1, a coordinate transformation and a corresponding transformation S2, a normal vector load S3, a color calculation S4, and a drawing information output S5 are provided. Processing is performed.

Vertex coordinate load processing S1 loads the vertex coordinate data into the floating-point register using the load instruction with the function of converting the integer data to the floating-point number described in FIG. At this time, the integer vertex coordinate data is 16 bits for each component, and the bit length information is obtained from the decoding result for the field 54 of the load instruction. Therefore, if at least one instruction is executed, floating point data of one component of the coordinate point can be obtained in the floating point register.

In the coordinate transformation and perspective transformation processing S2, the coordinates on the screen (plane) and the depth in the three-dimensional space are obtained by calculating the floating-point data of the loaded coordinate points and the coordinate transformation matrix.

Normal vector loading process In step S3, the normal vector is loaded into the floating-point register using the load instruction with the function of converting integer data to a floating-point number described in FIG. At this time, the component data of the integer normal vector is 8 bits, and the bit length information is obtained from the result of decoding the field 54 of the load instruction. Even if the bit length of the integer data changes, no special processing is required to set the change of the bit length of the integer data to be loaded in the register or the like. Therefore, by executing at least one instruction, the floating-point data of one component of the normal vector can be obtained in the floating-point register.

In the color calculation process S4, the vector of the vertex normal is The brightness of the vertices is calculated from the inner product of the converted data and the ray vector, and the color information is added to it.

In the drawing information output process S5, each of the obtained screen coordinates, depth, brightness in consideration of color, and texture coordinates is output to a memory or a renderer.

FIG. 11 shows a comparative example with the 10th processing. This processing example uses a system or a data processor that obtains the bit length of integer data from the register setting value when converting from integer data to floating point data. It is an example. Therefore, before the vertex coordinate load processing S1, the conversion data size is 16 bits (2 bytes). The processing for executing the load instruction for setting the conversion data size register to the conversion data size (2 bytes) ( S a) must be added. In the normal vector loading process, the size of the component data is 8 bits (1 byte). Therefore, before the process, a load instruction that changes the setting value of the post-conversion data size register is executed. Must be left (S b). Compared to the processing in Fig. 10, at least two more times must be performed for each operation on one polygon vertex.

FIG. 12 shows an example of an information processing device (also called a computer device) employing the data processor 1 of FIG. 1 and an example of an information processing network including the same.

The information processing network shown in Fig. 12 is a system such as a LAN (local area network), a WAN (wide area network) such as the Internet, and a wireless communication network. What is indicated by 94 means a transmission medium such as an optical fiber, an ISDN line, or a wireless line in the system. Although there is no particular limitation on the transmission medium 94, a host computer 93, a roux or evening Evening terminals 90, 91, and 92, which are typically shown via communication adapters 95, 96, and 97, are connected.

The terminal controller 90 includes, but is not limited to, the data processor (MPU) 1 and the external bus 14 includes a display controller (DIS PC) 103, a network controller (NETC) 104, and D A RAM 105 is connected, and a floppy disk controller (FDC) 100, a keyboard controller (KEYC) 101, and an integrated device are connected to the peripheral circuit 15 of the processor 1. 'A controller (I DEC) 102 is provided. The DISPC 103 controls drawing on the video RAM (VRAM) 111, and displays the drawn display data on the display (DISP) 110. The NETC 104 is connected to the communication adapter 95, and performs buffering of transmission / reception information and communication protocol control. The DRAM 105 is used for a program area and a work area of the data processor 1. A floppy disk drive 106 is connected to the FDC 100 to read information from and write information to a floppy disk 120 as an example of a recording medium. The keyboard 107 is connected to the KE YC 101. A hard disk drive (HDD) 108 and a CD-ROM drive (CD RD) 109 are connected to the IDEC 102. The HDD 108 has a magnetic disk, which is another example of the recording medium. CDRD 109 has a further example of a recording medium, CD-ROM 121. The other terminal combination devices 91 and 92 have the same configuration as described above.

For example, in the terminal combination device 90, when performing the three-dimensional graphics processing by the processing described in FIG. 10 using the load instruction FM OV, a program for the processing is executed by, for example, a user. Installed from the floppy disk 120 or CD-ROM 122 to the hard disk drive 108. At this time, the program is recorded in advance on the floppy disk 120 or the CD-ROM 122. In some cases, the set-up of the terminal viewing device may provide the program preinstalled on the hard disk drive. When executing the installed program, the data processor 1 loads the program into the DRAM 105 and fetches and executes instructions from the DRAM 105 sequentially. It is also possible to take out part of the program stored in the CD-ROM 121 directly from the CD-ROM and execute it.

Thereby, the terminal computer device 90 is connected to the floppy disk 1

The program can be installed via the device 20 or the like, or the program can be executed directly from the hard disk drive device 108 or the like. Therefore, the terminal computer device 90 can easily realize the reduction of the data capacity for the floating-point operation and the efficiency of the data processing as described above.

Further, the terminal combination device 90 can download the program from the host combination device 93. That is, the host convenience device 93 has the compressed program in a hard disk device or the like, for example. After the terminal computer 90 establishes communication with the host computer 93, the terminal computer 90 specifies the program and instructs download, whereby the program is transmitted to the transmission medium 94. Then, it is downloaded to the hard disk drive device 108 of the terminal computer device 90. The downloaded program is then decompressed and installed in a predetermined program storage area. As a result, the terminal computer 90 performs a three-dimensional graphics process using the load instruction FMOV. Noh is realized.

As described above, since the terminal computer 90 can easily acquire the program on the network via the transmission medium 94, the transmission medium 94 is provided to the terminal computer 90. This is useful for easily realizing the reduction of the data capacity for the above-mentioned floating-point operation and the efficiency of the data processing.

Note that the format of the spoken command FMOV included in such a program and the contents of the three-dimensional graphic processing using the geometry operation using polygon data are the same as those described above, Detailed description is omitted here.

According to the data processor 1 and the data processing system described above, the following operational effects can be obtained.

[1] Data processors 1, 1B and graphics chip 1C can convert integer data with a bit length shorter than that of the floating-point register into floating-point data and load it into the floating-point register. Therefore, the data amount or the data memory capacity can be reduced as compared with the case where data having the same bit length as that of the floating-point register is input. In addition, if the amount of data is reduced, the data transfer cost is also reduced, so the data processing speed is improved in a system where the data transfer cost determines the overall processing speed rather than the calculation cost. Can be done.

[2] Since the integer data can be converted to floating-point data by the conversion circuit 42 and loaded into the floating-point register, the integer data can be converted to floating-point data and loaded into the floating-point register with one instruction. be able to. [3] In the type conversion, a bit length extension process is performed according to the difference between the bit length of the integer data and the bit length of the mantissa of a predetermined floating-point format. With the conversion function described above, Since it is obtained from the decoded result of the load instruction, even when integer data having different bit lengths are mixed, processing such as the load processing involving the type conversion can be performed by one instruction. Controlling the bit length information of the integer data to be processed.Even if the bit length of the integer data to be processed changes as compared to the case where the register length is specified, unnecessary register access operation is not performed each time. Also, data processing efficiency is improved.

[4] The conversion circuit 42 can support a load instruction without a conversion function, so there is a degree of freedom to load integer data into the floating-point register and then convert it to floating-point data. .

[5] The conversion circuit supports the function of inverting the floating-point number data of the floating-point register to an integer register having a shorter bit length and storing it in the memory. The degree of freedom in data processing such as conversion can be obtained.

C 6] By incorporating a data cache unit in the data processor, data access speed by integer unit can be increased. [7] In a mode in which the conversion circuit 42 is connected to the data bus 10 to which the data cache unit 6 is connected, two bytes of integer data are converted in parallel to floating-point data. By supporting the parallel conversion function for converting data into data, it is possible to further improve the efficiency of the data loading process involving type conversion.

[8] In a data processing system in which the data processor 1 is applied to the geometry calculation in 3D graphics processing, etc., the coordinates of the vertices of the polygon and the data bits as in the normal vector Even if the lengths are different and the effect of reducing the amount of data is to be maximized, the bit length of the data to be converted is specified by the instruction, and no special control register value change operation is required. Overhead of data processing does not increase and reduction of data amount The effect of the above can be sufficiently exhibited.

[9] A storage medium storing a program that can easily reduce the data capacity for floating-point arithmetic and increase the efficiency of data processing for an information processing device, and transmission for transmitting such a program Media can be provided.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, the bit length of integer data and the bit length of floating-point data are not limited to the above description. The bit length of the floating-point register is 4 n bytes, the integer data is a bit length of n bytes or 2 n bytes, and the bit width of the data bus is 8 n bytes. The cache memory device may be capable of outputting a plurality of continuous integer data in a range of 8 n bytes to the data bus in parallel. n can be adapted as 8 bits or 16 bits.

The configuration of the built-in module and bus of the data processor is not limited to the configuration of the data processor and the graphic chip. If it is a data processor that supports virtual memory, an address conversion buffer or a memory management unit may be incorporated.

The recording medium for the program may be a medium for statically recording the program, and may be a non-volatile memory card, a DVD (digital video / disk), M0 (magnet optical), or the like. . The transmission medium may be any communication medium for electronically, electromagnetically or optically distributing or distributing a program through a network connected by a wired line or a wireless line. Industrial availability

The present invention is not limited to graphics but can also be applied to file operations in voice recognition, voice synthesis, and the like. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a signal processing device, a data processing system that performs signal processing, and an information processing network.

Claims

The scope of the claims

1. An instruction control means for decoding a fetched instruction to generate a control signal, a floating-point arithmetic circuit, an operation of which is controlled by the control signal, a floating-point register and a conversion means,

The conversion means inputs integer data represented by a bit length shorter than the bit length of the floating-point register, and converts the input integer data into floating-point data in a predetermined floating-point format. A first process of outputting the type-converted floating-point data to the floating-point register, and

The bit length information of the integer data required for the type conversion is obtained by the instruction control means decoding the bit length information area of the integer data included in the first instruction instructing the first process. De-night processing

2. The converting means further inputs integer data represented by a bit length shorter than the bit length of the floating-point register, and converts the number of bits of the input integer data into a bit of the floating-point register. A second process of extending the extended integer data to the floating-point register, and

The bit length information of the integer data necessary for extending the bit length of the integer data in the second process is obtained by transmitting the bit length information area of the integer data included in the second instruction instructing the second process to the instruction. 2. The data processing apparatus according to claim 1, wherein the control means is obtained by decoding.

3. The conversion means further inputs a floating-point number data from the floating-point register and converts the input floating-point data into the floating-point register. A third process is possible in which the inverse process is performed to convert the inverse data to integer data represented by a bit length shorter than the evening bit length and output the inverse-converted integer data, and a third instruction instructing the third process is performed. The bit length information of the integer data necessary for the inverse conversion is obtained from the result of the instruction control means decoding the bit length information of the integer data contained in the request data. 3. The data processing device according to paragraph 1 or 2.

The bit length information area indicates one of a second bit length shorter than the first bit length of the floating point register and a third bit length shorter than the second bit length. 3. The data processing device according to claim 1, wherein the data processing device can be selectively specified.

The first bit length is 32 bits, the second bit length is 16 bits, and the third bit length is 8 bits. Item 4. The data processing device according to item 4.

3. The apparatus according to claim 1, further comprising an integer unit whose operation is controlled by a control signal output from said instruction control means, and configured as a single-chip data processor. The data processing device according to the item.

7. The data processing device according to claim 6, further comprising a cache memory device connected to said integer unit and said floating point register.

8. The data processing apparatus according to claim 7, wherein said conversion means is coupled to a data bus to which said cache memory device is connected.

The floating point register has a bit length of 4 n bytes,

The integer data has a bit length of n bytes or 2 n bytes, the data bus has a bit width of 8 n bytes, The cache memory device is capable of outputting a plurality of continuous integer data in a range of 8 n bytes to the data bus in parallel,

The conversion means, based on the decoding result of the bit length information error of the integer data included in the first instruction, the first integer data on the data bus and the second integer data adjacent thereto on the data bus 9. The data processing apparatus according to claim 8, wherein the first processing is performed in parallel with the data processing.

0. A data processor capable of decoding a fetched instruction and performing a floating-point operation using a floating-point register based on the result of decoding, wherein the instruction using the floating-point register includes an instruction type. The first instruction has an operation code field, a register field specifying a floating-point register used for processing, and a field indicating other information.

In the first instruction, the operation code field indicates that integer data is to be converted into floating-point data in a predetermined floating-point format and stored in a floating-point register.

The register setting field indicates the type of the floating-point register storing the converted floating-point data,

Part of the other information field indicates the location of the integer data to be converted to floating-point data,

Another part of the other information field indicates the bit length information of the integer data represented by a bit length shorter than the bit length of the floating point register. Data processing device.

1. The instruction using the floating-point register includes an operation code field indicating the type of the instruction, a register setting field for specifying the floating-point register used for processing, and other information fields. Further comprising a second instruction having

In the second instruction, the operation code field indicates that the integer data is to be extended in bit length and stored in a floating-point register.

The register setting field indicates a type of a floating-point register for storing the converted floating-point data,

Another part of the other information field indicates bit length information of integer data represented by a bit length shorter than the bit length of the floating point register. The data processing device according to claim 10.

2. The floating point register has a bit length of 32 bits,

12. The data processing device according to claim 9, wherein the bit length information of the integer data selectively indicates an 8-bit length or a 16-bit length. .

3. A data processing system having a first data processing device and a second data processing device connected to the first data processing device, wherein the first data processing device has a fetched instruction. Instruction control means that decodes fetched instructions and generates control signals by decoding fetched instructions, integer units, floating-point arithmetic circuits, floating-point registers And converting means, wherein the converting means inputs integer data represented by a bit length shorter than the bit length of the floating-point register, and converts the input integer data into a predetermined floating-point format. Type conversion to floating point A first process of outputting the obtained floating-point data to the floating-point register;

In the type conversion, the bit length information of the integer data necessary for the bit length extension according to the difference between the bit length of the integer data and the bit length of the mantissa of the floating-point format is obtained by the first processing. The instruction control means decodes the bit length information area of the integer data included in the predetermined instruction for instructing

The data processing system according to claim 1, wherein the second data processing device is capable of performing data processing by inputting a floating-point operation result obtained by the first data processing device.

4. The first data processing device further includes a main memory connected to the first data processing device, and a cache memory capable of storing a part of storage information stored in the main memory. 14. The data processing system according to claim 13, wherein the data processing system comprises:

5. The method according to claim 13, wherein the integer data is a vertex coordinate data for approximating a three-dimensional shape and a polygon data including vertex normal data. Data processing system.

6. The floating point register has a bit length of 32 bits,

The vertex coordinate data of the polygon data has a 16-bit length for each component, and the vertex normal data has an 8-bit length for each component.

16. The data processing system according to claim 15, wherein the bit length information of the integer data selectively indicates an 8-bit length or a 16-bit length.

7. The first data processing unit uses a geometry 16. The method according to claim 15, wherein the second data processing device performs an operation, and the second data processing device performs a process of drawing data obtained by the geometry operation in a frame buffer. The data processing system described in Item 16.

18. A data processing system comprising: a central processing unit; a floating-point unit; a memory connected to the central processing unit and the floating-point unit;

The floating-point unit has a floating-point register, a floating-point arithmetic circuit, and conversion means,

The conversion means inputs integer data represented by a bit length shorter than the bit length of the floating point register into the memory, and converts the input integer data into floating point number data of a predetermined floating point number format. A first process of performing type conversion and outputting the type-converted floating-point data to the floating-point register.

The bit length information of the integer data necessary for the type conversion is obtained from the value of the bit length information area of the integer data included in the predetermined instruction instructing the first process,

The data processing system according to claim 1, wherein the accelerator is capable of performing a data process by inputting a floating-point operation result by the floating-point unit.

9.The integer data is polygon data including 16-bit vertex coordinate data of each component for approximating the three-dimensional shape and vertex normal data of each component of 8 bit length,

The floating-point register has a bit length of 32 bits, and the bit length information of the integer data selectively indicates an 8-bit or 16-bit length. Claim 18 of the claim On-board data processing system.

20.The floating-point unit performs a geometry operation using polygon data, and the x-ray processing performs a process of drawing the data obtained by the geometry operation in a frame buffer. The data processing system according to claim 19, characterized in that:

2 1.A recording medium that records a program for realizing a data processing function by a floating-point operation in an information processing device,

The program converts the integer data represented by a bit length shorter than the bit length of the floating-point register inside the information processing device into floating-point number data in a predetermined format, and converts the data into the floating-point register. The first process to load is feasible,

In the first process, the bit length information of the integer data necessary for the type conversion is obtained from a bit length information error held by a first instruction instructing the first process. recoding media.

22. The first instruction has an operation code field indicating a type of the instruction, a register specification field specifying a floating-point register used for processing, and other information fields.

The operation code field indicates that integer data is to be converted into floating-point data in a predetermined floating-point format and stored in a floating-point register.

The register designation field indicates a type of a floating-point number register for storing the converted floating-point number data,

23. The recording medium according to claim 21, wherein another part of said other information field is said bit length information area.

23.The program causes the information processing apparatus to implement a geometry operation function using polygon data, and the polygon data includes vertex coordinate data and vertex normal data for approximating a three-dimensional shape. The recording medium according to claim 21 or 22, wherein the recording medium is an integer number.

24. A transmission medium for transmitting a program for realizing a data processing function by a floating-point operation to an information processing device,

The program converts the integer data represented by a bit length shorter than the bit length of the floating-point register inside the information processing device into floating-point data in a predetermined format, and The first process to load in the evening is feasible,

In the first process, the bit length information of the integer data necessary for the type conversion is obtained from a bit length information error held by a first instruction instructing the first process. Transmission medium.

25. The first instruction has an operation code field indicating the type of the instruction, a register setting field for specifying a floating-point register used for processing, and other information fields,

A part of the other information field indicates the location of the integer data to be converted to a floating point number,

25. The transmission medium according to claim 24, wherein another part of said other information field is said bit length information area.

6. The program causes the information processing device to implement a geometry operation function using polygon data, and the polygon data includes the integers including vertex coordinate data and vertex normal data for approximating a three-dimensional shape 26. The transmission medium according to claim 24, wherein the transmission medium is overnight.