WO2001040855A1 - Lcd device and method of manufacture thereof - Google Patents

Lcd device and method of manufacture thereof Download PDF

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Publication number
WO2001040855A1
WO2001040855A1 PCT/JP2000/007834 JP0007834W WO0140855A1 WO 2001040855 A1 WO2001040855 A1 WO 2001040855A1 JP 0007834 W JP0007834 W JP 0007834W WO 0140855 A1 WO0140855 A1 WO 0140855A1
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WO
WIPO (PCT)
Prior art keywords
bus line
spacer
liquid crystal
gate bus
display device
Prior art date
Application number
PCT/JP2000/007834
Other languages
French (fr)
Japanese (ja)
Inventor
Akihiko Tateno
Mitsuaki Morimoto
Tazo Ikeguchi
Takashi Iwamoto
Masaki Ban
Hiroshi Murata
Masaaki Kubo
Original Assignee
Sekisui Chemical Co., Ltd.
Sharp Kabushiki Kaisha
Nisshin Engineering Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sekisui Chemical Co., Ltd., Sharp Kabushiki Kaisha, Nisshin Engineering Inc. filed Critical Sekisui Chemical Co., Ltd.
Publication of WO2001040855A1 publication Critical patent/WO2001040855A1/en

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1339Gaskets; Spacers; Sealing of cells
    • G02F1/13392Gaskets; Spacers; Sealing of cells spacers dispersed on the cell substrate, e.g. spherical particles, microfibres

Definitions

  • the present invention relates to a method for manufacturing a liquid crystal display device using a TFT substrate and a liquid crystal display device.
  • the general structure of a liquid crystal display device is such that a spherical sensor 8 with a diameter of about 5 / m is distributed between two electrode substrates 1 and 2 to maintain a gap.
  • the two substrates are adhered by a sealant 4 and the gap space is filled with a liquid crystal 7:
  • the distance between the pair of electrode substrates, that is, the thickness of the liquid crystal layer, affects the light transmittance. Good display cannot be achieved unless it is kept constant over the entire display area of the liquid crystal display device.
  • one of the electrode substrates is a TFT substrate 2 on which a thin film transistor (TFT) is formed, and the other is a color filter (CF) substrate 1.
  • TFT thin film transistor
  • CF color filter
  • the structure of the TFT substrate is orthogonal to the source bus line 14a (S); the gate bus line 13a (G) and the Cs common bus line 15a (Cs).
  • a transistor 18 is formed at the GS line intersection corresponding to the pixel electrode 3.
  • the C s common bus line is a wiring for connecting to the auxiliary capacitance capacitor (C s).
  • the spacers are randomly and uniformly distributed on the TFT substrate on which the pixel electrodes are formed, so that the spacers are irregularly arranged on the TFT substrate.
  • the spacer is disposed on the pixel electrode, that is, on the display unit of the liquid crystal display device.
  • the spacer is generally formed of a synthetic resin, glass, or the like, and when placed on a pixel electrode, light escapes from the spacer, so that the aperture is substantially opened. As a result, the aperture ratio was reduced, and a problem such as a decrease in luminance / contrast occurred.
  • Japanese Patent Application Laid-Open No. Heisei 4-41226 discloses that the electric attractive force is applied to select and place a spacer, thereby reducing the amount of the spacer on the pixel electrode.
  • a method for suppressing the deterioration of screen quality is disclosed. In this method, the pixel electrode on the TFT substrate is grounded, the voltage is switched between the row selection line and the column selection line, a positive voltage is applied to the wiring other than the pixel electrode, and a negatively charged spacer is sprayed there. As a result, the spacer is selectively arranged in the wiring part by electric attraction.
  • the moisture adsorbed on the TFT substrate surface causes a leak in the substrate surface potential of the TFT substrate, and the surface potential of the pixel electrode rises. That is, since the entire TFT substrate has substantially the same potential and no potential difference occurs between the pixel electrode and the wiring portion, it is difficult to selectively dispose the spacer on the wiring.
  • a TFT substrate has a configuration in which one of a row selection line and a column selection line is a gate bus line for switching transistors, and the other is a source bus line for actually applying a voltage to a pixel electrode. ing.
  • the voltage applied to the source bus line is such that, for example, the gate bus line is grounded and the transistor's off-resistance (1 to 10 ⁇ ) from the source bus line even if the transistor switch is off.
  • the surface potential of the pixel electrode also rises.
  • the present invention provides a liquid crystal display device using a TF substrate, in which a spacer is selectively scattered to provide high-quality display characteristics free from a decrease in brightness or contrast due to the spacer.
  • Manufacturing method of liquid crystal display device having the same and manufactured by the manufacturing method It is an object to provide a liquid crystal display device.
  • the first is a TFT liquid crystal display device in which a spacer is dispersed between a TFT substrate and a color filter substrate, bonded with a sealant, and liquid crystal is injected into the gap.
  • This is a method for manufacturing a liquid crystal display device, which comprises applying a voltage to the substrate and spraying a charged spacer thereon.
  • the Cs two-mon bus line is a Ge-one! ⁇
  • the step of drying the TFT substrate on which the spacer is sprayed is performed by heating the substrate before spraying the spacer, raising the substrate temperature to 100 ° C or more, It is preferable that the sheet resistance is 1 ⁇ 10 12 ⁇ or more in sheet resistance.
  • the spraying of the spacer is performed when the substrate surface resistance of the dried TF substrate is 1 X 1 ⁇ ⁇ ⁇ ⁇ or more as a sheet resistance.
  • the step of selectively arranging the spacer on the gate bus line by using the above-described electric attraction is performed by applying a negative voltage to the gate bus line and applying a negative voltage to the source bus when the sprayer is positively charged. Grounding the line and the Cs common bus line, and applying a positive voltage to the gate bus line and grounding the source bus line and the Cs common bus line when the spreader is negatively charged. I like it.
  • the step of selectively arranging the spacer on the gate bus line by using the above-mentioned electric repulsive force is as follows. In addition, when the gate bus line is grounded and the spreader is negatively charged, it is preferable to apply a negative voltage to the source bus line and the Cs common bus line, and to ground the gate bus line.
  • the step of selectively arranging the spacer on the gate bus line using the above-mentioned electric attraction and electric repulsion is performed when the spreader is positively charged.
  • a positive voltage is applied to the Cs common bus line and a negative voltage is applied to the gate bus line, and the spreader is negatively charged, a negative voltage is applied to the sense bus line and the Cs common bus line. It is preferable to apply the positive voltage to the gate bus line.
  • the gate bus line and the source bus line it is preferable to apply a voltage only to the gate bus line and the source bus line to a TFT substrate having a structure in which the Cs common bus line is common to the gate bus line.
  • the voltage applied to the gate bus line, the nonce bus line, and the Cs common bus line is such that the potential difference between the gate bus line, the source bus line, and the Cs common bus line is 30 to
  • the voltage is 60 V:
  • the charged amount of the spreader is exactly 15 to ⁇ 250 C / g or 115 to 125 CZ g. It is preferable that there is.
  • the spacer is a mature plastic adhesive spacer or a photo-curing adhesive spacer, and is preferably fixed and arranged by heating or light irradiation after being selectively arranged on the gate bus line. .
  • the line width of the gate bus line is preferably at least three times the average particle diameter of the spacer.
  • the TFT substrate is annealed at a temperature of 150 ° C. or more to compensate for the TFT characteristics.
  • the liquid crystal display device manufactured by the first present invention is also one of the present invention.
  • a liquid crystal display device in which a TFT substrate and a color filter substrate are bonded together with a spacer and a sealant therebetween, and a liquid crystal is injected into a gap therebetween.
  • the gate is selectively arranged on a gate bus line formed on a TFT substrate using electric attraction and Z or repulsion, and a line width of the gate bus line is an average of the spacer.
  • This is a liquid crystal display device that is three times or more the particle size.
  • the width of the gate bus line not covered by the pixel electrode is preferably 4 to 5 times the average particle diameter of the spacer.
  • FIG. 2 is a conceptual plan view showing the wiring of the TFT substrate used in the present invention.
  • FIG. 3 is a conceptual diagram for explaining a line width of an effective gate line in the present invention.
  • FIG. 4 is an enlarged plan view showing a state when a spacer is sprayed on the TFT substrate according to the first invention.
  • FIG. 5 is an enlarged plan view showing a state in which a spacer is sprayed on a TFT substrate by a conventional method of manufacturing a liquid crystal display device.
  • FIG. 6 is a conceptual diagram showing a structure of a general liquid crystal display device.
  • 1 to 6 1 represents an electrode substrate (CF substrate), 2 represents an electrode substrate (TFT substrate), 3 represents a pixel electrode, 4 represents a sealant, 7 represents a liquid crystal, 8 represents a spacer, 10 represents a container, 11 a represents a spray nozzle, 11 b represents a spacer supply device, 1 2 represents a voltage applying device, 13 a represents a gate bus line, 13 b represents a gate contact pad, 14 a represents a source bus line, and 14 b represents a source contact pad.
  • 15a represents the Cs common bus line
  • 15b represents the Cs contact pad
  • 16a, 16b, and 16c represent the probe pins
  • Reference numeral 17 denotes a spray pipe
  • 18 denotes a transistor
  • 19 denotes a gap between pixel electrodes
  • 20 denotes an insulating film.
  • a spacer is dispersed and arranged between a TFT substrate having been subjected to an alignment treatment and a filter substrate and bonded with a sealant, and a liquid crystal is filled in the gap.
  • a method of manufacturing a TFT liquid crystal display device by injecting, wherein a step of drying a TFT substrate on which a spacer is sprayed, and a step of forming a spacer by using an electric attraction and / or an electric repulsion. And selectively arranging them on the bus line.
  • the step of drying the TFT substrate on which the spacer is sprayed is performed by heating the substrate before spraying the spacer, and raising the substrate temperature to 100 ° C.
  • the substrate surface resistance is preferably 1 ⁇ 10 12 ⁇ / port or more in sheet resistance. ⁇ F ⁇ ⁇ As the temperature of the substrate rises, the amount of adhering water decreases, so the resistance on the substrate surface increases, no current leaks, and stable placement of the sensor can be performed stably. Become like More preferably, the substrate temperature is 120 to 150 ° C., and the substrate surface resistance is 1 ⁇ 10 12 to 1 ⁇ 10 14 ⁇ / cm2 in sheet resistance.
  • the TFT substrate can be heated by a hot plate, a hot-air circulation oven, an infrared furnace, or the like.
  • the TFT substrate When a hot plate is used in the step of drying the TFT substrate, the TFT substrate may be brought into close contact with the hot plate heated to 120 C for 5 minutes or more.
  • a spacer is sprayed on the second TFT substrate.
  • the sprayer is sprayed, and the substrate surface resistance of the dried TFT substrate is 1 ⁇ 1 in sheet resistance. If the substrate surface resistance of the TFT substrate is less than 1 ⁇ 10 "0 in sheet resistance, current may leak on the TFT substrate and a spacer may be formed. May not be able to be selected and placed with high accuracy. More preferably, it carried out at 1 X 1 o u ⁇ 1 X 1 ⁇ 14 ⁇ in sheet resistance. In order to prevent moisture from re-adhering to the substrate surface after drying, it is preferable to spray a spacer within 5 minutes after drying or to fill the inside of the spraying device with dry nitrogen.
  • the step of selectively arranging a sensor on the gate bus line by using the above-described electric attraction and ⁇ or electric repulsion includes the step of forming the gate bus line and the source bus line formed on the TFT substrate. A voltage is individually applied to each of the wires, and a charged spacer is sprayed there.
  • the Cs common bus line is a TFT substrate that is not common to the gate bus line
  • a voltage is individually applied to each of the gate bus line, the source bus line, and the Cs common bus line.
  • the method of selectively arranging the spacer on the gate bus line using the above-mentioned electric attraction is to apply a negative voltage to the gate bus line when the spacer to be sprayed is positively charged, and to apply the negative voltage to the source bus line and the source bus line. Ground the Cs common bus line.
  • the method of selectively arranging the spacer on the gate bus line by using the above-mentioned electric repulsive force is as follows. When the scattered sensor is positively charged, a positive voltage is applied to the source bus line and the Cs common bus line. And ground the gate bus line. When the spreader is negatively charged, a negative voltage is applied to the source bus line and the Cs common bus line, and the gate bus line is grounded.
  • the method of selectively arranging the bus on the gate bus line by using the above-mentioned electric attraction and electric repulsion is as follows.
  • the source bus line and the Cs common bus line are used. Apply a positive voltage to, and apply a negative voltage to the gate bus line.
  • the spreader is negatively charged, a negative voltage is applied to the source bus line and the Cs common bus line, and a positive voltage is applied to the gate bus line.
  • a TFT substrate having a structure in which the Cs common bus line is common to the gate bus line can be used.
  • the spacer is effective. Specifically, it can be selectively arranged on the gate bus line.
  • the voltage applied to the gate bus line, the single bus line, and the Cs common bus line is such that the potential difference between the gate bus line, the source bus line, and the Cs common bus line is 30 to It is preferably 60 V. Among them, the potential difference is more preferably about 40 V.
  • the amount of charge of the spacer sprayed in the invention is preferably 125500 / ic / g or 15250C / g. More preferably, the charge amount measured by a suction type Faraday gauge is 15 + 200 CZg or
  • the optimum charge amount is subdivided depending on the specific gravity of the above-mentioned sensor and the particle diameter.
  • a preferable charge amount is 15 to 60 CZg or -156 C / g.
  • the suitable charge amount is T 20 ⁇ 80 C / g or ⁇ 2080 ⁇ C / g, and when the particle size is 3.0 zm, The appropriate charge amount is ⁇ 520 ⁇ C / g or 150 ⁇ C / g. If the charge amount of the above-mentioned spacer is too small or too large, inconvenience occurs.
  • the spacer used in the first present invention is a thermoplastic adhesive spacer or a photo-curing adhesive spacer, which is selectively arranged on a gate bus line and then bonded by heating or light irradiation. Preferably, it is fixed.
  • thermoplastic adhesive spacer or photo-curable adhesive spacer is used to bond and fix the spacer on the gate bus line.
  • the spacer is prevented from moving on the gate bus line.
  • the line width of the gate bus line formed on the TFT substrate is preferably at least three times the average particle diameter of the spacer.
  • the spacer can be effectively arranged on the gate bus line. More preferably, it is 45 times.
  • the line width of the gate bus line is at least 15 m, and preferably about 20 to 25 / im.
  • the selection arrangement ratio is reduced, the gate bus line is deviated from the gate bus line, and the gate line is disposed on the pixel electrode. May increase. This is because repulsive force is exerted between the sensor placed first on the gate bus line and the later-distributed spacer because the spacers have the same polarity potential. This is because it is difficult to work and fit in a narrow space.
  • a method of improving the selective placement ratio of the gate is as follows. There is a method in which the potential difference between the common bus line and the common bus line is set slightly higher at 50 to 60 V. At this voltage, the characteristic shift of the transistor described above starts to occur, but with this level of characteristic shift, the TFT substrate should be annealed at 150 ° C or higher for about 1 hour after spraying. As a result, the TFT characteristics are restored.
  • the TFT substrate after spraying the spacer, can be annealed at a temperature of 150 ° C. or more to compensate for the TFT characteristics. More preferably, annealing is performed at about 20 ° C.
  • the two substrates are bonded together to cure the sealant. It is annealed automatically for firing for about an hour.
  • a TFT substrate on which a sensor is selectively arranged as described above and a CF substrate are bonded and adhered with a sealant, and a liquid crystal is filled in a gap between the substrates to form a liquid crystal display.
  • the device is manufactured.
  • the first aspect of the present invention has the above-described configuration, it is possible to provide a liquid crystal display device having high-quality display characteristics without a decrease in brightness or contrast due to a speaker.
  • the liquid crystal display device manufactured according to the first aspect of the present invention is also one aspect of the present invention.
  • the second invention is a liquid crystal display device in which a TFT substrate and a color filter substrate are bonded together with a spacer and a sealant interposed therebetween, and a liquid crystal is injected into a gap therebetween.
  • the spacer is selectively disposed on a gate bus line formed on a TFT substrate by using an electric attractive force and Z or a repulsive force, and the line width of the gate bus line is This is a liquid crystal display device with an average particle diameter of three times or more.
  • the width of the gate bus line that is not covered by the pixel electrode corresponds to the effective gate bus line width.
  • the width of the gate bus line that is not covered with the pixel electrode is 4 to 5 times the average particle diameter of the spacer because the spacer is effectively selected and arranged on the gate bus line. Is preferred.
  • the second invention can be manufactured, for example, by using the first invention.
  • FIG. 1 is a conceptual diagram showing a sprinkler spray device used in the present invention.
  • a nozzle 11 a for spraying the charged spacer 8 is provided at the upper end of the container 10.
  • An apparatus 11 b for supplying a spacer 8 is connected to the spray nozzle 11 a via a spray pipe 17.
  • a TFT substrate 2 on which a gate bus line, a source bus line, and a Cs common bus line are formed is provided below the container 10.
  • the probe pins 16a, 16b, and 16c are individually contacted with the gate bus line, source bus line, and Cs common bus line of the TFT substrate 2, respectively.
  • a voltage is applied to the TFT substrate 2 and the charged spacers 8 are sprayed on the TFT substrate 2 to select the spacers 8 on the gate bus line using electric attraction and electric or repulsion. Place
  • the method of charging the base 8 is as follows: the spraying pipe 17 and the spraying nozzle 11a shown in FIG. 1 are made of stainless steel, Teflon, Nymouth or urethane resin. When the spreader 8 passes through the spraying pipe 17 and the spraying nozzle 11 a, the charge generated by friction is used.
  • a charging gun method using corona discharge is not preferable.
  • the potential of the spacer is too high, and the repulsion between the controllers is strong. Therefore, the arrangement on the game bus line is deteriorated.
  • FIG. 2 is a conceptual diagram showing a wiring structure of a TFT substrate which is not invented.
  • a gate contact pad 13b for applying a voltage to the gate bus line 13a a source contact pad 14b for applying a voltage to the source bus line 14a
  • a C s dimon pad 15 b for applying a voltage to the C s common bus line 15 a is provided, and here the Pc-pins 16 a, 16 b, and 16 c shown in FIG. 1 are provided.
  • Each is contacted.
  • These contact pads may be provided at a plurality of points on one TFT substrate in order to facilitate wiring or to reduce wiring resistance, and may be combined at one point.
  • FIG. 3 is a conceptual diagram for explaining the effective gate bus line width in the invention.
  • the pixel electrode 3 is formed on the insulating film 20 formed on the gate bus line 13a.
  • the gate bus line 13a is disposed so as to cover the gate bus line 13a to make the display area large.
  • the gap 19 between the pixel electrodes corresponds to the effective line width of the gate bus line.
  • the effective width of the gate bus line is at least three times the average particle diameter of the spacer in order to effectively select and place the spacer on the gate bus line. Is preferred. BEST MODE FOR CARRYING OUT THE INVENTION
  • Gate bus lines were formed and patterned on a transparent glass substrate, and then a gate insulating film was formed. Furthermore, the TFT electrode was formed by performing film formation and patterning operations on the pixel electrode, the source bus line, and the Cs common bus line, respectively.
  • the electrode pattern of the TFT substrate was formed as shown in Fig. 2, and the line width of the gate bus line was about 20 m.
  • a common electrode substrate for a TFT type liquid crystal display was prepared as a CF substrate. These two substrates were subjected to an orientation treatment.
  • a spacer A thermoplastic spacer having an average particle size of about 5 ⁇ m was prepared.
  • the prepared TFT substrate was adhered to a hot plate heated to 120 ° C. for 10 minutes. After the drying process, the substrate surface resistance of the TFT substrate was 1 ⁇ 10 " ⁇ in sheet resistance. Immediately after the drying process, the TFT substrate was set on the spraying device shown in FIG. As a result, a positive voltage was applied to the gate bus line on the TFT substrate, the source bus line and the Cs common bus line were grounded, and the spacer was negatively charged and sprayed. The potential difference between the source bus line and the Cs common bus line was 43 V.
  • the results of observing the TFT substrate on which the spacers were sprayed with an optical microscope are shown in FIG. Most spacers 8 were selectively arranged on the gate bus line 13a.
  • the TFT substrate was subjected to a heat treatment, and the spacer was bonded and fixed.
  • a liquid crystal display device was manufactured through the steps of seal formation, bonding, substrate cutting, and liquid crystal injection.
  • the obtained liquid crystal display has high contrast and good display characteristics because there is no light leakage due to the spacer.
  • Example 2 The operation was performed in the same manner as in Example 1 except that a negative voltage was applied to the source bus line and the Cs common bus line, and the gate bus line was grounded. At this time, the potential difference between the gate bus line on the substrate, the source bus line and the Cs common bus line was 39 V.
  • Example 1 The drying step was omitted in Example 1, or the heating time in the drying step was 5 minutes, and the heating temperature was 80. C.
  • a liquid crystal display device was manufactured in the same manner as in Example 1 except that the temperature was changed to 100 ° C. or 120 ° C.
  • Table 1 shows the relationship between the substrate heating temperature and the spraying rate of the spreader in this case. According to Table 1, when the TFT substrate is heated to 100 ° C or more, about 90% or more of the spacers are selectively arranged on the gate bus line. The display characteristics of the device were extremely good.
  • the present invention has the above-described configuration, in a liquid crystal display device using a TFT substrate, a spacer on a pixel electrode is eliminated or greatly reduced, and luminance due to the spacer is reduced. It is possible to provide a liquid crystal display device having high quality display characteristics without a decrease or a decrease in nintrast.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Optics & Photonics (AREA)

Abstract

A high-quality LCD using a TFT substrate, in which spacers are scattered selectively to prevent the spacers from causing decreases in brightness and contrast. According to a method of the invention, a TFT substrate and a color filter substrate are joined with spacers scattered and liquid crystal sealed between them. The method comprises the steps of drying a TFT substrate on which spacers are scattered, and selectively arranging spacers on gate bus lines by means of electrical attraction and/or repulsion. The step of selectively arranging spacers on gate bus lines by means of electrical attraction and/or repulsion includes applying voltage to the individual conductors of gate bus lines and source bus lines and scattering charged spacers.

Description

明細書  Specification
液晶表示装置の製造方法及び液晶表示装置 技術分野  Liquid crystal display device manufacturing method and liquid crystal display device
本発明は、 T F T基板を用いた液晶表示装置の製造方法及び液晶表示装置に関 する。 背景技術  The present invention relates to a method for manufacturing a liquid crystal display device using a TFT substrate and a liquid crystal display device. Background art
一般的な液晶表示装置の構造は、 図 6に示すように、 2枚の電極基板 1 、 2の 間に直径約 5 / mの球状のスべ一サ 8を分散配置してギャップが保たれ、 両基板 はシール剤 4により接着されており、 ギャップ空間には液晶 7が充填されている: この一対の電極基板の間隔、 即ち液晶層の層厚は、 光透過率に影響を及ぼすため に、 液晶表示装置の表示領域の全域にわたって一定に保たれなければ良好な表示 を行うことができなレ、。  As shown in Fig. 6, the general structure of a liquid crystal display device is such that a spherical sensor 8 with a diameter of about 5 / m is distributed between two electrode substrates 1 and 2 to maintain a gap. The two substrates are adhered by a sealant 4 and the gap space is filled with a liquid crystal 7: The distance between the pair of electrode substrates, that is, the thickness of the liquid crystal layer, affects the light transmittance. Good display cannot be achieved unless it is kept constant over the entire display area of the liquid crystal display device.
T F T液晶表示装置においては、 上記電極基板の一方が薄膜トランジスタ (T F T) が形成された T F T基板 2で、 他方がカラ一フィルタ (C F ) 基板 1であ る。 T F T液晶表示装置は、 T F T基板 2と C F基板 1 とに配向処理を施した後、 2枚の基板の間にスべ一サ 8を分散配置させ、 シール剤 4で貼り合わせて、 間隙 に液晶 7を充填することにより製造される。  In the TFT liquid crystal display device, one of the electrode substrates is a TFT substrate 2 on which a thin film transistor (TFT) is formed, and the other is a color filter (CF) substrate 1. In the TFT liquid crystal display device, after subjecting the TFT substrate 2 and the CF substrate 1 to an orientation treatment, a sensor 8 is dispersed and arranged between the two substrates, and the substrates are bonded with a sealant 4, and a liquid crystal is provided in the gap. Manufactured by filling 7.
T F T基板の構造は、 図 2に示すようにソースバスライン 1 4 a ( S ) 力;, ゲ —トバスライン 1 3 a (G) 及び C s コモンバスライン 1 5 a (C s ) と直交配 置されており、 画素電極 3に対応して G— Sライン交点にトランジスタ 1 8が形 成されている。 なお、 C s コモンバスラインとは、 補助容量コンデンサ ( C s ) に接続するための配線である。  As shown in Fig. 2, the structure of the TFT substrate is orthogonal to the source bus line 14a (S); the gate bus line 13a (G) and the Cs common bus line 15a (Cs). A transistor 18 is formed at the GS line intersection corresponding to the pixel electrode 3. The C s common bus line is a wiring for connecting to the auxiliary capacitance capacitor (C s).
従来の T F T液晶表示装置の製造方法では、 画素電極が形成された T F T基板 上に、 スぺーサをランダムかつ均一に散布するため、 スぺ一サは T F T基板上に 不規則に配置され、 多くのスぺーサが画素電極上、 即ち、 液晶表示装置の表示部 に配置されてしまう。 スぺ一サは、 一般的に合成樹脂やガラス等から形成されて おり、 画素電極上に配置されるとスぺ一サから光抜けが生じるために実質上の開 口率を低下させることとなり、 輝度ゃコントラス トを低下させるといった問題が 発生していた。 In the conventional method of manufacturing a TFT liquid crystal display device, the spacers are randomly and uniformly distributed on the TFT substrate on which the pixel electrodes are formed, so that the spacers are irregularly arranged on the TFT substrate. The spacer is disposed on the pixel electrode, that is, on the display unit of the liquid crystal display device. The spacer is generally formed of a synthetic resin, glass, or the like, and when placed on a pixel electrode, light escapes from the spacer, so that the aperture is substantially opened. As a result, the aperture ratio was reduced, and a problem such as a decrease in luminance / contrast occurred.
この問題を解決する方法—として、 特開平 4一 4 2 1 2 6号公報には、 電気的引 力を^いてスべ一サを選択配置することで画素電極上のスべ一サを減らし、 画面 品位の低下を抑える方法が開示されている。 この方法では、 T F T基板上の画素 電極をアースし、 行選択線と列選択線の電圧切替えを行って画素電極以外の配線 部に正電圧を印加し、 そこに負帯電させたスベーサを散布することで、 電気的引 力によりスぺーサを配線部に選択的に配置する。  As a method for solving this problem, Japanese Patent Application Laid-Open No. Heisei 4-41226 discloses that the electric attractive force is applied to select and place a spacer, thereby reducing the amount of the spacer on the pixel electrode. A method for suppressing the deterioration of screen quality is disclosed. In this method, the pixel electrode on the TFT substrate is grounded, the voltage is switched between the row selection line and the column selection line, a positive voltage is applied to the wiring other than the pixel electrode, and a negatively charged spacer is sprayed there. As a result, the spacer is selectively arranged in the wiring part by electric attraction.
しかし、 上述の方法を用いて T F T基板の配線に電圧を印加すると、 T F T基 板表面に吸着した水分により T F T基板の基板表面電位にリークが生じ、 画素電 極の表面電位 上昇する。 即ち、 T F T基板全体がほ 同電位になって画素電極 と配線部との間に電位差が生じないため、 スぺ一サを選択的に配線上に配置する ことが困難であった。  However, when a voltage is applied to the wiring of the TFT substrate using the method described above, the moisture adsorbed on the TFT substrate surface causes a leak in the substrate surface potential of the TFT substrate, and the surface potential of the pixel electrode rises. That is, since the entire TFT substrate has substantially the same potential and no potential difference occurs between the pixel electrode and the wiring portion, it is difficult to selectively dispose the spacer on the wiring.
また、 一般的な T F T基板の構成は、 行選択線と列選択線とのいずれか一方が トランジスタのスィツチングを行うゲ一トバスラインで、 他方が画素電極へ実際 に電圧を印加するソースバスラインとなっている。 この T F T基板において、 ソ —スバスラインに印加した電圧は、 例えばゲートバスラインをアースし、 トラン ジスタのスィツチがオフ状態であっても、 ソースバスラインから トランジスタの オフ抵抗 (1〜 1 0 Μ Ω ) を通じて、 又は、 C s コモンバスラインから C sコン デンサを介して、 画素電極の表面電位も上昇する。 そのため、 上述の方法のよう に、 毎秒 5〜3 0回の割合で行選択線と列選択線の電圧切替えを行った場合、 ン —スバスラインの電圧に引きずられて画素電極の表面電位も上昇し、 画素電極と ソースバスライン上との電位差がなくなり、 スぺーサを選択的に配置する効果が 不充分となる欠点があった。 発明の要約  In general, a TFT substrate has a configuration in which one of a row selection line and a column selection line is a gate bus line for switching transistors, and the other is a source bus line for actually applying a voltage to a pixel electrode. ing. In this TFT substrate, the voltage applied to the source bus line is such that, for example, the gate bus line is grounded and the transistor's off-resistance (1 to 10 Ω) from the source bus line even if the transistor switch is off. , Or from the Cs common bus line through the Cs capacitor, the surface potential of the pixel electrode also rises. Therefore, when the voltage is switched between the row selection line and the column selection line at a rate of 5 to 30 times per second as in the above-described method, the surface potential of the pixel electrode is increased by being dragged by the voltage of the source bus line. However, the potential difference between the pixel electrode and the source bus line disappears, and the effect of selectively arranging the spacer is insufficient. Summary of the Invention
本発明は、 上記に鑑み、 T F Τ基板を用いた液晶表示装置において、 スぺーサ を選択的に散布し、 スぺ一サによる輝度低下やコン トラス ト低下がない、 高品位 の表示特性をもった液晶表示装置の製造方法及びその製造方法により製造される 液晶表示装置を提供することを目的とする。 SUMMARY OF THE INVENTION In view of the above, the present invention provides a liquid crystal display device using a TF substrate, in which a spacer is selectively scattered to provide high-quality display characteristics free from a decrease in brightness or contrast due to the spacer. Manufacturing method of liquid crystal display device having the same and manufactured by the manufacturing method It is an object to provide a liquid crystal display device.
第 1の本癸明は、 T F T基板とカラ一フィルタ基板との間にスぺ一サを分散配 置してシール剤で貼り合わせ、 その間隙に液晶を注入することよりなる T F T液 晶表示装置の製造方法であって、 スぺ一サが散布される T F T基钣を乾燥させる 工程と、 電気的引力及び Z又は電気的斥力を用いてスベーサをゲー トバスライン 上に選択配置する工程とからなり、 前記電気的引力及び Z又は電気的斥力を用い てスベ一サをゲ一トバスライン上に選択配置する工程は、 T F T基板上に形成さ れたゲ一卜バスライン及びソースバスラインの各配線に個別に電圧を印加し、 そ こに帯電させたスベーサを散布することよりなる液晶表示装置の製造方法である。 第 1の本発明においては、 C s二モンバスラインが、 ゲ一! ^バスラインと共通 でない T F T基板の場合は、 ゲートバスライン、 ソースバスライン及び C s コモ ンバスラインの各配線に個別に電圧を印加することが好ましレ、。  The first is a TFT liquid crystal display device in which a spacer is dispersed between a TFT substrate and a color filter substrate, bonded with a sealant, and liquid crystal is injected into the gap. A method of drying the TFT substrate on which the spacers are sprayed, and a step of selectively disposing the spacers on the gate bus line using electric attraction and Z or electric repulsion, The step of selectively arranging the spacer on the gate bus line using the electric attraction and Z or the electric repulsion is performed separately for each of the gate bus line and the source bus line formed on the TFT substrate. This is a method for manufacturing a liquid crystal display device, which comprises applying a voltage to the substrate and spraying a charged spacer thereon. In the first aspect of the present invention, the Cs two-mon bus line is a Ge-one! ^ In the case of TFT substrates that are not common to bus lines, it is preferable to apply voltages individually to the gate bus line, source bus line, and Cs common bus line.
上記スぺ一サが散布される T F T基板を乾燥させる工程は、 スぺーサを散布す る前に基板を加熱することにより行い、 基板温度を、 1 0 0 °C以上に上昇させ、 基板表面抵抗を、 シート抵抗で 1 X 1 0 12 Ω Ζ口以上とすることが好ましい。 The step of drying the TFT substrate on which the spacer is sprayed is performed by heating the substrate before spraying the spacer, raising the substrate temperature to 100 ° C or more, It is preferable that the sheet resistance is 1 × 10 12 Ω or more in sheet resistance.
第 1の本発明において、 スぺ一サの散布は、 乾燥させた T F Τ基板の基板表面 抵抗が、 シ一ト抵抗で 1 X 1 Ο ^ Ω Ζ Π以上にて行うことが好ましい。  In the first aspect of the present invention, it is preferable that the spraying of the spacer is performed when the substrate surface resistance of the dried TF substrate is 1 X 1 Ο ^ Ω で or more as a sheet resistance.
上記電気的引力を用いてスぺーサをゲ一トバスライン上に選択的に配置するェ 程は、 散布するスベ一サが正帯電のときには、 ゲートバスラインに負電圧を印加 し、 かつ、 ソースバスライン及び C s コモンバスラインをアースし、 散布するス ベーサが負帯電のときには、 ゲートバスラインに正電圧を印加し、 かつ、 ソース バスライン及び C sコモンバスラインをアースすることよりなることが好ましレ、。 上記電気的斥力を用いてスベーサをゲ一トバスライン上に選択的に配置するェ 程は、 散布するスぺ一サが正帯電のときには、 ン一スバスライン及び C s コモン バスラインに正電圧を印加し、 かつ、 ゲートバスラインをアースし、 散布するス ぺーサが負帯電のときには、 ソースバスライン及び C s コモンバスラインに負電 圧を印加し、 かつ、 ゲー トバスラインをアースすることよりなることが好ましレ、。 上記電気的引力及び電気的斥力を用いてスベーサをゲ一トバスライン上に選択 的に配置する工程は、 散布するスぺ一サが正帯電のときには、 ソースバスライン 及び C s コモンバスラインに正電圧を印加し、 かつ、 ゲートバスラインに負電圧 を印加し、 散布するスぺ一サが負帯電のときには、 ン一スバスライン及び C sコ モンバスラインに負電圧を印加し、 かつ、 ゲ一 バスラインに正電圧を印加する ことよりなることが好ましい。 The step of selectively arranging the spacer on the gate bus line by using the above-described electric attraction is performed by applying a negative voltage to the gate bus line and applying a negative voltage to the source bus when the sprayer is positively charged. Grounding the line and the Cs common bus line, and applying a positive voltage to the gate bus line and grounding the source bus line and the Cs common bus line when the spreader is negatively charged. I like it. The step of selectively arranging the spacer on the gate bus line by using the above-mentioned electric repulsive force is as follows. In addition, when the gate bus line is grounded and the spreader is negatively charged, it is preferable to apply a negative voltage to the source bus line and the Cs common bus line, and to ground the gate bus line. Masure, The step of selectively arranging the spacer on the gate bus line using the above-mentioned electric attraction and electric repulsion is performed when the spreader is positively charged. When a positive voltage is applied to the Cs common bus line and a negative voltage is applied to the gate bus line, and the spreader is negatively charged, a negative voltage is applied to the sense bus line and the Cs common bus line. It is preferable to apply the positive voltage to the gate bus line.
第 1の本発明において、 C sコモンバスラインが、 ゲートバスラインと共通で ある構造の T F T基板に対しては、 ゲートバスラインとソースバスラインとにの み電圧を印加することが好ましい。  In the first aspect of the present invention, it is preferable to apply a voltage only to the gate bus line and the source bus line to a TFT substrate having a structure in which the Cs common bus line is common to the gate bus line.
第 1の本発明において、 ゲートバスラインと、 ン一スバスライン及び C sニモ ンバスラインとに印加する電圧は、 ゲートバスラインと、 ソースバスライン及び C s コモンバスラインとの間の電位差が 3 0〜 6 0 Vであることが好ましい: 第 1の本発明において、 散布されるスベ一サの帯電量は、 丁 1 5〜^ 2 5 0 C / g又は一 1 5〜一 2 5 0 C Z gであることが好ましレヽ。  In the first aspect of the present invention, the voltage applied to the gate bus line, the nonce bus line, and the Cs common bus line is such that the potential difference between the gate bus line, the source bus line, and the Cs common bus line is 30 to Preferably, the voltage is 60 V: In the first aspect of the present invention, the charged amount of the spreader is exactly 15 to ^ 250 C / g or 115 to 125 CZ g. It is preferable that there is.
上記スぺ一サは、 熟可塑性の接着性スベーサ又は光硬化性の接着性スぺーサで あって、 ゲートバスライン上に選択配置された後、 加熱又は光照射によって接着 固定されることが好ましい。  The spacer is a mature plastic adhesive spacer or a photo-curing adhesive spacer, and is preferably fixed and arranged by heating or light irradiation after being selectively arranged on the gate bus line. .
上記ゲートバスラインの線幅は、 スぺーサの平均粒子径の 3倍以上であること が好ましい。  The line width of the gate bus line is preferably at least three times the average particle diameter of the spacer.
第 1の本発明;こおいては、 スベーサを散布後、 T F T基板を 1 5 0 °C以上の温 度でァニールして T F T特性の補償を行うことが好ましい。  In the first present invention, it is preferable that after spraying the spacer, the TFT substrate is annealed at a temperature of 150 ° C. or more to compensate for the TFT characteristics.
第 1の本発明により製造されてなる液晶表示装置もまた、 本発明の 1つである。 第 2の本発明は、 T F T基板とカラ一フィルタ基板とを、 スぺーサ及びシール 剤を介在させて貼り合わせ、 その間隙に液晶を注入してなる液晶表示装置であつ て、 前記スぺ一サは、 T F T基板上に形成されたゲートバスライン上に電気的引 力及び Z又は斥力を用いて選択的に配置されたものであり、 前記ゲ一トバスライ ンの線幅は、 前記スベーサの平均粒径の 3倍以上である液晶表示装置である。 第 2の本発明においては、 画素電極が被さっていないゲートバスラインの幅が、 スベーサの平均粒径の 4〜 5倍であることが好ましい。 図面の簡単な説明 第 1図は、 本発明において用いるスベーサ散布装置の概念図である。 The liquid crystal display device manufactured by the first present invention is also one of the present invention. According to a second aspect of the present invention, there is provided a liquid crystal display device in which a TFT substrate and a color filter substrate are bonded together with a spacer and a sealant therebetween, and a liquid crystal is injected into a gap therebetween. The gate is selectively arranged on a gate bus line formed on a TFT substrate using electric attraction and Z or repulsion, and a line width of the gate bus line is an average of the spacer. This is a liquid crystal display device that is three times or more the particle size. In the second aspect of the present invention, the width of the gate bus line not covered by the pixel electrode is preferably 4 to 5 times the average particle diameter of the spacer. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a conceptual diagram of a spacer application device used in the present invention.
第 2図は、 本発明において用いる T F T基板の配線を示す平面概念図である。 第 3図は、 本発明における有効なゲートラインの線幅を説明するための概念図 である。  FIG. 2 is a conceptual plan view showing the wiring of the TFT substrate used in the present invention. FIG. 3 is a conceptual diagram for explaining a line width of an effective gate line in the present invention.
第 4図は、 第 1の本発明により T F T基板にスぺーサを散布したときの状態を 示した平面拡大図である。  FIG. 4 is an enlarged plan view showing a state when a spacer is sprayed on the TFT substrate according to the first invention.
第 5図は、 従来の液晶表示装置の製造方法により T F T基板にスベーサを散布 したときの状態を示した平面拡大図である。  FIG. 5 is an enlarged plan view showing a state in which a spacer is sprayed on a TFT substrate by a conventional method of manufacturing a liquid crystal display device.
第 6図は、 一般的な液晶表示装置の構造を示す概念図である。  FIG. 6 is a conceptual diagram showing a structure of a general liquid crystal display device.
第 1図〜第 6図において、 1は、 電極基板 (C F基板) を表し、 2は、 電極基 板 (T F T基板) を表し、 3は、 画素電極を表し、 4は、 シール剤を表し、 7は, 液晶を表し、 8は、 スぺ一サを表し、 1 0は、 容器を表し、 1 1 aは、 散布ノズ ルを表し、 1 1 bは、 スぺーサ供給装置を表し、 1 2は、 電圧印加装置を表し、 1 3 aは、 ゲートバスラインを表し、 1 3 bは、 ゲートコンタク トパッドを表し、 1 4 aは、 ソースバスラインを表し、 1 4 bは、 ソースコンタク トパッ ドを表し、 1 5 aは、 C s コモンバスラインを表し、 1 5 bは、 C sコンタク トパッドを表 し、 1 6 a、 1 6 b、 及び、 1 6 cは、 プローブピンを表し、 1 7は、 散布配管 を表し、 1 8は、 トランジスタを表し、 1 9は、 画素電極の隙間を表し、 2 0は、 絶縁膜を表す。 発明の詳細な開示  1 to 6, 1 represents an electrode substrate (CF substrate), 2 represents an electrode substrate (TFT substrate), 3 represents a pixel electrode, 4 represents a sealant, 7 represents a liquid crystal, 8 represents a spacer, 10 represents a container, 11 a represents a spray nozzle, 11 b represents a spacer supply device, 1 2 represents a voltage applying device, 13 a represents a gate bus line, 13 b represents a gate contact pad, 14 a represents a source bus line, and 14 b represents a source contact pad. 15a represents the Cs common bus line, 15b represents the Cs contact pad, 16a, 16b, and 16c represent the probe pins, Reference numeral 17 denotes a spray pipe, 18 denotes a transistor, 19 denotes a gap between pixel electrodes, and 20 denotes an insulating film. Detailed Disclosure of the Invention
以下に本発明を詳述する。  Hereinafter, the present invention will be described in detail.
第 1の本発明の液晶表示装置の製造方法は、 配向処理を施した T F T基板と力 ラ一フィルタ基板との間にスぺーサを分散配置してシール剤で貼り合わせ、 その 間隙に液晶を注入することよりなる T F T液晶表示装置の製造方法であって、 ス ぺ一サが散布される T F T基板を乾燥させる工程と、 電気的引力及び/又は電気 的斥力を用いてスぺーサをゲ一トバスライン上に選択配置する工程とからなる。 上記スぺーサが散布される T F T基板を乾燥させる工程は、 スぺ一サを散布す る前に基板を加熱することにより行い、 基板温度を、 1 0 0 °C以上に上昇させ、 基板表面抵抗を、 シート抵抗で 1 X 1 012Ω /口以上とすることが好ましい。 Τ F Τ基板の温度が上昇することにより、 付着水分は減少するため、 基板表面の抵 抗が高くなり、 電流がリークすることがなくなり、 安定的に高精度にスべ一サの 配置が行えるようになる。 より好ましくは、 基板温度は、 1 20〜 1 50°C、 基 板表面抵抗は、 シ一卜抵抗で 1 X 1 012〜 1 X 1 014ΩΖ口である。 In the first method of manufacturing a liquid crystal display device of the present invention, a spacer is dispersed and arranged between a TFT substrate having been subjected to an alignment treatment and a filter substrate and bonded with a sealant, and a liquid crystal is filled in the gap. A method of manufacturing a TFT liquid crystal display device by injecting, wherein a step of drying a TFT substrate on which a spacer is sprayed, and a step of forming a spacer by using an electric attraction and / or an electric repulsion. And selectively arranging them on the bus line. The step of drying the TFT substrate on which the spacer is sprayed is performed by heating the substrate before spraying the spacer, and raising the substrate temperature to 100 ° C. or more, The substrate surface resistance is preferably 1 × 10 12 Ω / port or more in sheet resistance. Τ F す る As the temperature of the substrate rises, the amount of adhering water decreases, so the resistance on the substrate surface increases, no current leaks, and stable placement of the sensor can be performed stably. Become like More preferably, the substrate temperature is 120 to 150 ° C., and the substrate surface resistance is 1 × 10 12 to 1 × 10 14 Ω / cm2 in sheet resistance.
上記 TFT基板の加熱は、 ホッ トプレート、 熱風循環オーブン、 赤外線炉等に より行うことができる。  The TFT substrate can be heated by a hot plate, a hot-air circulation oven, an infrared furnace, or the like.
上記 T F Τ基板を乾燥させる工程に、 ホッ トプレートを用いる場合には、 1 2 0 Cに加熱されたホッ トブレートに T F T基板を 5分以上密着させればよい。 第 1の本発明においては、 上述のように T F T基板を乾燥させた後、 二の TF T基板にスぺーサを散布する。  When a hot plate is used in the step of drying the TFT substrate, the TFT substrate may be brought into close contact with the hot plate heated to 120 C for 5 minutes or more. In the first present invention, after drying the TFT substrate as described above, a spacer is sprayed on the second TFT substrate.
第 1の本発明において、 スベーサの散布は、 乾燥させた T F T基板の基板表面 抵抗が、 シート抵抗で 1 X 1 。"。ノロ以上にて行うことが好ましい。 TFT基 板の基板表面抵抗がシート抵抗で 1 X 1 0"0ノロ未満であると、 T FT基板上 で電流がリークすることがあり、 スぺーサを高精度に選択配置できなくなること がある。 より好ましくは、 シート抵抗で 1 X 1 ou〜 1 X 1 ο14ΩΖϋで行う。 また、 乾燥後基板表面に水分が再付着しないように、 乾燥後 5分以内にスベー サを散布するか、 散布装置内に乾燥窒素を充満させることが好ましい。 In the first aspect of the present invention, the sprayer is sprayed, and the substrate surface resistance of the dried TFT substrate is 1 × 1 in sheet resistance. If the substrate surface resistance of the TFT substrate is less than 1 × 10 "0 in sheet resistance, current may leak on the TFT substrate and a spacer may be formed. May not be able to be selected and placed with high accuracy. More preferably, it carried out at 1 X 1 o u ~ 1 X 1 ο 14 ΩΖϋ in sheet resistance. In order to prevent moisture from re-adhering to the substrate surface after drying, it is preferable to spray a spacer within 5 minutes after drying or to fill the inside of the spraying device with dry nitrogen.
第 1の本発明において、 上記電気的引力及び Ζ又は電気的斥力を用いてスべ一 サをゲートバスラインに選択配置する工程は、 T FT基板上に形成されたゲート バスライン及びソースバスラインの各配線に個別に電圧を印加し、 そこに帯電さ せたスぺ一サを散布することよりなる。  In the first aspect of the present invention, the step of selectively arranging a sensor on the gate bus line by using the above-described electric attraction and Ζ or electric repulsion includes the step of forming the gate bus line and the source bus line formed on the TFT substrate. A voltage is individually applied to each of the wires, and a charged spacer is sprayed there.
C sコモンバスラインが、 ゲ一トバスラインと共通でない TFT基板の場合は、 ゲ一トバスライン、 ソースバスライン及び C sコモンバスラインの各配線に個別 に電圧を印加する。  When the Cs common bus line is a TFT substrate that is not common to the gate bus line, a voltage is individually applied to each of the gate bus line, the source bus line, and the Cs common bus line.
上記電気的引力を用いてスベーサをゲ一トバスライン上に選択的に配置する方 法は、 散布するスぺーサが正帯電のときには、 ゲートバスラインに負電圧を印加 し、 かつ、 ソースバスライン及び C sコモンバスラインをアースする。 散布する スぺーサが負帯電のときには、 ゲートバスラインに正電圧を印加し、 かつ、 ソ一 スバスライン及び C s コモンバスラインをアースすることよりなる。 上記電気的斥力を^いてスぺ一サをゲ一トバスライン上に選択的に配置する方 法は、 散布するスぺ一サが正帯電のときには、 ソースバスライン及び C sコモン バスラインに正電圧を印加し、 かつ、 ゲートバスラインをアースする。 散布する スぺ一サが負帯電のときには、 ソースバスライン及び C s コモンバスラインに負 電圧を印加し、 かつ、 ゲートバスラインをアースすることよりなる。 The method of selectively arranging the spacer on the gate bus line using the above-mentioned electric attraction is to apply a negative voltage to the gate bus line when the spacer to be sprayed is positively charged, and to apply the negative voltage to the source bus line and the source bus line. Ground the Cs common bus line. When the spacer to be sprayed is negatively charged, apply a positive voltage to the gate bus line, and It consists of grounding the sub bus line and the C s common bus line. The method of selectively arranging the spacer on the gate bus line by using the above-mentioned electric repulsive force is as follows. When the scattered sensor is positively charged, a positive voltage is applied to the source bus line and the Cs common bus line. And ground the gate bus line. When the spreader is negatively charged, a negative voltage is applied to the source bus line and the Cs common bus line, and the gate bus line is grounded.
上記電気的引力及び電気的斥力を用いてスべ一サをゲ一トバスライン上に選択 的に配置する方法は、 散布するスぺ一サが正帯電のときには、 ソースバスライン 及び C s コモンバスラインに正電圧を印加し、 かつ、 ゲートバスラインに負電圧 を印加する。 散布するスぺ一サが負帯電のときには、 ソースバスライン及び C s コモンバスラインに負電圧を印加し、 かつ、 ゲートバスラインに正電圧を印加す ることよりなる。  The method of selectively arranging the bus on the gate bus line by using the above-mentioned electric attraction and electric repulsion is as follows. When the spreader is positively charged, the source bus line and the Cs common bus line are used. Apply a positive voltage to, and apply a negative voltage to the gate bus line. When the spreader is negatively charged, a negative voltage is applied to the source bus line and the Cs common bus line, and a positive voltage is applied to the gate bus line.
上述の 3通りの方法によるスぺ一サの選択的配置効杲は、 ほぼ同等であるが、 電源設備が 1つで済むという点から、 上記の電気的引力を用いる引力方式又は上 記の電気的斥力を用いる斥力方式が経済的には好ましい。  The effects of the selective placement of the spacers by the above three methods are almost the same, but since only one power source is required, A repulsion method using a repulsive force is economically preferable.
第 1の本発明には、 C sコモンバスラインが、 ゲートバスラインと共通である 構造の T F T基板を用いることもできる。 C sコモンバスラインが、 ゲートバス ラインと共通である構造の T F T基板を用いる場合には、 ゲ一トバスラインとソ —スバスラインとにのみ上述のように電圧を印加することで、 スぺーサを効果的 にゲートバスライン上に選択配置できる。  In the first invention, a TFT substrate having a structure in which the Cs common bus line is common to the gate bus line can be used. When a TFT substrate having a structure in which the Cs common bus line is common to the gate bus line is used, by applying a voltage to only the gate bus line and the source bus line as described above, the spacer is effective. Specifically, it can be selectively arranged on the gate bus line.
第 1の本発明において、 ゲートバスラインと、 ン一スバスライン及び C sコモ ンバスラインとに印加する電圧は、 ゲートバスラインと、 ソースバスライン及び C sコモンバスラインとの間の電位差が 3 0〜6 0 Vであることが好ましい。 な かでも、 電位差が 4 0 V程度であることがより好ましい。  In the first aspect of the present invention, the voltage applied to the gate bus line, the single bus line, and the Cs common bus line is such that the potential difference between the gate bus line, the source bus line, and the Cs common bus line is 30 to It is preferably 60 V. Among them, the potential difference is more preferably about 40 V.
ゲートバスラインと、 ソースバスライン及び C s コモンバスラインとの間の上 記電位差が大きいほど、 スベーサの選択配置性はよくなるが、 上記電位差が大き すぎると トランジスタの破壊やオン、 オフ特性のシフトという問題が生じる。 実 験によれば、 上記電位差が 5 0〜 6 0 Vを境にトランジスタの特性シフ卜が見ら れ、 2 0 0 Vを超えると、 トランジスタの絶緣破壊が生じる。 第 1の^:発明において散布されるスぺーサの帯電量は、 1 5 25 0 /i C / g又は 1 5 2 50 C/ gであることが好ましい。 より好ましくは、 吸 引式のファラデーゲージにて測定した帯電量が、 十 1 5 + 200 CZg又はThe greater the potential difference between the gate bus line, the source bus line, and the Cs common bus line, the better the selectivity of the spacer, but if the potential difference is too large, the transistor is destroyed and the on / off characteristics shift. The problem arises. According to an experiment, the characteristic shift of the transistor is seen at the boundary of the potential difference of 50 to 60 V, and when the potential difference exceeds 200 V, the transistor is destroyed in an insulated manner. 1st: The amount of charge of the spacer sprayed in the invention is preferably 125500 / ic / g or 15250C / g. More preferably, the charge amount measured by a suction type Faraday gauge is 15 + 200 CZg or
— 1 5 20 O CZgである。 — 1 5 20 O CZg.
更に詳細には、 上記スべ一サの比重 .粒子径によっても最適な帯電量が細分化 される。 例えば、 比重 1. 0〜 1. 3のスベーサにて、 粒子径が 5. 0 / mであ る場合の好適な帯電量は、 1 5〜十 60 CZg又は— 1 5 60 C/g であり、 粒子径が 4. 5 mである場合の好適な帯電量は、 T 20 ÷ 80 C /g又は— 2 0 8 0 μ C/ gであり、 粒子径が 3. 0 z mである場合の好適 な帯電量は、 τ 5 0 2 0 0 μ C/ g又は一 5 0 2 0 0 μ C/ gである。 上記スべ一サの帯電量は、 少なすぎても多すぎても不都合が生じる。 スベーサ の帯電量が少なすぎると、 静電的な力が弱まるため、 スベーサがゲートバスライ ン上に適切に配置されないことがある。 また、 スベーサのゲートバスライン上へ の電気的引力が弱まり、 散布気流が基板に当たって基板外側に流れる際に、 その 気流にのってスベーサが基板外に逃げてしまい、 基板への散布個数が少ないこと がある。 スぺ一サの帯電量が多すぎると、 スぺ一サ同士の反発力が強くなり、 先 にゲ一トバスラインに載ったスぺ一サの電位により新たに散布されたスベーサが 弾かれるため、 スベーサがゲ一トバスライン上に密に配置されないことがある。 第 1の本発明において用いられるスベーサは、 熱可塑性の接着性スぺーサ又は 光硬化性の接着性スぺーサであって、 ゲートバスライン上に選択配置された後、 加熱又は光照射によって接着固定されることが好ましい。  More specifically, the optimum charge amount is subdivided depending on the specific gravity of the above-mentioned sensor and the particle diameter. For example, in a baser having a specific gravity of 1.0 to 1.3 and a particle size of 5.0 / m, a preferable charge amount is 15 to 60 CZg or -156 C / g. When the particle size is 4.5 m, the suitable charge amount is T 20 ÷ 80 C / g or −2080 μC / g, and when the particle size is 3.0 zm, The appropriate charge amount is τ520 μC / g or 150 μC / g. If the charge amount of the above-mentioned spacer is too small or too large, inconvenience occurs. If the charge of the spacer is too low, the electrostatic force will weaken and the spacer may not be properly positioned on the gate bus line. In addition, the electric attraction of the spacer to the gate bus line is weakened, and when the scattered airflow hits the substrate and flows outside the substrate, the airflow causes the spacer to escape to the outside of the substrate, and the number of sprayed particles to the substrate is small. Sometimes. If the charge amount of the spacer is too large, the repulsive force between the switches becomes strong, and the newly sprayed spacer is repelled by the potential of the spacer previously placed on the gate bus line. The spacers may not be densely arranged on the gate bus line. The spacer used in the first present invention is a thermoplastic adhesive spacer or a photo-curing adhesive spacer, which is selectively arranged on a gate bus line and then bonded by heating or light irradiation. Preferably, it is fixed.
上記熱可塑性の接着性スぺーサ又は光硬化性の接着性スぺ一サを用いてスぺー サをゲ一トバスライン上に接着固定することにより、 その後の液晶表示装置製造 工程及び製造された液晶表示装置の使用時に、 スぺーサがゲートバスライン上か ら移動することが防止される。  The above-mentioned thermoplastic adhesive spacer or photo-curable adhesive spacer is used to bond and fix the spacer on the gate bus line. When the display device is used, the spacer is prevented from moving on the gate bus line.
第 1の本発明においては、 T FT基板上に形成されるゲ一トバスラインの線幅 は、 スぺーサの平均粒子径の 3倍以上であることが好ましい。 上記ゲー トバスラ インの線幅が、 スぺ一サの平均粒子径の 3倍以上であることにより、 スぺーサを 効果的にゲ一卜バスライン上に配置できる。 より好ましくは、 4 5倍である。 例えば、 直径 5 / mのスベーサを散布する場合には、 上記ゲートバスラインの線 幅は、 少なく とも 1 5 m、 好ましくは 2 0〜 2 5 /i m程度である。 In the first aspect of the present invention, the line width of the gate bus line formed on the TFT substrate is preferably at least three times the average particle diameter of the spacer. When the line width of the gate bus line is three times or more the average particle diameter of the spacer, the spacer can be effectively arranged on the gate bus line. More preferably, it is 45 times. For example, when spraying a baser having a diameter of 5 / m, the line width of the gate bus line is at least 15 m, and preferably about 20 to 25 / im.
上記ゲ一卜バスラインの線幅がスべ一サの平均粒子径の 3倍未満であると、 選 択配置率が低下し、 ゲートバスライン上から外れ、 画素電極上に配置されるスぺ ーサの割合が多くなることがある。 これは、 スぺ一サ同士が同極性の電位を持つ ているために、 先にゲ一トバスライン上に載ったスぺ一サと後で散布されたスぺ —サとの間で反発力が働き、 狭いスペースに載り難いためである。  When the line width of the gate bus line is less than three times the average particle diameter of the spacer, the selection arrangement ratio is reduced, the gate bus line is deviated from the gate bus line, and the gate line is disposed on the pixel electrode. May increase. This is because repulsive force is exerted between the sensor placed first on the gate bus line and the later-distributed spacer because the spacers have the same polarity potential. This is because it is difficult to work and fit in a narrow space.
ゲートバスラインの線幅がスべ一サの平均粒子径の 3倍未満である場合に、 ス ぺ一サの選択配置率を改善する方法としては、 ゲートバスラインと、 ソースバス ライン及び C s コモンバスラインとの間の電位差を 5 0〜 6 0 Vとやや高めに設 定する方法がある。 この電圧では、 上述のトランジスタの特性シフ トが生じ始め るが、 このレベルの特性シフ トであれば、 スぺ一サ散布後、 T F T基板を 1 5 0 °C以上で 1時間程度ァニールすることにより T F T特性が元に戻る。  When the line width of the gate bus line is less than three times the average particle size of the gate, a method of improving the selective placement ratio of the gate is as follows. There is a method in which the potential difference between the common bus line and the common bus line is set slightly higher at 50 to 60 V. At this voltage, the characteristic shift of the transistor described above starts to occur, but with this level of characteristic shift, the TFT substrate should be annealed at 150 ° C or higher for about 1 hour after spraying. As a result, the TFT characteristics are restored.
第 1の本発明においては、 スベーサを散布後、 T F T基板を 1 5 0 °C以上の温 度でァニールして T F T特性の補償を行うことができる。 より好ましくは、 2 0 o °c程度にてァニールする。  In the first aspect of the present invention, after spraying the spacer, the TFT substrate can be annealed at a temperature of 150 ° C. or more to compensate for the TFT characteristics. More preferably, annealing is performed at about 20 ° C.
第 1の本発明においては、 上記のァニール工程について、 特別なプロセスを加 える必要はない。 第 1の本発明では、 通常の液晶表示装置の製造方法と同様に、 スベーサ散布後、 2枚の基板を貼り合わせてシール剤を硬化させるために 1 5〇 〜 2 0 (TCで 1〜 2時間程度焼成するため、 自動的にァニールされる。  In the first aspect of the present invention, it is not necessary to add a special process to the above annealing step. In the first aspect of the present invention, similarly to the method of manufacturing a normal liquid crystal display device, after spraying the spacer, the two substrates are bonded together to cure the sealant. It is annealed automatically for firing for about an hour.
第 1の本発明においては、 上述のようにしてスべ一サが選択配置された T F T 基板と、 C F基板とをシール剤で貼り合わせて接着し、 基板間隙に液晶を充填し て、 液晶表示装置が製造される。  In the first aspect of the present invention, a TFT substrate on which a sensor is selectively arranged as described above and a CF substrate are bonded and adhered with a sealant, and a liquid crystal is filled in a gap between the substrates to form a liquid crystal display. The device is manufactured.
第 1の本発明は、 上述の構成からなるので、 スべ一サによる輝度低下やコン ト ラス ト低下がない、 高品位の表示特性をもった液晶表示装置を提供できる。 第 1の本発明により製造されてなる上記液晶表示装置もまた、 本発明の 1つで ある。  Since the first aspect of the present invention has the above-described configuration, it is possible to provide a liquid crystal display device having high-quality display characteristics without a decrease in brightness or contrast due to a speaker. The liquid crystal display device manufactured according to the first aspect of the present invention is also one aspect of the present invention.
第 2の本発明は、 T F T基板とカラーフィルタ基板とを、 スべ一サ及びシール 剤を介在させて貼り合わせ、 その間隙に液晶を注入してなる液晶表示装置であつ て、 スぺ一サは、 T F T基板上に形成されたゲートバスライン上に電気的引力及 び Z又は斥力を用いて選択的に配置されたものであり、 ゲ一トバスラインの線幅 は、 スぺーサの平均粒径の 3倍以上の液晶表示装置である。 The second invention is a liquid crystal display device in which a TFT substrate and a color filter substrate are bonded together with a spacer and a sealant interposed therebetween, and a liquid crystal is injected into a gap therebetween. The spacer is selectively disposed on a gate bus line formed on a TFT substrate by using an electric attractive force and Z or a repulsive force, and the line width of the gate bus line is This is a liquid crystal display device with an average particle diameter of three times or more.
液晶表示装置の明るさを大きくするために、 ゲートバスライン上に形成した絶 縁膜の上に、 画素電極をゲートバスラインに被せるように配置し、 表示面積を大 きくする工夫がなされる場合がある。 この場合、 画素電極が被さっていないゲ一 トバスラインの幅が、 有効なゲ一トバスラインの線幅に相当する。  In order to increase the brightness of the liquid crystal display device, it is necessary to arrange a pixel electrode on the insulating film formed on the gate bus line so that the pixel electrode covers the gate bus line, so that the display area is enlarged. There is. In this case, the width of the gate bus line that is not covered by the pixel electrode corresponds to the effective gate bus line width.
第 2の本発明では、 スべ一サを効果的にゲ一トバスライン上に選択配置するた め、 画素電極が被さっていないゲー トバスラインの幅は、 スベーサの平均粒子径 の 4〜 5倍であることが好ましい。  In the second aspect of the present invention, the width of the gate bus line that is not covered with the pixel electrode is 4 to 5 times the average particle diameter of the spacer because the spacer is effectively selected and arranged on the gate bus line. Is preferred.
第 2の 発明は、 例えば、 第 1の本発明を用いることにより、 製造することが できる。  The second invention can be manufactured, for example, by using the first invention.
以下、 本発明の実施の形態を、 図 1〜3を用いて具体的に説明する。  Hereinafter, embodiments of the present invention will be specifically described with reference to FIGS.
図 1は、 本癸明で用いるスぺ一サの散布装置を示す概念図である。 容器 1 0の 上端部に、 帯電させたスぺーサ 8を散布するノズル 1 1 aが設けられている。 散 布ノズル 1 1 aには、 散布配管 1 7を介して、 スぺ一サ 8を供給する装置 1 1 b が接続されている。 容器 1 0の下方には、 ゲー トバスライン、 ソースバスライン 及び C sコモンバスラインが形成された T F T基板 2が設置されている。 T F T 基板 2のゲートバスライン、 ソースバスライン及び C s コモンバスラインの各配 線に対し、 それぞれ個別にプローブピン 1 6 a、 1 6 b、 1 6 cを接触させ、 電 圧印加装置 1 2にて電圧を印加し、 帯電させたスぺーサ 8を上記 T F T基板 2に 散布することで、 電気的引力及びノ又は電気的斥力を用いて、 スぺ一サ 8をゲ一 トバスライン上に選択的に配置する。  FIG. 1 is a conceptual diagram showing a sprinkler spray device used in the present invention. A nozzle 11 a for spraying the charged spacer 8 is provided at the upper end of the container 10. An apparatus 11 b for supplying a spacer 8 is connected to the spray nozzle 11 a via a spray pipe 17. Below the container 10, a TFT substrate 2 on which a gate bus line, a source bus line, and a Cs common bus line are formed is provided. The probe pins 16a, 16b, and 16c are individually contacted with the gate bus line, source bus line, and Cs common bus line of the TFT substrate 2, respectively. A voltage is applied to the TFT substrate 2 and the charged spacers 8 are sprayed on the TFT substrate 2 to select the spacers 8 on the gate bus line using electric attraction and electric or repulsion. Place
本発明において、 スベーサ 8を帯電させる方法には、 図 1に示した散布配管 1 7と散布ノズル 1 1 aとに、 ステンレス製、 テフロン製、 ナイ口ン製又はウレタ ン樹脂製等のものを用い、 スぺ一サ 8が、 散布配管 1 7と散布ノズル 1 1 a とを 通る際に摩擦によって生じる帯電を利用する。  In the present invention, the method of charging the base 8 is as follows: the spraying pipe 17 and the spraying nozzle 11a shown in FIG. 1 are made of stainless steel, Teflon, Nymouth or urethane resin. When the spreader 8 passes through the spraying pipe 17 and the spraying nozzle 11 a, the charge generated by friction is used.
本発明におけるスベーサの散布万法としては、 コロナ放電を^いた帯電ガン方 式は好ましくない。 スベーサの電位が高くなりすぎ、 スぺ一サ同士の反発力が強 くなるため、 ゲー バスライン上への配置性が悪くなる。 As a method of spraying a spacer in the present invention, a charging gun method using corona discharge is not preferable. The potential of the spacer is too high, and the repulsion between the controllers is strong. Therefore, the arrangement on the game bus line is deteriorated.
図 2は、 不発明で^いる T F T基板の配線構造を示す概念図である。 図 2に示 すように、 ゲートバスライン 1 3 aに電圧印加するためのゲ一トコンタク トパッ ド 1 3 b、 ソースバスライン 1 4 aに電圧印加するためのソ一スコンタク トパッ ド 1 4 b、 C s コモンバスライン 1 5 aに電圧印加するための C s 二モンパッ ド 1 5 bが設けられており、 ここに図 1に記載のプコ一ブピン 1 6 a、 1 6 b、 1 6 cがそれぞれ接触される。 これらコンタク トパッ ドは、 配線を行い易くするた め、 又は、 配線抵抗値を低くするために、 1枚の T F T基板に対して各々複数点 設けられてもよく、 各 1点にまとめられてもよレ、。  FIG. 2 is a conceptual diagram showing a wiring structure of a TFT substrate which is not invented. As shown in FIG. 2, a gate contact pad 13b for applying a voltage to the gate bus line 13a, a source contact pad 14b for applying a voltage to the source bus line 14a, A C s dimon pad 15 b for applying a voltage to the C s common bus line 15 a is provided, and here the Pc-pins 16 a, 16 b, and 16 c shown in FIG. 1 are provided. Each is contacted. These contact pads may be provided at a plurality of points on one TFT substrate in order to facilitate wiring or to reduce wiring resistance, and may be combined at one point. Yeah.
図 3は、 不発明における有効なゲ一トバスラインの線幅を説明するための概念 図である。 Hi 3に示すように、 T F T基板の構成によっては、 完成した液晶表示 装置の明るさを大きくするために、 ゲ一トバスライン 1 3 a上に形成した絶緣膜 2 0の上に、 画素電極 3をゲートバスライン 1 3 aに被せるように配置し、 表示 面積を大きくする工夫がなされるが、 この場合は画素電極の隙間 1 9が上記有効 なゲートバスラインの線幅に相当する。 本発明において、 スべ一サを効果的にゲ ―卜バスライン上に選択配置するためには、 上記有効なゲ一トバスラインの線幅 力 スべ一サの平均粒子径の 3倍以上であることが好ましい。 発明を実施するための最良の形態  FIG. 3 is a conceptual diagram for explaining the effective gate bus line width in the invention. As shown in Hi 3, depending on the configuration of the TFT substrate, in order to increase the brightness of the completed liquid crystal display device, the pixel electrode 3 is formed on the insulating film 20 formed on the gate bus line 13a. The gate bus line 13a is disposed so as to cover the gate bus line 13a to make the display area large. In this case, the gap 19 between the pixel electrodes corresponds to the effective line width of the gate bus line. In the present invention, the effective width of the gate bus line is at least three times the average particle diameter of the spacer in order to effectively select and place the spacer on the gate bus line. Is preferred. BEST MODE FOR CARRYING OUT THE INVENTION
以下に実施例を挙げて本発明を更に詳細に説明するが、 本発明はこれらの実施 例のみに限定されるものではない。 実施例 1  Hereinafter, the present invention will be described in more detail by way of examples, but the present invention is not limited to these examples. Example 1
透明ガラス基板上に、 ゲートバスラインを形成しパターニングした後、 ゲート 絶縁膜を形成した。 更に、 画素電極、 ソースバスライン及び C s コモンバスライ ンについて、 それぞれ成膜とパターニングの操作を行い、 T F T基板を作製した。  Gate bus lines were formed and patterned on a transparent glass substrate, and then a gate insulating film was formed. Furthermore, the TFT electrode was formed by performing film formation and patterning operations on the pixel electrode, the source bus line, and the Cs common bus line, respectively.
T F T基板の電極パターンは、 図 2に示すように形成し、 ゲートバスラインの線 幅は約 2 0 mであった。 C F基板として、 T F T型液晶表示装置用のコモン電 極基板を準備した。 この 2枚の基板に、 配向処理を施した。 スぺーサとして、 平 均粒子径が約 5 β mである熱可塑性のスぺーサを準備した。 The electrode pattern of the TFT substrate was formed as shown in Fig. 2, and the line width of the gate bus line was about 20 m. A common electrode substrate for a TFT type liquid crystal display was prepared as a CF substrate. These two substrates were subjected to an orientation treatment. As a spacer, A thermoplastic spacer having an average particle size of about 5 βm was prepared.
スべ一サ散布前の基板の乾燥工程として、 1 2 0 °Cに加熱したホッ 卜プレート に、 作製した T F T基板を 1 0分間密着させた。 乾燥工程後、 T F T基板の基板 表面抵抗は、 シート抵抗で 1 X 1 0 " Ω Ζコであった。 乾燥工程後すぐに、 図 1 で示される散布装置に T F T基板を設置し、 電圧印加装置により T F T基板上の ゲ一トバスラインに正電圧を印加し、 ソースバスライン及び C s コモンバスライ ンをアースし、 スぺーサを負帯電させて散布した。 このとき、 基板上のゲートバ スラインと、 ソースバスライン及び C s コモンバスラインとの間の電位差 、 4 3 Vであった。  As a drying step of the substrate before spraying with the heater, the prepared TFT substrate was adhered to a hot plate heated to 120 ° C. for 10 minutes. After the drying process, the substrate surface resistance of the TFT substrate was 1 × 10 "ΩΖ in sheet resistance. Immediately after the drying process, the TFT substrate was set on the spraying device shown in FIG. As a result, a positive voltage was applied to the gate bus line on the TFT substrate, the source bus line and the Cs common bus line were grounded, and the spacer was negatively charged and sprayed. The potential difference between the source bus line and the Cs common bus line was 43 V.
スぺ一サが散布された T F T基板を光学顕微鏡で観察した結果を、 図 4に拡大 して示した。 ほとんどのスぺーサ 8がゲートバスライン 1 3 a上に選択的に配置 されていた。 この T F T基板を加熱処理し、 スぺーサを接着固定した。 次いで、 この T F T基板と C F基板とを用いて、 シール形成、 貼り合わせ、 基板切断、 液 晶注入の工程を経て、 液晶表示装置を作製した。 得られた液晶表示装置 、 スぺ —サに起因する光抜けがないため、 コントラス トが高く、 良好な表示特性であつ  The results of observing the TFT substrate on which the spacers were sprayed with an optical microscope are shown in FIG. Most spacers 8 were selectively arranged on the gate bus line 13a. The TFT substrate was subjected to a heat treatment, and the spacer was bonded and fixed. Next, using the TFT substrate and the CF substrate, a liquid crystal display device was manufactured through the steps of seal formation, bonding, substrate cutting, and liquid crystal injection. The obtained liquid crystal display has high contrast and good display characteristics because there is no light leakage due to the spacer.
実施例 2 Example 2
ソースバスライン及び C s コモンバスラインに負電圧を印加し、 ゲートバスラ インをアースしたこと以外は、 実施例 1と同様にして操作を行った。 このとき、 基板上のゲ一トバスラインと、 ソースバスライン及び C s コモンバスラインとの 間の電位差は、 3 9 Vであった。  The operation was performed in the same manner as in Example 1 except that a negative voltage was applied to the source bus line and the Cs common bus line, and the gate bus line was grounded. At this time, the potential difference between the gate bus line on the substrate, the source bus line and the Cs common bus line was 39 V.
スぺ一サが散布された T F T基板を光学顕微鏡で観察した結果、 実施例 1 と同 様に、 ほとんどのスぺーサがゲートバスライン上に選択的に配置されていた。 ま た、 この T F T基板を用いて実施例 1 と同様に液晶表示装置を作製したところ、 得られた液晶表示装置は、 スぺ一サに起因する光抜けがないため、 コントラス ト が高く、 良好な表示特性であった。 比較例 1 スベーサ散布前の T F T基板の乾燥工程を省いたこと以外は、 実施例 1と同様 に操作を行った。 なお、 T F T基板の基板表面抵抗は、 1 Χ 1 0 9 Ω Ζ口であり、 T F Τ基板上のゲ一トバスラインと、 ソースバスライン及び C s コモンバスライ ンとの間の電位差は、 8 Vであった。 As a result of observing the TFT substrate on which the spacers were sprayed with an optical microscope, almost all the spacers were selectively arranged on the gate bus lines as in the first embodiment. Further, when a liquid crystal display device was manufactured using this TFT substrate in the same manner as in Example 1, the obtained liquid crystal display device had a high contrast and was free from light leakage due to the spacer. Display characteristics. Comparative Example 1 The operation was performed in the same manner as in Example 1 except that the step of drying the TFT substrate before spraying the spacer was omitted. The substrate surface resistance of the TFT substrate is 1Χ109 Ω 9 , and the potential difference between the gate bus line on the TFΤ substrate, the source bus line and the Cs common bus line is 8 V Met.
スぺーサが散布された T F Τ基板を光学顕微鏡で観察した結果を、 図 5に拡大 して示した。 多くのスぺ一サ 8が画素電極 3上に散布されていた。 また、 この Τ F T基板を用いて、 実施例 1 と同様に液晶表示装置を作製したところ、 作製した 液晶表示装置は、 スぺーサに起因する光抜けの影響で、 実施例 1及び実施例 2よ りコン トラス 卜が劣っていた。  The results of observing the TF substrate on which the spacer was sprayed with an optical microscope are shown in FIG. Many sensors 8 were sprayed on the pixel electrodes 3. Further, a liquid crystal display device was manufactured using this FT substrate in the same manner as in Example 1. The manufactured liquid crystal display device was affected by the light leakage caused by the spacer. The contrast was inferior.
試験例 1 Test example 1
実施例 1において乾燥工程を省略、 又は、 乾燥工程における加熱時間を 5分間 とし、 加熱温度を 8 0。C、 1 0 0 °C又は 1 2 0 °Cとした以外は、 実施例 1 と同様 にして、 スぺ一サの散布を行い、 液晶表示装置を作製した。  The drying step was omitted in Example 1, or the heating time in the drying step was 5 minutes, and the heating temperature was 80. C. A liquid crystal display device was manufactured in the same manner as in Example 1 except that the temperature was changed to 100 ° C. or 120 ° C.
この場合の基板加熱温度とスぺ一ザの散布率の関係を表 1に示した。 表 1より、 T F T基板を 1 0 0 °C以上に加熱した場合には、 約 9割以上のスぺ一サがゲ一ト バスライン上に選択的に配置されており、 得られた液晶表示装置の表示特性は極 めて良好であった。  Table 1 shows the relationship between the substrate heating temperature and the spraying rate of the spreader in this case. According to Table 1, when the TFT substrate is heated to 100 ° C or more, about 90% or more of the spacers are selectively arranged on the gate bus line. The display characteristics of the device were extremely good.
Figure imgf000015_0001
Figure imgf000015_0001
産業上の利用可能性 Industrial applicability
本発明は、 上述の構成よりなるので、 T F T基板を用いた液晶表示装置におい て、 画素電極上のスぺ一サをなくすか又は大幅に少なく し、 スぺ一サによる輝度 低下やニントラス ト低下がない、 高品位の表示特性を持った液晶表示装置を提供 することができる。 Since the present invention has the above-described configuration, in a liquid crystal display device using a TFT substrate, a spacer on a pixel electrode is eliminated or greatly reduced, and luminance due to the spacer is reduced. It is possible to provide a liquid crystal display device having high quality display characteristics without a decrease or a decrease in nintrast.

Claims

請求の範囲 The scope of the claims
1 . T F Τ基板とカラーフィルタ基板との間にスぺ一サを分散配置してシール剤 で貼り合わせ、 その間隙に液晶を注入することよりなる T F T液晶表示装置の製 造方法であって、 スぺーサが散布される T F T基板を乾燥させる工程と、 電気的 引力及び Z又は電気的斥力を用いてスぺ一サをゲ一トバスライン上に選択配置す る工程とからなり、 前記電気的引力及び Z又は電気的斥力を用いてスベーサをゲ ―トバスライン上に選択配置する工程は、 T F T基板上に形成されたゲー卜バス ライン及びソースバスラインの各配線に個別に電圧を印加し、 そこに帯電させた スぺ一サを散布することよりなることを特徴とする液晶表示装置の製造方法。 1. A method for manufacturing a TFT liquid crystal display device, comprising dispersing and disposing a spacer between a TF substrate and a color filter substrate, bonding them with a sealant, and injecting liquid crystal into the gap. A step of drying the TFT substrate on which the spacer is sprayed, and a step of selectively arranging the spacer on the gate bus line using electric attraction and Z or electric repulsion. The step of selectively arranging the spacer on the gate bus line using Z and Z or electric repulsion applies a voltage individually to each of the gate bus line and the source bus line formed on the TFT substrate, and applies the voltage thereto. A method for manufacturing a liquid crystal display device, comprising spraying a charged spacer.
2 . 電気的引力及び/又は電気的斥力を用いてスぺーサをゲ一トバスライン上に 選択配置する工程は、 T F T基板上に形成されたゲートバスライン、 ソースバス ライン及び C s コモンバスラインの各配線に個別に電圧を印加し、 そこに帯電さ せたスぺ一サを散布することよりなることを特徴とする請求の範囲第 1項記載の 液晶表示装置の製造方法。 2. The step of selectively arranging the spacer on the gate bus line by using the electric attraction and / or the electric repulsion is performed on the gate bus line, the source bus line and the Cs common bus line formed on the TFT substrate. 2. The method for manufacturing a liquid crystal display device according to claim 1, wherein a voltage is individually applied to each wiring, and a charged spacer is sprayed thereon.
3 . スぺ一サが散布される T F T基板を乾燥させる工程は、 スぺーサを散布する 前に基板を加熱することにより行い、 基板温度を、 1 0 o °c以上に上昇させ、 基 板表面抵抗を、 シート抵抗で 1 X 1 0 ι2Ω Ζ口以上とすることを特徴とする請求 の範囲第 1又は 2項記載の液晶表示装置の製造方法。 3. The step of drying the TFT substrate on which the spacers are sprayed is performed by heating the substrate before spraying the spacers, raising the substrate temperature to 10 ° C or more, 3. The method for manufacturing a liquid crystal display device according to claim 1, wherein the surface resistance is 1 × 10 10 Ω2 Ω or more in sheet resistance.
4 . スぺーサの散布は、 乾燥させた T F Τ基板の基板表面抵抗が、 シート抵抗で 1 X 1 0 " Ω Ζ口以上にて行うことを特徴とする請求の範囲第 1、 2又は 3項記 載の液晶表示装置の製造方法。 4. The first, second or third aspect of the present invention, wherein the spraying of the spacer is performed at a substrate surface resistance of the dried TF substrate at a sheet resistance of 1 X 10 "Ω or more. The manufacturing method of the liquid crystal display device described in the item.
5 - 電気的引力を用いてスぺ一サをゲ一トバスライン上に選択的に配置する工程 は、 散布するスぺ一ザが正帯電のときには、 ゲートバスラインに負電圧を印加し、 かつ、 ソースバスライン及び C s コモンバスラインをアースし、 散布するスぺ一 サが負帯電のときには、 ゲートバスラインに正電圧を印加し、 かつ、 ソースバス ライン及び C sコモンバスラインをアースすることよりなることを特徴とする請 求の範囲第 1 、 2、 3又は 4項記載の液晶表示装置の製造方法。 6 . 電気的斥力を用いてスぺ一サをゲートバスライン上に選択的に配置する工程 は、 散布するスぺーサが正帯電のときには、 ソースバスライン及び C s コモンバ スラインに正電圧を印加し、 かつ、 ゲートバスラインをアースし、 散布するスぺ 一サが負帯電のときには、 ソースバスライン及び C s コモンバスラインに負電圧 を印加し、 かつ、 ゲートバスラインをアースすることよりなることを特徴とする 請求の範囲第 1、 2、 3又は 4項記載の液晶表示装置の製造方法。 5-The step of selectively arranging the sensor on the gate bus line by using the electric attraction includes applying a negative voltage to the gate bus line when the sprayer is positively charged, and Ground the source bus line and C s common bus line and spray them. Claims 1, 2, 3, or 3 characterized in that when the power supply is negatively charged, a positive voltage is applied to the gate bus line and the source bus line and the Cs common bus line are grounded. 5. The method for manufacturing a liquid crystal display device according to item 4. 6. The step of selectively arranging the spacer on the gate bus line by using electric repulsion is performed by applying a positive voltage to the source bus line and the C s common bus line when the spreader is positively charged. When the spreader is negatively charged, a negative voltage is applied to the source bus line and the Cs common bus line, and the gate bus line is grounded. 5. The method for manufacturing a liquid crystal display device according to claim 1, 2, 3, or 4, wherein:
7 . 電気的引力及び電気的斥力を用いてスぺーサをゲ一トバスライン上に選択的 に配置する工程は、 散布するスぺーサが正帯電のときには、 ソースバスライン及 び C s コモンバスラインに正電圧を印加し、 かつ、 ゲートバスラインに負電圧を 印加し、 散布するスぺーサが負帯電のときには、 ソースバスライン及び C s コモ ンバスラインに負電圧を印加し、 かつ、 ゲートバスラインに正電圧を印加するこ とよりなることを特徴とする請求の範囲第 1、 2、 3又は 4項記載の液晶表示装 置の製造方法。 8 . C s コモンバスラインが、 ゲートバスラインと共通である構造の T F T基板 に対しては、 ゲ一トバスラインとソースバスラインとにのみ電圧を印加すること を特徴とする請求の範囲第 1 、 2、 3、 4、 5、 6又は 7項記載の液晶表示装置 の製造方法。 9 . ゲートバスラインと、 ソースバスライン及び C s コモンバスラインとに印加 する電圧は、 ゲートバスラインと、 ソースバスライン及び C s コモンバスライン との間の電位差が 3 0〜 6 0 Vであることを特徴とする請求の範囲第 1 、 2、 3、 4、 5、 6、 7又は 8項記載の液晶表示装置の製造方法。 7. The step of selectively arranging spacers on the gate bus line by using electric attraction and electric repulsion is performed when the spreader is positively charged, when the source bus line and the C s common bus line are used. When a positive voltage is applied to the gate bus line and a negative voltage is applied to the gate bus line, and the spreader is negatively charged, a negative voltage is applied to the source bus line and the C s common bus line, and 5. The method for manufacturing a liquid crystal display device according to claim 1, wherein a positive voltage is applied to the liquid crystal display device. 8. For a TFT substrate having a structure in which the Cs common bus line is common to the gate bus line, a voltage is applied only to the gate bus line and the source bus line. 8. The method for manufacturing a liquid crystal display device according to 2, 3, 4, 5, 6, or 7. 9. The voltage applied to the gate bus line, the source bus line, and the Cs common bus line is such that the potential difference between the gate bus line, the source bus line, and the Cs common bus line is 30 to 60 V. 9. The method for manufacturing a liquid crystal display device according to claim 1, 2, 3, 4, 5, 6, 7, or 8.
1 0. 散布されるスぺーサの帯電量は、 + 1 5〜十 250 μ CZg又は一 1 5〜 — 2 50 μ CZgであることを特徴とする請求の範囲第 1、 2、 3、 4、 5、 10. The charged amount of the spacer to be sprayed is +15 to 10 250 μCZg or 1 15 to −250 μCZg. Claims 1, 2, 3, and 4 , Five,
6、6,
7、 8又は 9項記載の液晶表示装置の製造方法。 1 1. スぺーサは、 熱可塑性の接着性スぺーサ又は光硬化性の接着性スぺーサで あって、 ゲートバスライン上に選択配置された後、 加熱又は光照射によって接着 固定されることを特徴とする請求の範囲第 1、 2、 3、 4、 5、 6、 7、 8、 9 又は 1 0項記載の液晶表示装置の製造方法。 1 2. ゲートバスラインの線幅は、 スぺーサの平均粒子径の 3倍以上であること を特徴とする請求の範囲第 1、 2、 3、 4、 5、 6、 7、 8、 9、 1 0又は 1 1 項記載の液晶表示装置の製造方法。 10. The method for manufacturing a liquid crystal display device according to 7, 8, or 9. 1 1. The spacer is a thermoplastic adhesive spacer or a photo-curing adhesive spacer. After being selectively arranged on the gate bus line, it is adhesively fixed by heating or light irradiation. The method for manufacturing a liquid crystal display device according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10. 1 2. The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and ninth, wherein the line width of the gate bus line is at least three times the average particle diameter of the spacer. 12. The method for manufacturing a liquid crystal display device according to any one of items 10 to 11.
1 3. スぺ一サを散布後、 T F T基板を 1 50°C以上の温度でァニールして T F T特性の補償を行うことを特徴とする請求の範囲第 1、 2、 3、 4、 5、 6、 7、1 3. After spraying the spacer, the TFT substrate is annealed at a temperature of 150 ° C. or more to compensate for the TFT characteristics. 6, 7,
8、 8,
9、 9,
1 0、 1 1又は 1 2項記載の液晶表示装置の製造方法。 13. The method for manufacturing a liquid crystal display device according to item 10, 10, 11, or 12.
1 4. 請求の範囲第 1、 2、 3、 4、 5、 6、 7、 8、 9、 1 0、 1 4. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
1 1、 1 2又 は 1 3項記載の液晶表示装置の製造方法により製造されてなることを特徴とする 液晶表示装置。 11. A liquid crystal display device manufactured by the method for manufacturing a liquid crystal display device according to item 1, 12, or 13.
1 5. TFT基板とカラーフィルタ基板とを、 スぺ一サ及びシール剤を介在させ て貼り合わせ、 その間隙に液晶を注入してなる液晶表示装置であって、 前記スぺ ーサは、 T F T基板上に形成されたゲートバスライン上に電気的引力及び Z又は 斥力を用いて選択的に配置されたものであり、 前記ゲートバスラインの線幅は、 前記スべ一サの平均粒径の 3倍以上であることを特徴とする液晶表示装置。 1 5. A liquid crystal display device in which a TFT substrate and a color filter substrate are bonded together with a spacer and a sealant interposed therebetween, and a liquid crystal is injected into a gap between the substrates. The gate bus lines formed on the substrate are selectively arranged using electrical attraction and Z or repulsion, and the line width of the gate bus lines is defined as an average particle size of the spacer. A liquid crystal display device characterized by being three times or more.
1 6. 画素電極が被さっていないゲ一トバスラインの幅は、 スべ一サの平均粒径 の 4〜 5倍であることを特徴とする請求の範囲第 1 5項記載の液晶表示装置。 16. The liquid crystal display device according to claim 15, wherein the width of the gate bus line not covered by the pixel electrode is 4 to 5 times the average particle diameter of the spacer.
PCT/JP2000/007834 1999-12-03 2000-11-08 Lcd device and method of manufacture thereof WO2001040855A1 (en)

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