WO2001037347A1

WO2001037347A1 - Non-volatile semiconductor memory location and method for producing the same

Info

Publication number: WO2001037347A1
Application number: PCT/DE2000/003990
Authority: WO
Inventors: Christoph Ludwig; Christoph Kutter; Peter Wawer; Elard Stein Von Kamienski
Original assignee: Infineon Technologies Ag
Priority date: 1999-11-18
Filing date: 2000-11-15
Publication date: 2001-05-25
Also published as: DE19955602A1

Abstract

The invention relates to a non-volatile semiconductor memory location comprising a semiconductor substrate (1), a first insulating layer (3), a charge-storing layer (4), a second insulating layer (5), and a control layer (6). The invention also relates to a corresponding production method according to which, in order to improve the temperature properties, the charge-storing layer (4) is constructed by a dielectric having a low energy gap.

Description

description

Non-volatile semiconductor memory cell and method for its production

The present invention relates to a non-volatile semiconductor memory cell and a method for its production, and in particular to EPROM, EEPROM and FLASH-EPROM memory cells with improved temperature properties.

Non-volatile semiconductor memory cells, such as those used in EPROM, EEPROM and FLASH-EPROM memories, usually consist of a semiconductor substrate, an insulating tunnel oxide layer, a conductive floating gate layer, an insulating dielectric layer and a conductive control layer. To store information, charges are introduced into the floating gate layer from a channel region formed in the semiconductor substrate via the tunnel oxide layer. Methods for introducing the charges into the floating gate layer are, for example, injection of hot charge carriers, channel injection and Fowler-Nordheim tunnels.

Another conventional layer structure is the so-called SONOS structure (silicon / oxide / nitride / oxide / silicon), the charges to be stored not being stored in an electrically conductive floating gate layer but in an Si ₃ N ₄ layer. FIG. 1 shows a simplified representation of a band model for such a conventional SONOS semiconductor memory cell structure, as described, for example, by the literature reference “A novel SONOS structure for nonvolatile me ories with improved data retention”, H. Reisinger et al, Symposium on VLSI Technology Digest of Technical Papers, 1997, pages 113 and 114. Here, an SiO ₂ layer 3, an Si ₃ N layer 4 and an SiO ₂ layer 5 are formed on an Si semiconductor substrate 1 and then ßend a polysilicon control layer 6 deposited. The charges to be stored are preferably brought into the S 3 O ₄ layer 3 by means of injection of hot charge carriers, channel injection or Fowler-Nordheim tunnels and the S ₃ N ₄ layer 4 and stored there, as a result of which a switching behavior of a in the semiconductor substrate 1 trained field effect transistor is affected. A disadvantage of such a conventional SONOS semiconductor memory cell structure, however, is the insufficient temperature properties. In particular at temperatures greater than 80 degrees Celsius, the charge holding properties of the Si ₃ N ₄ layer 4 deteriorate dramatically, which leads to loss of information. To prevent such temperature phenomena, the thickness of the oxide layers 3 and 5 is usually increased, disadvantageously increasing the write / read voltages for the non-volatile semiconductor memory cell.

In addition, with such a structure, relatively high write / read voltages are required. FIG. 2 shows a simplified representation of the band model of a SONOS memory cell structure after application of a read / write voltage Uo. The voltage value of such a read / write voltage U ₀ is, for example, 8 V, this voltage present between semiconductor substrate 1 and control layer 6 being the individual voltages Ui and U ₃ for the oxide layers and U ₂ for the S ₃ N layer 4 split. According to FIG. 2, due to the S ₃ N _{4 used} as the charge-storing layer, there is a further disadvantage in that, due to the low relative dielectric constant E _r of approx V caused. This reduces the voltage drop occurring at the oxide layers, which is why higher write / read voltages must be used overall.

To eliminate such a temperature sensitivity and improve the writing / reading properties is from the DE 19830477 AI discloses a non-volatile semiconductor memory cell, the charge storage layer being made of an electrically conductive material and special oxide layers being formed in order to improve the temperature properties. Due to the use of a conductive material for the charge-storing layer, a voltage drop when a read / write voltage is applied across the charge-storing layer can be reduced, the data retention capability and the durability of the nonvolatile memory cell even at elevated operating temperatures through the use of the special additional oxide layers is guaranteed. However, the complex manufacturing process and the relatively high layer thicknesses between the charge-storing layer and the control layer are disadvantageous here.

The invention is therefore based on the object of providing a non-volatile semiconductor memory cell and an associated production method in which data retention and durability are reliably ensured, in particular at high operating temperatures, and programming with relatively low write / read voltages is realized can.

This task is solved with regard to the semiconductor memory cell by the features of claim 1 and with regard to the method by the measures of claim 9.

In particular, by using a dielectric with a band gap E _g <5 eV for the charge-storing layer, a non-volatile semiconductor memory cell is obtained which has sufficient charge retention and durability even at high operating temperatures.

When using a material for the charge storage

Layer with a relative dielectric constant E _r > 10 is also the voltage drop within the charge storage layer negligible compared to the voltage drop across the oxide, so that the programming voltage required for writing / reading is minimal.

Preferably, the charge-storing layer consists of TιO _x and / or WO _x with x = 2 to 3, whereby a sufficiently small band gap E _g and a sufficiently large relative dielectric constant E _{r is obtained} .

The charge-storing layer preferably has a microcrystalline structure, as a result of which the charge-holding properties are further improved. A further improvement in the charge holding properties results from the additional use of Si ₃ N layers on the surfaces of the charge-storing layer.

Further advantageous configurations of the invention are characterized in the further subclaims.

The invention is described below with reference to exemplary embodiments with reference to the drawing.

Show it:

1 shows a simplified representation of a band model of a conventional SONOS structure;

FIG. 2 shows a simplified illustration of the band model of the conventional SONOS structure when a write / read voltage is applied;

FIG. 3 shows a simplified representation of a band model of a semiconductor memory cell according to a first exemplary embodiment; FIG. 4 shows a simplified representation of a band model of a semiconductor memory cell according to a second exemplary embodiment;

FIG. 5 shows a simplified illustration of the band model of the semiconductor memory cell according to the first exemplary embodiment when a write / read voltage is applied; and

6a to 6e show perspective views of the semiconductor memory cell according to the first exemplary embodiment in respective manufacturing steps.

FIG. 3 shows a simplified representation of a band model of a semiconductor memory cell according to a first exemplary embodiment. FIG. 6E shows an associated perspective illustration of the semiconductor memory cell according to the first exemplary embodiment, active areas being formed in a semiconductor substrate 1 by forming a shallow trench isolation 2 (shallow trench isolation, STI). A first insulating layer 3 is formed on the surface of the semiconductor substrate 1 and has a relatively high band gap as a tunnel oxide layer and preferably consists of Si0 ₂ . 3 or 6E, a dielectric with a band gap Eg <5 eV is used as the charge-storing layer 4, preferably titanium oxide and / or tungsten oxide with a band gap of approximately 3 eV being used. The charge-storing layer 4 is completely surrounded by a second insulating layer 5, which in turn preferably consists of Si0 ₂ . Finally, there is a control layer 6 on the one described above

Layer stack, wherein the control layer 6 preferably consists of polysilicon and is used to control the field effect transistor structure formed in this way.

By using a dielectric for the charge-storing layer 4, one obtains one in the same way as in the above-described SONOS structure according to FIG non-volatile semiconductor memory cell with very good charge holding properties, which, in particular in the event of partial destruction of the first and / or second insulating layers 3 and 5, prevents the stored charges from escaping completely. Such disturbances or leakage currents through the first and / or second insulating layers 3 and 5 can be caused, for example, by incident α particles. Since the dielectric, in contrast to an electrically conductive charge-storing layer 4, essentially retains the charges in its installed locations, such a disturbance of the insulating layers only affects a limited space in the charge-storing layer 4, as a result of which the charge retention is improved.

On the other hand, the temperature properties of the semiconductor memory cell according to the invention are greatly improved since, in relative terms, the free electrons in the charge-storing layer 4 have a substantially higher energy barrier, i. H. must overcome first insulating layer 3 or second insulating layer 5. The energy barriers of the first and second insulating layers 3 and 5 are therefore only overcome by thermal excitation at substantially higher temperatures, which results in the improved temperature sensitivity of the semiconductor memory cell.

In particular when using TιO _x or W0 _X with x = 2 to 3, there are optimal values for the band gap Eg and the corresponding energy barrier of a respective Sι0 ₂ layer.

FIG. 4 shows a simplified representation of a band model of a semiconductor memory cell in accordance with a second exemplary embodiment, wherein in addition to the charge-storing layer 4 consisting of a dielectric with a small band gap, S ₃ N ₄ layers are formed for the first and second insulating layers 3 and 5. According to FIG. 4, a Si ₂ layer 3 and a charge-storing layer 4, which is preferably located on a silicon semiconductor substrate 1 consists of TιO _x and / or WO _x with x = 2 to 3. The S ₃ N ₄ layer 7a is located between the S ₂ layer 3 and the charge-storing layer 4, which prevents charge retention in the first insulating layer 3 and improves charge retention in the event of a damaged insulation layer. In the same way, a further S ₃ N layer can be formed on the surface of the second insulating layer 5, which in turn prevents charges from remaining in the second insulating layer 5 and improves the charge retention of the charge-storing layer 4 to the adjacent control layer 6 hm. In this way, the charge-holding properties of the semiconductor memory cell according to the invention are further improved while the temperature properties remain the same.

The use of a material for the charge-storing layer 4 with a high relative dielectric constant E _r > 10 results in a particularly advantageous reduction in the threshold voltages for the semiconductor memory cell and in particular for the programming or writing / reading voltages.

FIG. 5 shows a simplified representation of the band model of the semiconductor memory cell according to the first exemplary embodiment when a programming voltage U _{0 is applied} . According to FIG. 5, TιO _x and / or WO _x with x = 2 to 3 is again used as the charge-storing layer. Such a charge-storing layer 4 has a relative dielectric constant E _r of approximately 100 and, compared to the charge-storing layer of the conventional SONOS structure according to FIG. 2, is many times higher than the relative dielectric constant E _r of S ₃ N ₄ (E _r = 7, 2). Because of this high relative dielectric constant E _r , when a programming voltage Uo is applied, for example, the voltage drop across the charge-storing layer is relatively small and is, for example, U ₂ = 0.1 V. The voltages required for tunneling through the first and / or second insulating layers 3 and 5 Ui and U ₃ = 3 V can therefore be lower programming voltage U ₀ = 6.1 V can be realized. In contrast to the conventional SONOS structure, this results in significantly improved threshold voltages, which in turn has a positive effect on the implementation of corresponding generator circuits and the space required for this.

It has proven to be particularly advantageous if the charge-storing layer 4 is formed with a microcrystalline structure and consists, as it were, of a large number of individual blocks. The charge holding properties for storing introduced charges are thereby further improved, in particular a charge loss due to faults or defects in the insulating layers being further limited.

A method for producing the semiconductor memory cell according to the invention is described below. FIGS. 6A to 6E show perspective views to illustrate the method steps for the production of a semiconductor memory cell according to the first exemplary embodiment.

In the method step according to FIG. 6A, shallow trench isolation (STI process) is first carried out in a semiconductor substrate 1 to form active areas (AA). The semiconductor substrate 1 preferably consists of Si, SiGe, SiC, SOI, GaAs or another II IV semiconductor. The trenches exposed by the STI process are then filled with a TEOS-Si0 ₂ - and planarized. A first insulating layer 3 is then formed on the planarized surface. The first insulating layer 3 is preferably made of SiO ₂ and is deposited on the surface of the semiconductor substrate 1 or produced on it by thermal oxidation.

According to FIG. 6B, a charge-storing dielectric is now on the surface of the first insulating layer 3 Strei fenschicht 4 formed with a small band gap (Eg <5 eV). The charge-storing dielectric strip layer 4 also has a large number of longitudinal trenches Gl and can be produced in various ways.

Example 1 :

The charge-storing dielectric strip layer 4 can be formed, for example, by depositing a metal layer on the first insulating layer 3. Such deposition of the metal layer is preferably carried out in a sputtering process. In a subsequent process step, an oxidation of the metal layer is then carried out, wherein when using a Ti layer, for example in oxygen plasma at approximately 200 degrees Celsius to 300 degrees Celsius or in an RTP furnace at 700 degrees Celsius, the metal layer completely into a metal oxide layer or charge storage Layer 4 is converted. Subsequent to the oxidation of the metal layer, an etching is now carried out to produce the trenches Gl, an anisotropic reactive ion etching (RIE) preferably being carried out using an oxide hard mask. Such an oxide hard mask preferably has thicknesses of approximately 100 nm and can be formed by a TEOS deposition process using Si (C ₂ H ₅ 0 ₄ ). This oxide hard mask is used, for example

'■ Anisotropically etched by CHF ₃ , by CF ₄ or by a mixture of CHF ₃ and CF ₄ . For the etching of the metal oxide layer or charge-storing layer 4, for example, when using TiO ₂ , a mixed gas of CF ₄ and O _{2 is} used, the temperature being approximately 250 degrees Celsius. The mixed gas is excited by RF coupling or microwave excitation to form a plasma. The ratio of CF ₄ to 0 ₂ is preferably about 2% to 98%.

Alternatively, to form a WO _x layer as a metal oxide layer or charge-storing strip layer 4, a tungsten-containing layer, a pure tungsten layer, a tungsten ra nitride or a Wolfra silicide layer can be applied, which is generated with a conventional sputtering process or CVD process. After the tungsten-containing layer has been deposited, it is converted into a metal oxide layer in the same manner as described above, the conversion taking place in an oxygen atmosphere (for example 0 ₂ or H ₂ 0) at a temperature of 500 degrees Celsius to 1200 degrees Celsius ,

Example 2:

Alternatively, the charge-storing dielectric strip layer 4 can also be produced by depositing a metal layer and subsequent structuring, an oxidation and thus conversion into the charge-storing strip layer taking place in a last step. Such a production method has significant advantages, particularly in the structuring, since the respective deposited metal layers or metal-containing layers, in contrast to their oxide layers, can be etched relatively easily and the structuring is thereby greatly simplified.

Conventional etching methods, such as are preferably used for tungsten-containing or Ti layers, are used for the etching of the metal layers. A detailed description of these etching processes is therefore not given here.

The oxidation of the formed and structured metal layer then takes place in the same way as in Example 1.

Example 3:

Alternatively, the metal oxide layer can also be applied directly, the deposition of the metal-containing layer and the thermal oxidation of this layer being eliminated. The Wolfra The oxide layer is generated, for example, by a CVD process. For this purpose, tungsten fluoride and water in a gaseous state are led to the substrate surface as precursors:

2WF _S + 4H ₂ 0 → (WOF ₄ ) + W0 ₃ + (HF) or

WF ₆ + H ₂ 0 + Si → W - 0 + (2HF) + (Si + F ₄ ).

Subsequent heat treatment at a temperature of approx. 550 to 1100 degrees Celsius subsequently results in the tungsten oxide layer (WO _x with x = 2 to 3) in a microcrystalline or sintered phase (e.g. orthorhombic or tetragonal symmetry) in the same way as described above ) generated.

In particular due to the high temperature stability of WO _x , this material can be particularly easily integrated into the process.

The structuring takes place in the same way as described above.

After the formation of the charge-storing dielectric strip layer 4 with the three above-described embodiments, the second insulating layer 5 is then applied to the charge-storing dielectric strip layer 4, which is used as a floating gate layer, as shown in FIG. 6C. For example, an LPCVD (low pressure chemical vapor deposition) process can be used to form this second insulating layer 5. Here, an SiO ₂ layer is deposited either at a temperature of 650 degrees Celsius and a pressure of 100 mTorr using 100 SCCM TEOS. Alternatively, an SiO ₂ layer can be produced at a temperature of 680 degrees Celsius and a pressure of 500 mTorr using 150 SCCM TEOS. According to FIG. 6D, a conductive control layer 6 is subsequently deposited on the second insulating layer 5, which consists, for example, of polysilicon or another conductive material. The control layer 6 is preferably deposited over the entire surface as a polysilicon layer with a gas mixture of S lan and H ₂ at a temperature of 620 degrees Celsius.

According to FIG. 6E, in a further method step for forming further trenches G2, the control layer 6, the second insulating layer 5 and the charge-storing strip layer 4 are structured in order to form control layer tracks. This is preferably anisotropic reactive ion etching (RIE), an oxide hard mask (not shown) being used. Such an oxide hard mask preferably has a thickness of 100 nm and can be formed by a TEOS deposition process using Si (C ₂ H ₅ O ₄ ).

The actual etching for forming the further trenches G2 is carried out with respect to the poly-Si for the control layer 6 with Cl ₂ or HBr or a mixture of these two gases, it being possible for He and 0 _{2 to be} added. This is an anisotropic etching. For the etching of the charge-storing strip layer 4, when using Tι0 _2, for example, a mixed gas of CF ₄ and 0 _{2 is} used, the temperature being approximately 250 degrees Celsius. The mixed gas is in turn excited by an HF-E coupling or a microwave excitation to form a plasma. The ratio of CF ₄ to 0 _{2 is} preferably about 2% to 98%.

The released fluorine and the associated reaction of the metal oxide (Tι0 ₂ ) with the fluorine is responsible for the etching of the metal oxide layer or charge-storing dielectric strip layer 4 itself. Volatile metal-fluorine compounds form, with the oxygen acting as a passivator for the polysilicon that may be present takes over. By oxygen to form Sι0 _2, whose binding energy ^¬ (without the use of additional ion energy) is too high to be significantly etched by the low fluorine content. The charge-storing strip layer 4 is therefore etched selectively with respect to the control layer 6 (polysilicon).

Finally, a further insulating layer or passivation layer is applied in a method step, not shown.

According to the present description, titanium oxide or tungsten oxide is preferably used for the charge storage layer. However, it is not restricted to this, but rather includes all other materials which represent a dielectric with a small band gap and a high relative dielectric constant.

The first insulating layer 3 preferably consists of an SiO ₂ layer. However, it is not limited to this and can also consist of a Si ₃ N ₄ layer. In the same way, the second insulating layer is not limited to an Si0 ₂ layer, but rather comprises ONO (oxide / nitride / oxide) or Si ₃ N ₄ layers. Likewise, instead of the polysilicon for the control layer 6, another conductive material or a metal can be used.

The second insulating layer 5 can be formed in the same way by directly depositing a polysilicon layer on the charge-storing layer with subsequent temperature treatment, the second insulating layer 5 being subsequently formed at the border crossing to the charge-storing layer 4 during the heat treatment.

Claims

claims

1. A non-volatile semiconductor memory cell comprising: a semiconductor substrate (1); a first insulating layer (3); a charge storage layer (4); a second insulating layer (5); and a control layer (6) so that the charge-storing layer (4) has a dielectric with a band gap Eg <5 eV.

2. Non-volatile semiconductor memory cell according to claim 1, characterized in that the charge-storing layer (4) has a relative dielectric constant E _r > 10.

3. Non-volatile semiconductor memory cell according to claim 1 or 2, characterized in that the charge-storing layer (4) has TiO _x and / or WO _x with x = 2 to 3.

4. Non-volatile semiconductor memory cell according to one of the ' ^■ claims 1 to 3, characterized in that the charge-storing layer (4) has a microcrystalline structure.

5. Non-volatile semiconductor memory cell according to one of the claims 1 to 4, characterized in that an Si ₃ N ₄ layer is formed at least on one surface of the charge-storing layer (4).

6. Non-volatile semiconductor memory cell according to one of claims 1 to 5, characterized in that the first insulating layer (3) has an Si0 ₂ - or Si ₃ N ₄ layer.

7. Non-volatile semiconductor memory cell according to one of claims 1 to 6, characterized in that the second insulating layer (5) has a Si0 ₂ , ONO or Si ₃ N ₄ layer.

8. Non-volatile semiconductor memory cell according to one of the claims 1 to 7, that the control layer (6) comprises polysilicon or a metal.

9. A method for producing a non-volatile semiconductor memory cell, comprising the steps of: a) forming active regions in a semiconductor substrate (1); b) forming a first insulating layer (3); c) forming a charge-storing dielectric strip layer (4) with a band gap Eg <5 eV; d) forming a second insulating layer (5); e) forming a control layer (6); and f) structuring the control layer (6) and the charge storage layer (4).

10. The method according to claim 9, d a d u r c h g e k e n e z e i c h n e t that in step c) a metal layer is first deposited, then oxidized and finally structured.

11. The method according to claim 9, characterized in that in step c) a metal layer is first deposited, then structured and finally oxidized.

12. The method according to claim 9, so that a metal oxide layer is first deposited and finally structured in step c).

13. The method according to any one of claims 9 to 12, characterized by the step: bl) forming an SiN ₄ layer before forming the charge-storing dielectric strip layer (4).

14. The method according to any one of claims 9 to 13, characterized by the step: cl) forming an Si ₃ N ₄ layer after the formation of the charge-storing dielectric strip layer (4).

15. The method according to any one of claims 9 to 14, d a d u r c h g e k e n n z e i c h n e t that a Ti layer or W layer is deposited in step c).

16. The method according to any one of claims 9 to 15, d a d u r c h g e k e n n e e i c h n e t that a polysilicon layer is deposited in step e).

17. The method according to claim 16, so that the step d) is omitted and the second insulating layer (5) is partially formed from the control layer (6) by a heat treatment step.