WO2001035210A3 - Bus architecture and shared bus arbitration method for a communication processor - Google Patents

Bus architecture and shared bus arbitration method for a communication processor Download PDF

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Publication number
WO2001035210A3
WO2001035210A3 PCT/US2000/030305 US0030305W WO0135210A3 WO 2001035210 A3 WO2001035210 A3 WO 2001035210A3 US 0030305 W US0030305 W US 0030305W WO 0135210 A3 WO0135210 A3 WO 0135210A3
Authority
WO
WIPO (PCT)
Prior art keywords
bus
plural
architecture
masters
communication processor
Prior art date
Application number
PCT/US2000/030305
Other languages
French (fr)
Other versions
WO2001035210A2 (en
Inventor
Rainer R Hadwiger
Paul D Krivacek
Joern Soerensen
Palle Birk
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Priority to DE60027748T priority Critical patent/DE60027748T2/en
Priority to EP00976875A priority patent/EP1226493B1/en
Priority to AU14588/01A priority patent/AU1458801A/en
Publication of WO2001035210A2 publication Critical patent/WO2001035210A2/en
Publication of WO2001035210A3 publication Critical patent/WO2001035210A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7846—On-chip cache and off-chip main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W74/00—Wireless channel access
    • H04W74/04—Scheduled access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masters each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.
PCT/US2000/030305 1999-11-05 2000-11-03 Bus architecture and shared bus arbitration method for a communication processor WO2001035210A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE60027748T DE60027748T2 (en) 1999-11-05 2000-11-03 BUSARCHITECTURE AND DISTRIBUTED BUSARBITRATION PROCESS FOR A COMMUNICATION PROCESSOR
EP00976875A EP1226493B1 (en) 1999-11-05 2000-11-03 Bus architecture and shared bus arbitration method for a communication processor
AU14588/01A AU1458801A (en) 1999-11-05 2000-11-03 Bus architecture and shared bus arbitration method for a communication processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16381699P 1999-11-05 1999-11-05
US60/163,816 1999-11-05

Publications (2)

Publication Number Publication Date
WO2001035210A2 WO2001035210A2 (en) 2001-05-17
WO2001035210A3 true WO2001035210A3 (en) 2002-01-17

Family

ID=22591705

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2000/030305 WO2001035210A2 (en) 1999-11-05 2000-11-03 Bus architecture and shared bus arbitration method for a communication processor
PCT/US2000/030300 WO2001035234A1 (en) 1999-11-05 2000-11-03 Generic serial port architecture and system
PCT/US2000/030454 WO2001035246A2 (en) 1999-11-05 2000-11-06 Cache memory system and method for a digital signal processor

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/US2000/030300 WO2001035234A1 (en) 1999-11-05 2000-11-03 Generic serial port architecture and system
PCT/US2000/030454 WO2001035246A2 (en) 1999-11-05 2000-11-06 Cache memory system and method for a digital signal processor

Country Status (5)

Country Link
EP (3) EP1226505B1 (en)
CN (3) CN100353349C (en)
AU (3) AU1458501A (en)
DE (3) DE60027748T2 (en)
WO (3) WO2001035210A2 (en)

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US20050154928A1 (en) * 2004-01-08 2005-07-14 International Business Machines Corporation Remote power-on functionality in a partitioned environment
CN1661576B (en) * 2004-02-25 2010-04-28 中国科学院计算技术研究所 Dynamic frequency conversion device of bus in high speed and processor under SOC architecture
US7957428B2 (en) * 2004-05-21 2011-06-07 Intel Corporation Methods and apparatuses to effect a variable-width link
CN100389413C (en) * 2004-09-15 2008-05-21 北京中星微电子有限公司 Serial communiction bus external equipment interface
CN100388251C (en) * 2004-12-24 2008-05-14 刘龙威 Switch circuit shared by external data storage device and application system
US7348799B2 (en) * 2005-01-11 2008-03-25 Hewlett-Packard Development Company, L.P. System and method for generating a trigger signal
US7428603B2 (en) 2005-06-30 2008-09-23 Sigmatel, Inc. System and method for communicating with memory devices via plurality of state machines and a DMA controller
JP4747896B2 (en) * 2006-03-17 2011-08-17 ソニー株式会社 Information processing apparatus and method, and program
US7930576B2 (en) * 2007-04-10 2011-04-19 Standard Microsystems Corporation Sharing non-sharable devices between an embedded controller and a processor in a computer system
CN101840385B (en) * 2009-03-19 2012-07-18 承景科技股份有限公司 Data access system
CN102654853B (en) * 2011-03-04 2015-03-04 上海华虹集成电路有限责任公司 Nandflash controller adopting two microprocessors
CN102662911A (en) * 2012-03-19 2012-09-12 中国科学院上海技术物理研究所 Control method for board-level reconfiguration infrared signal processor
US9129072B2 (en) 2012-10-15 2015-09-08 Qualcomm Incorporated Virtual GPIO
US9946675B2 (en) * 2013-03-13 2018-04-17 Atieva, Inc. Fault-tolerant loop for a communication bus
CN104216857B (en) * 2013-05-31 2017-09-22 英业达科技有限公司 Multiplexing switching device and its switching method
FR3026869B1 (en) * 2014-10-07 2016-10-28 Sagem Defense Securite ON-CHIP ON-CHIP SYSTEM WITH HIGH OPERATING SAFETY
US9450582B2 (en) 2015-02-03 2016-09-20 Freescale Semiconductor, Inc. Programmable buffer system
CN116401184A (en) * 2016-01-22 2023-07-07 索尼互动娱乐股份有限公司 Simulating backward compatible legacy bus behavior
GB2553338B (en) * 2016-09-02 2019-11-20 Advanced Risc Mach Ltd Serial communication control
CN106980577B (en) * 2017-03-20 2020-04-28 华为机器有限公司 Input/output processing method and device and terminal
US10558604B2 (en) * 2017-12-20 2020-02-11 Qualcomm Incorporated Communication interface transaction security
CN109725250B (en) * 2019-01-04 2021-07-13 珠海亿智电子科技有限公司 System and method for testing system-on-chip analog circuit
CN111045980A (en) * 2019-12-24 2020-04-21 广东嘉泰智能技术有限公司 Multi-core processor
CN114297105B (en) * 2021-12-29 2024-04-05 合肥市芯海电子科技有限公司 Embedded control circuit, chip and electronic equipment for direct memory access

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EP0426413A2 (en) * 1989-11-03 1991-05-08 Compaq Computer Corporation Multiprocessor arbitration in single processor arbitration schemes
EP0702307A1 (en) * 1994-08-08 1996-03-20 International Business Machines Corporation Multibus dynamic arbiter
WO1999026155A1 (en) * 1997-11-13 1999-05-27 Virata Limited Peripheral servicing
EP0924623A2 (en) * 1997-12-22 1999-06-23 Compaq Computer Corporation Computer system including arbitration mechanism allowing multiple bus masters to access a graphics bus

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EP0426413A2 (en) * 1989-11-03 1991-05-08 Compaq Computer Corporation Multiprocessor arbitration in single processor arbitration schemes
EP0702307A1 (en) * 1994-08-08 1996-03-20 International Business Machines Corporation Multibus dynamic arbiter
WO1999026155A1 (en) * 1997-11-13 1999-05-27 Virata Limited Peripheral servicing
EP0924623A2 (en) * 1997-12-22 1999-06-23 Compaq Computer Corporation Computer system including arbitration mechanism allowing multiple bus masters to access a graphics bus

Also Published As

Publication number Publication date
DE60027748D1 (en) 2006-06-08
EP1226493B1 (en) 2006-05-03
EP1236122A2 (en) 2002-09-04
EP1236122B1 (en) 2004-02-04
CN100336046C (en) 2007-09-05
DE60017775T2 (en) 2006-01-12
WO2001035246A3 (en) 2002-07-11
DE60027748T2 (en) 2007-04-05
DE60008139T2 (en) 2004-11-18
CN1387646A (en) 2002-12-25
CN100353349C (en) 2007-12-05
CN1279472C (en) 2006-10-11
DE60017775D1 (en) 2005-03-03
CN1387645A (en) 2002-12-25
AU1458801A (en) 2001-06-06
AU1465001A (en) 2001-06-06
DE60008139D1 (en) 2004-03-11
EP1226505B1 (en) 2005-01-26
CN1399743A (en) 2003-02-26
WO2001035234A9 (en) 2002-05-30
AU1458501A (en) 2001-06-06
EP1226493A2 (en) 2002-07-31
WO2001035210A2 (en) 2001-05-17
WO2001035246A2 (en) 2001-05-17
EP1226505A1 (en) 2002-07-31
WO2001035234A1 (en) 2001-05-17

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