WO2001029890A2 - Method relating to anodic bonding - Google Patents

Method relating to anodic bonding Download PDF

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Publication number
WO2001029890A2
WO2001029890A2 PCT/SE2000/002012 SE0002012W WO0129890A2 WO 2001029890 A2 WO2001029890 A2 WO 2001029890A2 SE 0002012 W SE0002012 W SE 0002012W WO 0129890 A2 WO0129890 A2 WO 0129890A2
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WO
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Patent type
Prior art keywords
member
characterised
bonding
method according
wafer
Prior art date
Application number
PCT/SE2000/002012
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French (fr)
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WO2001029890A3 (en )
Inventor
Leif Bergstedt
Gert Andersonn
Britta Ottosson
Original Assignee
Imego Ab
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01011Sodium [Na]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01058Cerium [Ce]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Abstract

The present invention relates to a method of bonding a first member (110, 210, 130, 230, 410, 430, 510, 530, 610) to a second silicon member (120, 220, 420a, 420b, 600) through anodic bonding. The method comprises the steps of selectively depositing on said first member bondable sections (170a, 170b, 270, 470a, 470b, 470c, 570, 620) before bringing said first and second members together for anodic bonding.

Description

TITLE

METHOD RELATING TO ANODIC BONDING

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method of bonding at least a first member to a second silicon member through anodic bonding.

BACKGROUND OF THE INVENTION

EP 742 581, for example, relates to a method of making sealed cavities on silicon wafer surfaces by anodic bonding and with electrically insulated conductors through the sealing areas to connect functional devices inside the cavities to electrical terminals outside said cavities. The conductors are provided through the use of doped buried crossings in a single crystal silicon substrate, thereby also allowing production of different kinds of integrated silicon devices, e.g. sensors.

The technique implies that Borosilicate glass plates are bonded onto a silicon (Si) wafer using so-called anodised bonding. A plate of glass is arranged on a Si wafer under an amount of pressure. The Si wafer and the glass are then heated up to some hundred degrees and a voltage is applied across the plates (glass and wafer) whereby the glass, which contains sodium (Na) ions migrate into the Si wafer, and a hermetic junction is obtained.

When two Si wafers are to be connected, a similar method as mentioned above is carried out, however, one of the wafers is coated with sputtered borosilicate glass and an anodised bonding is performed.

Generally, to be able to achieve an anodised bonding the object intended to be bonded to Si must contain Na-ions. usually through doping a glass with Soda lime glass. The reason for using borosilicate glass is that it matches the Si wafer characteristics, specially with respect to coefficient of expansion.

One major problem related to above mentioned and similar methods is the possibility of providing a conducting arrangement through the glass or wafer. In above mentioned European Patent No. 742 581, for example, the electrical connection path is from one of an outside wire bonding area via a first contact diffusion down to a buried conductor which crosses below the sealing area of the cavity, and via a second contact diffusion to a second aluminium interconnection line which establishes connections to two piezo-resistors.

SUMMARY OF THE INVENTION

The main object of the present invention is to provide a method of providing a hermetical sealing between a first substrate and a silicon substrate.

Another object of the present invention is to achieve a hermetical sealing through selective deposition of bondable surfaces on a first substrate and the silicon substrate. Yet another object of the invention is to provide electrical connection between the sealed space and the outside environment through or under the sealing section.

For these reasons, the initially mentioned method comprises the steps of selectively depositing on said first member at least one bondable section before bringing said first and second members together for anodic bonding.

Preferably, the first member is a glass wafer, specially a borosilicate glass wafer and said second wafer is a silicon wafer or the first member is a carrier wafer specially one of glass, ceramics or glass composite, such as LTCC (Low Temperature Cofired Ceramic) and said second wafer is a silicon wafer. The bondable section comprises a paste containing Na ions.

Preferably, the selective deposition is provided through screen printing or photo image forming.

Most preferably, depending on the function of the circuitry the bonding is hermetical. Preferably, said first member comprises of a cover, that said second silicon member is a carrier for a functional device and said first member bonded to said second member provides a sealing for said functional device. Moreover, a third member is arranged as a carrying member for supporting said second member.

In one embodiment, electrical connections are arranged out of said cover through said bonding sections and/or said third supporting member.

Preferably, said connections through said bonding sections are arranged on one of said first, second or third members before applying the bonding paste. The bonding sections are provided on said first member.

According to the invention, a method of selectively bonding a first member to a second silicon member through anodic bonding is provided, wherein the method comprises the steps of: providing the said first and second members, arranging said first member with bonding sections in predetermined sections, arranging said first and second members in a contacting position, pressing and heating said first and second members in said contacting position, and applying a voltage to said first and second members. Preferably, the second member is a silicon wafer comprising one or more active sections. The first member is a glass wafer provided with frames corresponding to said active sections.

The invention also concerns a sensor comprising a lid, a silicon substrate and a carrying substrate, wherein said lid, silicon substrate and carrying substrate are bonded through the method f the invention.

The invention also concerns a biological circuit hermetically connected to a substrate using the method f the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following, the invention will be further described in a non-limiting way with reference to the accompanying drawings in which:

Fig. 1 schematically illustrates an arrangement produced according to the teachings of the invention, Figs. 2a, 2b shows the wafers for anodic bonding process according to the invention in plan view, Fig. 3 shows a cross-section along line III-III in figs. 2a and 2b, in a preassembled form, Figs. 4a, 4b,4c are cross-sections through different schematic embodiments showing wiring according to the invention,

Fig. 5 is a cross-section through yet another embodiment, and

Fig. 6 is a schematic cross-section through a device bonded according to another aspect of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

According to one preferred embodiment paste, e.g. of thick or thin film is through, e.g. screen printing or photo image forming, with doping containing Na ions, provided with conductive and non conductive sections which are bondable through anodic bonding. The carrier section may be one of glass, ceramics or glass composite, such as LTCC (Low Temperature Cofired Ceramic).

There are a number of different thick-film pastes with different glass mixtures. It is also possible to produce pastes with sodium or soda-lime content, both as dielectric and conductive pastes. However, the object of these is to provide a glass composition which matches the substrate to be printed.

Fig. 1 is a cross section through a device 100, e.g. a sensor according to above mentioned sensor of EP 742 581. The device comprises a cover or lid 110, e.g. of borosilicate glass or other glass composition, a semiconducting wafer 120, a substrate 130, preferably a multi layer substrate including conductors 140 and vias 150 arranged therein and solder pads 160. The lid 110 is bonded to the Si wafer 120 through bonding areas 170a, provided in accordance with the teachings of the present invention. The substrate 130 is also bonded to the Si wafer 120 through bonding areas 170b, provided in accordance with the teachings of the present invention. The bonding areas 170 and 170b are provided as a paste on the lid 110 and carrier substrate 130, respectively, as closed frames through screen printing and/or photo image forming or the like.

The electronic circuitry or functional devices 180 arranged on the silicon (Si) wafer 120 are connected to the conductors 140, e.g. through connections 185 via the Si wafer. It is also possible to arrange connections that pass the bonding paste of the connection areas 170a and/or 170b, which will be exemplified in the following embodiments. The electronic circuitry 180 is further connected to other circuits through solder pads 160.

In a sensor, filter or similar applications both the lid 110 and the substrate 130 can be provided with cavities 190a and 190b, respectively.

Fig. 2a is a plane view of lid wafer 210 of glass on which a number of sealing frames 270 of a paste material containing Na-ions are printed, e.g. through screen printing. The frames provide a closed space building the cavities 290. On the other side, i.e. fig. 2b, functional devices 280 are realised on a Si wafer 220, which can be arranged on a carrying substrate 230 (fig. 3), which also is provided with bonding frames or sections 270b.

Fig. 3 illustrates the moment before the glass wafer 210 of fig. 2a is bonded onto the Si wafer 220 of fig. 2b. After the bonding process packaged units are formed, and each unit is cut out later in a suitable way well known for a skilled person.

In fig. 3, the functional devices 280 may also be countersunk in the substrate 220 through micro-machining or the like depending on the application and/or the material of the substrate.

The bonding process is performed in a known way, i.e. the Si wafer 220 and the lid glass wafer 210 or carrier 230 are combined and exposed to a pressure and heat up to a specific level, for example 350 °C (not limited) and then a voltage, e.g. 800 V (not limited), is applied through the stack comprising the Si wafer and the lid wafer and/or the carrier.

Here, it is possible to provide different ways of electrical connections out of the functional devices arranged inside the sealed area on the semiconductive material 230: Firstly, according to fig. 1, i.e. through the carrying substrate 130 and secondly through the sealing frame

270/270b. In the embodiment of fig. 4a, a substrate 420a is provided with conductors 440a, e.g. through etching or the like. Then the paste 470a (thin film paste) applied onto the glass 410 is pressed on the substrate 420a.

In fig. 4b a thick-film paste 470b is applied through, e.g. screen printing onto the glass 410. Conductors 440b having substantially the same thickness as the paste are arranged through a suitable method on the substrate 430b, e.g. alumina.

Clearly, other embodiments are also possible as shown in fig. 4c, in which a substrate 430 of LTCC is used and into which conductors 440c are immersed. Paste 470c is applied onto the glass 410 before bonding.

As shown in fig. 5, it is also possible to countersink the pastes 570 into the substrate 530 of LTCC so that the upper surface of the paste comes into a substantially same level as the upper surface of the LTCC. The glass is denoted with 510.

Additionally, the bonding according to the invention can be used as a sealing in further applications. In fig. 6, for example, a so-called biological circuit 600 is connected to a substrate 610. The biological circuit comprises a conduit 601 for transporting fluid or gas. It is possible to connect and seal the circuit to an external substrate 610 of, e.g. LTCC of another circuit likewise provided with a conduit 611 using the teachings of the invention, i.e. arranging a ring shaped paste bonding means 620 and anodically bonding the circuit to the substrate or other circuits.

The invention is not limited the shown embodiments but can be varied in a number of ways without departing from the scope of the appended claims and the arrangement and the method can be implemented in various ways depending on application, functional units, needs and requirements etc.

Claims

1. Method of bonding at least a first member (110, 210, 130, 230, 410, 430, 510, 530, 610) to a second silicon member (120, 220, 420a, 420b, 600) through anodic bonding, characterised by selectively depositing on said at least first member at least one bondable section (170a, 170b, 270, 470a, 470b, 470c, 570, 620) before bringing said first and second members together for anodic bonding.
2. The method according to claim 1, characterised in that said first member (110, 210, 410, 510) is a glass wafer, specially a borosilicate glass wafer and said second wafer is a silicon wafer (120, 220, 420).
3. The method according to claim 1 , characterised in that said first member is a carrier wafer (130, 230, 430, 530) specially one of glass, ceramics or glass composite, such as LTCC (Low Temperature Cofired Ceramic) and said second wafer is a silicon wafer.
4. The method according to any of preceding claims, characterised in that said bondable section (170a, 170b, 270, 470a, 470b, 470c, 570, 620) comprises a paste containing Na ions.
5. The method according to any of preceding claims, characterised in that said selective deposition is provided through screen printing or photo image forming.
6. The method according to any of preceding claims, characterised in that said bonding is hermetical.
7. The method according to any of preceding claims, characterised in that said first member constitutes a cover, that said second silicon member is a carrier for a functional device (180, 280, 600) and said first member bonded to said second member provides a sealing for said functional device.
8. The method according claim 7, characterised in that a third member is arranged as a carrying member for supporting said second member.
9. The method according claim 7, characterised in that electrical connections out of said cover are arranged through said bonding sections.
10. The method according claim 8, characterised in that electrical connections out of said cover are arranged through said third supporting member.
11. The method according any of claims 8-10, characterised in that said connections through said bonding sections are arranged on one of said first, second or third members before applying the bonding paste.
12. The method according to any of preceding claims, characterised in that said bonding sections are provided on said first member.
13. A method of selectively bonding a first member (110, 210, 130, 230, 410, 430, 510, 530, 610) to a second silicon member (120, 220, 420a, 420b, 600) through anodic bonding, characterised in that said bonding method comprises the steps of:
- providing the said first and second members,
- arranging said first member with bonding sections in predetermined sections, - arranging said first and second members in a contacting position,
- pressing and heating said first and second members in said contacting position, and
- applying a voltage to said first and second members.
14. The method according to claim 13, characterised in that second member is a silicon wafer comprising one or more active sections.
15. The method according to claim 14, characterised in that said first member is a glass wafer provided with frames corresponding to said active sections.
16. A sensor (100) comprising a lid (1 10), a silicon substrate (120), a carrying substrate (130) and sensor electronics, wherein said lid (1 10), silicon substrate (120) and carrying substrate (130) are bonded through one or several of methods according to any one of claims 1-15.
17. A biological circuit (600) hermetically connected to a substrate (610) using one or several of methods according to any one of claims 1-15.
PCT/SE2000/002012 1999-10-19 2000-10-17 Method relating to anodic bonding WO2001029890A3 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US16041199 true 1999-10-19 1999-10-19
US60/160,411 1999-10-19
SE9903798A SE522141C2 (en) 1999-10-19 1999-10-19 Bonding method for sensor and biological circuit, involves selectively depositing bondable section on a member before bonding the member with silicon member together for anodic bonding
SE9903798-8 1999-10-19

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
AU1183101A AU1183101A (en) 1999-10-19 2000-10-17 Method relating to anodic bonding
US10111138 US6951797B1 (en) 1999-10-19 2000-10-17 Method relating to anodic bonding
JP2001531139A JP2003512723A (en) 1999-10-19 2000-10-17 Method for anodic bonding
EP20000973305 EP1234330A2 (en) 1999-10-19 2000-10-17 Method relating to anodic bonding

Publications (2)

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WO2001029890A2 true true WO2001029890A2 (en) 2001-04-26
WO2001029890A3 true WO2001029890A3 (en) 2001-09-07

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PCT/SE2000/002012 WO2001029890A3 (en) 1999-10-19 2000-10-17 Method relating to anodic bonding

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EP (1) EP1234330A2 (en)
JP (1) JP2003512723A (en)
WO (1) WO2001029890A3 (en)

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WO2002050888A2 (en) * 2000-12-19 2002-06-27 Harris Corporation Method for making electronic devices including silicon and ltcc
US7153759B2 (en) 2004-04-20 2006-12-26 Agency For Science Technology And Research Method of fabricating microelectromechanical system structures
US7192841B2 (en) 2002-04-30 2007-03-20 Agency For Science, Technology And Research Method of wafer/substrate bonding
GB2408145B (en) * 2003-10-24 2007-06-06 Miradia Inc Method and system for hermetically sealing packages for optics
US7259466B2 (en) 2002-12-17 2007-08-21 Finisar Corporation Low temperature bonding of multilayer substrates
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Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002050888A3 (en) * 2000-12-19 2003-08-07 Harris Corp Method for making electronic devices including silicon and ltcc
US6809424B2 (en) * 2000-12-19 2004-10-26 Harris Corporation Method for making electronic devices including silicon and LTCC and devices produced thereby
US6987033B2 (en) 2000-12-19 2006-01-17 Harris Corporation Method for making electronic devices including silicon and LTCC and devices produced thereby
WO2002050888A2 (en) * 2000-12-19 2002-06-27 Harris Corporation Method for making electronic devices including silicon and ltcc
US7192841B2 (en) 2002-04-30 2007-03-20 Agency For Science, Technology And Research Method of wafer/substrate bonding
US7259466B2 (en) 2002-12-17 2007-08-21 Finisar Corporation Low temperature bonding of multilayer substrates
US7361593B2 (en) 2002-12-17 2008-04-22 Finisar Corporation Methods of forming vias in multilayer substrates
US7671461B2 (en) 2003-10-24 2010-03-02 Miradia Inc. Method and system for hermetically sealing packages for optics
US7303645B2 (en) * 2003-10-24 2007-12-04 Miradia Inc. Method and system for hermetically sealing packages for optics
GB2439403A (en) * 2003-10-24 2007-12-27 Miradia Inc Hermetically sealed wafer level packaging for optical MEMS devices
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JP2003512723A (en) 2003-04-02 application
EP1234330A2 (en) 2002-08-28 application

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