GB2443573A - Hermetically sealed optoelectronic MEMS wafer level package - Google Patents

Hermetically sealed optoelectronic MEMS wafer level package Download PDF

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Publication number
GB2443573A
GB2443573A GB0801228A GB0801228A GB2443573A GB 2443573 A GB2443573 A GB 2443573A GB 0801228 A GB0801228 A GB 0801228A GB 0801228 A GB0801228 A GB 0801228A GB 2443573 A GB2443573 A GB 2443573A
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United Kingdom
Prior art keywords
regions
substrate
region
recessed
transparent member
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Granted
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GB0801228A
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GB0801228D0 (en
GB2443573B (en
Inventor
Xiao Yang
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Miradia Inc
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Miradia Inc
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Priority claimed from US10/693,323 external-priority patent/US7303645B2/en
Application filed by Miradia Inc filed Critical Miradia Inc
Priority to GB0801228A priority Critical patent/GB2443573B/en
Priority claimed from GB0703881A external-priority patent/GB2439403B/en
Publication of GB0801228D0 publication Critical patent/GB0801228D0/en
Publication of GB2443573A publication Critical patent/GB2443573A/en
Application granted granted Critical
Publication of GB2443573B publication Critical patent/GB2443573B/en
Expired - Fee Related legal-status Critical Current
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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
    • G02B26/08—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
    • G02B26/0816—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements
    • G02B26/0833—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

Optoelectronic MEMS devices 350, for example, micro-mirror chips are mounted on a silicon CMOS wafer 344 and hermetically sealed in an inert gas environment within a recess of a transparent lid 352 bonded to the wafer. Individual devices are separated by subdividing the wafer/lid structure.

Description

METHOD AND SYSTEM FOR RERMETECALEY SEALING
PACKAGES FOR OPTICS
BACKGROUND OF THE INVENTION
f000fl This present invention relates generally to manufacturing objects. More particularly, the invention provides a method and structure for hermetically bonding a transparent cover to a semiconductor substrate. Merely by way of example, the invention has been applied to a transparent glass cover hemietically bonded to a semiconductor wafer containing a micro-mechanical electrical system. The method and structure can be applied to display technology as well as, for example, charge coupled display camera arrays, and infrared arrays.
0O02J The packaging of silicon integrated circuits has reached a high level of maturity.
FIG. I illustrates a simplified diagram of a conventional silicon integrated circuit package.
The silicon integrated circuit die 110 is mounted on a submount 115 featuring a ball grid array 120. Wire bonds 125 arc attached to the silicon die 110 to provide electrical connection to the submount 115. Typically, the silicon die 110 and the wire bonds 125 are encapsulated using a plastic encapsulant 130. The resulting package is robust and inexpensive.
100031 The package illustrated in FIG. 1 presents several drawbacks in applications that often require more than electrical operation of the silicon integrated circuit. An example of such an application is optical reflection off an array of micro-mirrors or other MEMS structure. For example, these applications typically require the ability to illuminate the top of the silicon integrated circuit with optical energy and subsequently reflect the optical energy off the top of the silicon integrated circuit with high efficiency. The optical properties of the plastic encapsulant, including lack of transparency, non-unifonnity of the index of refraction, and surface roughness make these packages unsuitable for this application. Additionally, many MEMS often require an open space above the surface of the silicon integrated circuit to enable the micro-electro-mechanical structures to move in the direction parallel to the plane of the MEMS as well as in the direction perpendicular to the plane of the MEMS. The physical contact that the plastic encapsulant makes with the surface of the integrated circuit, therefore, make this package unsuitable for many MEMS applications.
SUMMARY OF THE [NV ENT ION
(00041 This present invention relates generally to manufacturing objects. More particularly, the invention provides a method and structure for hermetically bonding a transparent cover to a semiconductor substrate. Merely by way of example, the invention has been applied to a transparent glass cover hermetically bonded to a semiconductor wafer containing a micro-mechanical electrical system. The method and structure can be applied to display technology as well as, for example, charge coupled display camera arrays, and infrared arrays.
According to one aspect of the present invention, there is provided a method for hermetically sealing devices, the method comprising: providing a substrate, the substrate Including a plurality of Individual chips, each of the chips including a plurality of devices, each of the chips being arranged In a spatial manner as a first array, the array configuration including a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips, the second street regions intersecting the first street regions to form the array configuration; providing a transparent member of a predetermined thickness, the transparent member including a plurality of recessed regions within the predetermined thickness and arranged in a spatial manner as a second array, each of the recessed regions being bordered by a standoff region, the standoff region having a thickness defined by a portion of the predetermined thickness; aligning the transparent member in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips whereupon the standoff region is coupled to each of the plurality of first street regions and coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions; and hermetically sealing each of the chips within one of the respective recessed regions by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions. Any aspect of the invention may include any of the following preferable features or combination of them.
According to a further aspect of the present invention1 there is provided a system for hermeticafly sealing devices, the system comprising: a substrate, the substrate configured to include a plurality of individual chips, wherein each of the chips includes a plurality of devices; wherein each of the chips are arranged in a spatial manner as a first array, the array configuration including a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips, the second street regions intersecting the first street regions to form the array configuration; a transparent member of a predetermined thickness, the transparent member configured to include a plurality of recessed regions within the predetermined thickness, wherein the plurality of recessed regions are arranged in a spatial manner as a second array, and wherein each of the recessed regions are bordered by a standoff region having a thickness defined by a portion of the predetermined thickness; wherein the substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips, whereupon the standoff region is coupled to each of the plurality of first street regions and is coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions; and wherein each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.
According to a further aspect of the present invention there is provided a method of hermetically sealing devices wherein a plurality of chips including devices are provided in an array on a substrate with space regions therebetween and wherein a transparent number having a corresponding array of recessed regions bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose each chip within a recessed region.
According to a further aspect of the present invention there is provided a system of hermetically sealed wherein a plurality of chips including devices are provided in an array on a substrate with space regions therebetween and wherein a transparent number having a corresponding array of recessed regions bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose each chip within a recessed region.
Any aspect of the invention may comprise any of the following preferable features.
either in combination or otherwise.
Preferably each of the first street regions has a first width ranging from about 0.5 mm to 1.0 mm in dimension and each of the second street regions has a second width ranging from about 0.5 mm to 1.0mm in dimension.
Preferably the transparent member has an optical power transmittance of greater than about 99%.
Preferably the transparent member is characterized by a coefficient of thermal expansion OT. the coefficient of thermal expansion is about the same as a coefficient of thermal expansion as of the substrate.
Preferably the transparent member comprises an antirereflective coating disposed overlying surface regions of each of the recessed regions.
Preferably the recessed regions are formed by a process selected from dry or wet etching, laser machining, acoustic machining, and casting.
Preferably the transparent member comprises a first transparent member overlying a standoff layer, the standoff layer including the standoff region.
Preferably the standoff layer comprises a second transparent member.
Preferably the bonding process is selected from at least a plasma activated bonding, eutectic bonding, glue layer or adhesive bonding, welding, anodic bonding, and fusion bonding.
Preferably the transparent member is characterized by a thickness ranging from about 0.1 mmto 1.2 mm.
Preferably each of the chips is maintained within an inert environment within one of the respective recessed regions.
Preferably the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.
Preferably the inert environment causes a damping process.
Preferably the inert environment causes a reduction in electrical breakdown.
Preferably each of the chips comprises an interconnect region, the interconnect region being outside of the recessed region.
Preferably the interconnect region is exposed through a through hole region on the transparent member.
Preferably the interconnect region comprises a plurality of bonding pads.
Preferably the substrate comprises a silicon bearing material.
Preferably the substrate is a silicon wafer.
Preferably each of the recessed regions comprises a first surface region coupled to a second surface region, the first surface region and the second surface region characterized to be of optical quality.
Preferably the first surface region has a root mean square surface roughness of less than or equal to 2 A for a 2 pm by 2 pm area Preferably each of the recessed regions is annular In shape.
Preferably each of the recess regions has a depth of about 0.5 mm and less.
Preferably the transparent member comprises a first side and a second side, the first side being parallel to the second side, the first side and the second side being coated with an antireflective material.
Preferably the coating of antireflective material reduces the reflectance of visible iight at the first side and the second side to less than 2% per side.
Preferably each of the recessed regions has a peripheral region that filters out light Preferably each of the recessed regions has a peripheral region that fomis an aperture region overlying a portion of one of the respective chips.
Preferably at least one of the plurality of devices comprises a plurality of charge coupled devices, a plurality of deflection devices, a plurality of sensing devices, and an integrated circuit device.
Preferably the antireflective material comprises MgF2.
Preferably the method further comprises dicing at least one of the chips by scribing a portion of each of the first street regions and by scribing a portion of each of the second street regions; attaching at least one of the chips within one of the respective recessed regions to a lead frame structure; wire bonding a portion of the attached chip to a portion of the lead frame structure; and encapsulating the wire bonded portion of the attached chip and the portion of the lead frame structure while maintaining a surface region of the transparent substrate defined on the recessed region free of encapsulant.
Preferably the system further comprises a lead frame structure; wherein at least one of the chips is diced by scribing a portion of each of the first street regions and by scribing a portion of each of the second street regions, wherein at least one of the chips within one of the respective recessed regions is attached to the lead frame structure; wherein a portion of the attached chip is wire bonded to a portion of the lead frame structure; and wherein the wire bonded portion of the attached chip and the portion of the lead frame structure is encapsulated while maintaining a surface region of the transparent substrate defined on the recessed region free of encapsulant.
Further aspects of the invention are set out in the attached independent claims and further preferable features are recited in the dependant claims.
10005J In a specific embodiment according to the present invention, a method for hermetically sealing devices is provided. The method includes providing a substrate that includes a plurality of individual chips, each of the chips including a plurality of devices. In this specific embodiment according to the present invention, the chips arc arranged in a spatial maimer as a first array. The array configuration in this embodiment includes a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips. The second street regions intersect the first street regions to form the array configuration. The method also includes pmviding a transparent member of a predetennined thickness. The transparent member in this embodiment includes a plurality of recessed regions within the predetermined thickness and arranged in a spatial manner as a second array. Preferably, each of the recessed regions is bordered by a standoff region. In this specific embodiment, the standoff region has a thickness defined by a portion of the predetermined thickness. The method also includes aligning the transparent member in a maimer to couple each of the plurality of recessed regions to a respective one of said plurality of chips. The transparent member is aligned such that the standoff region is coupled to each of the plurality of first street regions and is coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions. The method also includes hermetically sealing each of the chips within one of the respective recessed regions by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions. Preferably, the hermetic sealing uses at least a bonding process to isolate each of the chips within one of the recessed regions.
(0006J In an alternative specific embodiment, the invention provides a system for hermetically sealing devices. The system comprises a substrate configured to include a plurality of individual chips. Each of the chips includes a plurality of devices. Addtionally, each of the chips arc arranged in a spatial manner as a first array. The array configuration includes a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips. The second street regions intersect the first street regions to form the array configuration. The system further comprises a transparent member of a predetermined thickness. The transparent member is configured to include a plurality of recessed regions within the predetermined thickness. The plurality of recessed regions are arranged in a spatial manner as a second array. Furthermore, each of the recessed regions are bordered by a standoff region having a thickness defined by a portion of the predetermined thickness. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Accordingly, the standoff region is coupled to each of the plurality of first street regions and is coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second Street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.
[0007J These and other objects and features of the present invention and the manner of obtaining them will become apparent to those skilled in the art, and the invention itself will be best understood by reference to the following detailed description read in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[00081 FIG. I is a simplified diagram of a conventional silicon integrated circuit package.
[0009J FIG. 2 is a s mplified diagram of a conventional hermetically scaled transparent integrated circuit package.
(O010J FIGS. 3A -3D are simplified diagrams of a wafer-level hermetically scaled package according to an embodiment of the present invention.
fOOllJ FIGS. 4A and 4B are simplified diagrams of a transparent member according to an embodiment of the present invention formed from two transparent components.
[0012) FIG. 5A is a simplified top view of a transparent member and substrate according to an embodiment of the present invention at the time of hermetic sealing.
S
(00131 FIG. 5B is a simplified diagram of four transparent members and a substrate according to an alternative embodiment of the present invention at the time of hermetic sealing.
(0014J FIGS. 6 is a simpLified diagram of a single micro-mirror chip after hermetic sealing according to an embodiment of the present invention.
(0015J FIG. 7 is a simplified diagram of a die level package including a hermetically sealed die according to an embodiment of the present invention.
f0016J FIG. 8 is a simplified diagram illustrating the operation of a reflective system according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
(00171 According to the present invention, techniques for manufacturing objects are provided. More particularly, the invention provides a method and system for hermetically sealing packages for objects. Merely by way of example, the invention has been applied to the hermetic sealing of an optical micro-mirror package. The method and system can be applied to sensor technology as well as other MEMS devices where hermetic packaging is required.
(0018J FIG. 2 illustrates a simplified diagram of a conventional hermetically sealed transparent integrated circuit package useful for optical illumination of a micro-mirror array.
In FIG. 2, a silicon MEMS die 210 featuring a micro-mirror array 215 is mounted on a submount 220. The die is attached to the submount using die attach procedures that are compatible with hermetically sealed packaging requirements well known to those skilled in the art. Wre bonds 225 are attached to the silicon die and the submount as with the package illustrated in FIG. 1.
f0019J To provide an open space above the micro-mirror array 215, a solid standoff 230 is typically placed near the outer edge of the submount. This standoff is typically shaped as a square annulus and fabricated from covar or other suitable materials. The standoff is often brazed onto the submount at contact points 235. A glass cover plate 240 is typically brazed onto the top of the standoff at contact points 245 to seal the package.
[0020J The cost of the package illustrated in FIG. 2 is typically high, in some cases around $70. Additionally, it is usually necessary to assemble the package in a clean room environment to prevent potential handling damage and contamination. Thus, there is a need for an improved method and system for hermetically sealing packages for objects.
100211 FIGS. 3A -3D are simplified diagrams of a wafer-level hermetically sealed package according to an embodiment of the present invention. These diagrams illustrate examples according to specific embodiments. One of ordinary skill in the art would recognize various modifications, alternatives and variations. Preferably, formation of the package occurs prior to separation of the active devices into die form. Here, separation often occurs using a dicing and/or scribing and breaking process, among others. Additional details of the present method are provided throughout the present specification and more particularly below.
(0022J In the embodiment illustrated in FIG. 3A, a substrate 310 is processed according to methods to form an array of individual chips 315 on a substrate. In an embodiment according to the present invention, the substrate 310 is a CMOS semiconductor wafer, for example, Si, and the chips 315 are MEMS. An example of one way of forming these MEMS is described in U.S. Patent Application Serial Number 60/390389, commonly owned, and hereby incorporated by reference for all purposes. In the embodiment illustrated in FIG. 3A, the chips include a plurality of devices. Additionally, the CMOS wafer is processed to form integrated circuits 312, metal traces for electrical leads 314, and other CMOS structures. In an embodiment according to the present invention, the devices are micro-mirrors arranged in a mu-dimensional array, e.g., two-dimensional array. In alternative embodiments, the plurality of devices comprise a plurality of charge coupled devices (CCD), a plurality of deflection devices, a plurality of sensing devices, an integrated circuit device, any combination of these, and the like.
(0023J In the embodiment illustrated in FIG. 3B, a transparent member 320 is provided that includes a plurality of recessed regions 325 in the lower surface of the transparent member.
The transparent member has a predetermined thickness 330. In an embodiment according to the present invention, the thickness of the transparent member is 1.2 mm. Alternatively, the thickness ranges from about 0.5 mm to about 3 mm in other embodiments. Of course, the thickness will depend upon the particular applications.
f0024j Preferably, the recessed region is a volume defined within a member. The volume has a depth 322 defined by the distance from the bottom of the transparent member 324 to the top of the recessed region 339. The outer edges of the recessed region are defined by the l0 vertical edges of standoffs 335. In an embodiment according to the present invention, the volume of the recessed regions is uniform across the transparent member.
(00251 According to an embodiment of the present invention, the individual standoffs 335 comprise an annular rectangular ring with height 322 oriented in a plane parallel to the x-y plane. The lower surface of the standoff is prepared, in an embodiment according to the present invention, to mate to the substrate and form a bond sufficient to form a hermetically sealed package, as is discussed in detail below.
100261 In embodiments according to the present invention, the depth of the recessed region is a predetermined depth. In the embodiment illustrated in FIG. 3B, the depth 332 of the recessed regions is 0.5 mm. Alternatively, the depth ranges from about 0.1 mm to about I mm in other embodiments. Of course, the depth of the recessed region will depend on the particular applications. Additionaily, in embodiments according to the present invention, the area of the individual recessed regions will be a predetermined size. In the embodiment illustrated in FIG. 3B, the area of the individual recessed regions is about 14 mm x 13 mm.
Depending on the specific applications, this area may vary in size.
[0027J The recessed regions formed in the transparent member are arranged in a spatial manner to form a multi-dimensional array in the x-y plane. In some embodiments according to the present invention, the recessed regions are arranged to form a two-dimensional array in the x-y plane. In the embodiment illustrated in FIGS. 3A -3D, the depth and the x-y dimensions of the recessed regions 325 are greater than the height and the x-y dimensions of the chips 315. Accordingly, the chips fit within the recessed regions and the edges of the recessed regions are separated from the outer edges of the chips in all three dimensions.
Moreover, in the embodiment illustrated in FIGS. 3A and 3B, the center-to-center spacing of the recessed regions in both the x and ydimensions exceeds the size of the recessed regions in both the x and y dimensions, respectively, providing space for the standoff regions 335 between adjacent chips. The lateral dimension of the standoff regions have a predetennined size. In an embodiment according to the present invention the lateral dimension of the standoff region ranges between 0.5 mm and 1. 0 mm.
(0028J In an embodiment according to the present invention, the transparent member is formed from a product sold under the name of Corning EagLe200 ' display grade glass substrate manufactured by Corning Incorporated of Corning, New York. The glass substrate is characterized by high optical quality, including, but not limited to, optical power
LI
transmittance in the visible region of greater than 90%. The transmittance of light through the member can be increased by the application of anti-reflection (AR) coatings to the optical surfaces of the substrate, as disclosed below. Additionally, Corning Eagle " display grade glass is used in some embodiments according to the present invention because the coefficient of thermal expansion of the glass substrate is close to the coefficient of thermal expansion of Si.
[0029J For a material, by definition, the thermal strain at temperature T is the change in length of a member, due to a change in temperature, (F-Tj), divided by the original length I of that member. Denoting thermal strain at temperature F as e7), e(T).= (1) 1 00301 Also, by definition, the coefficient of thermal expansion for a material, denoted as aa is, a(T)=. (2) [0031J In embodiments according to the present invention in which temperature variation as a function of time is expected, it is useful to match the coefficient of thermal expansion (CTh) of the transparent cover to the CTE of the substrate. The matching of these CTEs limits the amount of warping and stress introduced in the substrate due to temperature variation.
[00321 In the embodiment illustrated in FIGS. 3A -3D, the transparent member is designed and fibricated to reduce optical absorption and thereby increase the transmission of optical energy at the wavelength range of interest. In an embodiment according to the present invention, the wavelength range of interest is the visible spectrum between 400 and 700 mu.
Additionally, in this embodiment, the top surface of the member 337 and the top surface of the recessed regions 339 are polished or finished to provide optical quality surfaces.
Moreover, AR coatings may be applied to the top surface of the transparent member and the top surface of the recessed regions. The AR coatings applied to the top surface of the transparent member will reduce the amount of light reflected off the top of the transparent member as it impinges on the package and thereby increase the amount of light that reaches the micro-mirmr array 315. Moreover, AR coatings applied to the top of the recessed regions will reduce the amount of light reflected off the transparent member as it leaves the package.
Overall system throughput will be increased by the use of these AR coatings. Quarter wave (A14) coatings of MgF2 or other suitable dielectric materials can be used to form broadband AR coatings. For example, a ?14 MgF2 coating centered at 550 mu (with an index of refraction of 1.38 at 550 nm) deposited on a Coming Eagle20001'4 display grade glass substrate, results in a power reflectance less than 2% per surface across the visible spectrum (400-700nm).
[00331 The transparent member can be worked to form the recessed regions in a variety of ways. For example, in one embodiment according to the present invention, the recessed regions can be etched into the transparent member by the use of dry or wet chemical etching, laser machining, acoustic machining, water jet machining, or the like.
[00341 In an alternative embodiment according to the present invention, the transparent member is formed by machining a first planar component and subsequently bonding a separate transparent component to the first.component as illustrated in FIG. 4. The first planar component 410 is a planar substrate that is machined or otherwise worked to formopenings at locations in which recessed regions 415 are to be positioned. Additional openings arc formed at positions 417 to form through holes used for attachment of wire bonds to the chip interconnect region, as will be described below. Unmachined areas of the first planar component wili form the standoff regions 420. A second, planar transparent component 430 is bonded to the top of the first planar component to form the completed transparent member. In a specific embodiment according to the present invention, the first planar component and the second planar transparent component are both transparent. A side vIew of the completed transparent member taken along the plane A-A of FIG. 4A is illustrated in FIG. 4B. As illustrated in FIG. 4B, the standoff regions 420 and the top transparent component 430 are illustrated.
[0035J One of the benefits provided by this alternative fabrication process is that the optical properties of the two components are not always similar. In fact, for some applications, the optical properties of the first component illustrated in FIGS. 4A and 4B do not impact system performance. For example, depending on the optical path through the package, light may never impinge on the first component. In other embodiments according to the present invention, it is desirable to absorb any light that does impinge on the lower component.
10036) In an embodiment according to the present invention, the optical properties of the transparent member are predetermined. In a specific embodiment, the transmittance and absorption coefficient of the transparent member are uniform as a function of position in the x-y plane.
[0037) In an embodiment according to the present invention, the bonding of the two transparent components is accomplished by low temperature glass fit bonding or other methods known to those of skill in the art. Additionally, AR coatings are applied to the top and bottom of the second transparent component prior to bonding to increase optical throughput. As discussed above, in this embodiment according to the present invention, the optical quality of the second transparent member will control the optical quality of light passing through the top of the recessed regions, enabling the use of polishing and coating methods not applicable to embodiments in which the transparent member is formed from a single substrate.
10038) In an embodiment according to the present invention, kennetically sealed die-level packages are formed by coupling the transparent member to the substrate. FIG. 3C is a simplified diagram of the transparent member and the substrate at the time of hennetic sealing. The transparent member is aligned in a manner to position the standoff regions 340 and 342 above the street regions 344 and 346. The individual chips 350 are located below and in communication with an associated recessed region 352 and hermetically sealed by the transparent cover 354 at contact points 356 located at the base of the standoff regions 342.
Through holes 354 provide access to bond pads 358 located on the CMOS wafer.
(0039) Hermetic sealing of the transparent member to the substrate is performed according to several methods well known to those skilled in the alt For example, in an embodiment according to the present invention, hermetic sealing is performed by plasma activated covalent wafer bonding (PACWB). PACWB is performed at room temperature after the substrate and transparent member have been cleaned, for example, in SCI (NH3:H202:H20, 1:4:20) at 60 C, rinsed in dc-ionized (DI) water, dipped in 2% HF for 20 seconds, rinsed in DI water and dried with N2 or air. The substrate and transparent member are then exposed, for example, to an oxygen plasma in a reactive ion etcher at a chamber pressure of about 35 mlorr. In an alternative embodiment according to the present invention, the substrate and transparent member are exposed to an argon plasma. After plasma treatment, the surface of the silicon oxide is hydrophilic, promoting bonding. The substrate and the transparent member are brought into contact at room temperature in a preselected ambient environment.
In alternative embodiments according to the present invention, other bonding techniques are used, for example, eutectjc low temperature bonding and anodic bonding.
(0040) In an embodiment according to the present invention, the hermetic sealing process illustrated in FIG. 3C is performed in an environment comprising inert gases. Examples of inert gases are N2 and Ar, among others. The benefits provided by hermetic sealing in an inert environment include, but are not limited to dampening of oscillations present in the devices and the prevention of electrical arcing. For example, if the devices are micro-mirrors arranged in an array, oscillations present during operation and motion of the micro-mirrors arc damped and attenuated by the presence of the inert gas. Additionally, the possibility of electrical arcing between the elements of the micro-mirror array and/or the drive electronics is reduced by the presence of the inert gas.
(0041) FIG. 5A is a top-view of the device illustrated in FIG. 3C at the time of hermetic sealing. The standoff regions 510 running in the y-direction are located above the parallel street regions 512 and the standoff regions 515 running in the x-direction are located above the parallel street regions 517. Bond pads 520 are located at the right and left sides of the active devices 522. As illustrated in FIG. 3C, through holes 348 in the transparent member provide access to the bond pads.
100421 In an embodiment according to the present invention, the hermetic sealing process is performed by bonding a single transparent member to a single substrate. In this embodiment, the size of the single transparent member is selected to correspond to the size of the substrate.
For example, a transparent member approximately 30 cm in width and length is bonded to a substrate 30 cm in diameter. Alternatively, the transparent member may be rectangular and larger in size than the substrate. man alternative embodiment according to the present invention, the size of the transparent substrate is only a fraction of the substrate size. In this alternative embodiment, before hermetic sealing, multiple transparent members are arranged to align with matched areas on the substrate surface. The multiple transparent members are subsequently bonded to the substrate. For example, FIG. SB illustrates a simplified diagram of four transparent members 552, 554, 556, and 558 arranged in a two-dimensional array above an array of chips 560 located on the substrate. In the alternative embodiment illustrated in FIG. SB, the transparent members are manufactured so that adjacent transparent members abut each other at planes 570 and 572. However, this is not necessary. Additional alternative embodiments according to the present invention may align the transparent members differently.
100431 FIG. 3D illustrates, according to an embodiment of the present invention, the separation of individual dies after hermetic sealing is completed. in the embodiment illustrated in FIG. 3D, the individual dies 360 are separated along lines running in the y-direction located between adjacent bond pads. In the x-direction, the dies are separated to align the plane of separation with the through holes 362 located in the transparent member outside of the recessed region 364. For comparison, the lines in the y-direction and x-direction are illustrated in FIG. 5A as lines 530 and 535, respectively.
(0044J In a specific embodiment according to the present invention, the individual dies are separated by cutting the substrate into dies using a diamond saw. In an alternative embodiment, the dies are separated by scribing the substrate using a diamond scribe. In an embodiment of the invention in which the substrate is a silicon wafer, the die separation is performed by sawing the silicon substrate with a rotating circular abrasive saw blade.
100451 FIG. 6 is a top-view of a single die according to an embodiment of the present invention. The lateral dimensions of the chip and recessed region arc predetermined sizes. In the embodiment illustrated in FIG. 6, the lateral dimensions of the chip 610 is about 17mm by 13 mm. The center to center spacing of the chip is about 21 mm in the x- direction and 17 mm in the y-direction. The chip in this specific embodiment comprises a 1024 x 768 array of micro-mirrors 615. The edges of the micro-mirrors are separated from the standoff regions 620 in the x and y directions by a distance of 0.5 mm. The standoff regions are 0.5 mm in width. Through holes 625 and 627 to the left and right of the standoff regions, respectively, provide access to bond pads 630 100 pm in size and set on a 150 pin pitch. Alternatively, the center to center spacing of the chip 610 is 16 mm x12 mm, resulting in a separation between the chip and the standoff regions of 0.25 nun. Of course, these dimensions will depend upon the particular applications.
(00461 In an embodiment according to the present invention, the surface roughness of the standoff regions that come in contact with the substrate is reduced to a predetermined level.
An Atomic Force Microscopy (AFM) is typically used to characterize the surface roughness of the lower surface of the standoff region. For example, a Digital Instruments EnviroScopetm' from Veeco Instruments, Inc. can be used.
10047) For example, in a specific embodiment according to the present invention, the root mean square surface roughness of the lower surface of the standoff regions is less than or equal to 2 A for a 2 pm by 2 pin area. In alternative embodiments according to the present invention, the surface roughness is about 3 A RMS over a 2 pm by 2 pm area.
(0048) FIG. 7 is a simplified diagram of a die level package useful for making electrical connection to a hermetically sealed package and mounting the package according to an embodiment of the present invention.
(0049) FIG. 7 illustrates an embodiment according to the present invention in which the hermetically sealed package is mounted on a lead frame structure, such as a ball grid array.
The separated CMOS die, chip, and hennetically sealed package previously described are illustrated as 705. In an embodiment according to the present invention, at least one interconnect region is associated with each chip on the substrate. In the embodiment illustrated in FIG. 7, the interconnect region or bonding pads 710 are located, for example, on or near the top surface of the wafer. In an embodiment according to the present invention, the interconnect pads are electrically connected to the plurality of devices to actuate the mechanical devices according to a MEMS algorithm. Thus, electrical signals presented at the interconnect region 710 result in mechanical motion of the devices 715. As disclosed previously, in a specific embodiment according to the present invention, the electrical signals presented at the interconnect region 710 deflect some or all of the micro-mirrors present in the micro-mirror array to preferentially reflect light passing through the transparent member 717 and incident on the micro-mirror array.
[0050) In order to electrically connect the interconnect region (and thus the devices) to external drivers, wire bonds 720 are connected from the interconnect pads 710(0 electrical connections located on the lead frame structure 725. In an embodiment according to the present invention, the wire bonds are made using Au wires about 25 pm in diameter, which are capable of canying in excess of 500 mA of current. In the embodiment according to the present invention illustrated in FIG. 7, the wire bonds are encapsulated in encapsulant 730.
The use of encapsulants, for example, plastic, to protect electrical components from environmental damage is well known to those skilled in the art. The lead frame, in some embodiments, is brazed onto a heat spreader 742 to reduce the thermal load on the hermetically sealed package.
(0051J In FIG. 7, the encapsulant is applied to encapsulate at least a portion of the lead frame, the wire bonds, the intenonnect regions, and the sides of the transparent member adjacent the through holes, while maintaining a surface region 735 of the transparent member Located above the recessed region free from encapsulant. Thus, the optical properties of the surface region 735 are unaffected by the application of the encapsulant. In the embodiment illustrated in FIG. 7, the total thickness 740 of the die level package is 1.27 mm. Thus, the package illustrated in FIG. 7 combines both a hermetically sealed package useflul for optical MEMS and a non-hermetically sealed plastic encapsulated package.
(00521 FIG. 8 illustrates the operation of a reflective system employing a specific embodiment of the present invention. In embodiments according to the present invention, it is desirable to spatially filter light incident on and reflected from the package. In the embodiment illustrated in FIG. 8, a beam of light from a light source 810 is incident on the top surface of the transparent member 815. A portion of the light 830 passing through the transparent member is incident on the surface of the plurality of devices, in this embodiment, a micro-mirror array 820. Another portion of the light 835 from the lamp 810 is blocked or filtered by filter mask 825 located at the periphery of the transparent member. Light blocked by the left, top and bottom sides of filter mask 825 is not able to reach the micro-mirror array.
In addition, light reflected off portions of the chip other than the micro-mirror array is blocked by the right side of the filter mask. Thus, by the use of filter mask 825, the reflected light passing to detector 840 is limited to a selected portion of the original beam that is incident on the package.
(00531 In the embodiment illustrated in FIG. 8, the filter mask is located on the upper surface of the transparent member, however, this is not required. In alternative embodiments, the filter mask is located on the lower surface or sides of the transparent member. In an additional embodiment according to the present invention, the use of non-transparent materials in the fabrication of the transparent member can complement the filter mask. In an embodiment according to the present invention, the filter mask comprises a layer of chrome.
In alternative embodiments, the filter mask is made from other reflective or absorptive materials.
j0054J In the embodiment illustrated in FIG. 8, the filter mask forms an aperture region that blocks light from impinging on or reflecting from portions of the die other than the micro-mirror array. In alternative embodiments, the filter mask is only used to block light on the incident (left) side and not on the exit (right) side of FIG 8.
100551 While the above is a complete description of specific embodiments of the invention, the above description should not be taken as limiting the scope of the invention as defined by the claims.
Further exemplary aspects of the invention are disclosed in the following numbered paragraphs by
way of example:
I. A sealed structure for micro-electromechanical devices, wherein a plurality of chips including a plurality of devices are provided in an array on a substrate with space regions therebetween and wherein a sealing member of a thickness and having a corresponding array of recessed regions within the thickness and bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose each chip within a corresponding recessed region; wherein said sealing member is provided with a filter portion configured to filter light incident on said sealing member.
2. A sealed structure according to clause I wherein said filter portion comprises a spatial filter.
3. A sealed structure according to clause I or 2 wherein the filter portion is disposed on a surface of the sealing member and is adapted to block a portion of the light incident on the sealing member.
4. A sealed structure according to any preceding clause wherein the filter portion is arranged in a further array.
5. A sealed structure according to clause 4 wherein the fitter portion array is aligned with the device array.
6. A scaled structure according to any preceding clause wherein the fitter portion comprises a layer of light absorbing material.
7. A sealed structure according to clause 6 wherein the light absorbing material comprises chrome.
8. A sealed structure according to clause 6 or 7 wherein the light absorbing material is adapted to absorb both light incident on the sealing member and light passing through the sealing member and then reflected from the substrate.
9. A sealed structure according to any of clauses I to 5, wherein the filter portion comprises a layer of reflective material.
10. A sealed structure according to clause 9 wherein the reflective material comprises chrome.
11. A sealed structure according to any preceding clause wherein the filter portion is disposed on a surface of each of the plurality of recessed regions.
12. A sealed structure according toy preceding clause wherein the filter portion is disposed on a surface of the sealing member opposing a face of the standoff region.
13. A sealed structure according to any preceding clause wherein the filter portion is disposed on an incident light surface of the sealing member.
14. A sealed structure according to any preceding clause wherein the scaling member comprises a first transparent member overlying a standoff layer, the standoff layer including at least a portion of the standoff region.
IS. A sealed structure according to any preceding clause wherein the standoff layer comprises a second transparent member.
16. A sealed structure according to any preceding clause wherein each of the plurality of chips is hermetically sealed within one of the plurality of recessed regions.
17. A sealed structure according to any preceding clause wherein each of the plurality of recessed regions comprises an inert environment.
18. A sealed structure according to clause 17 wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.
19. A sealed structure according to any preceding clause wherein the substrate comprises a silicon substrate.
20. A sealed structure according to any preceding clause wherein each of the plurality of recessed regions is rectangular in shape.
21. A sealed structure according to any preceding clause wherein the filter portion comprises a rectangular window spatially overlapping with at least a portion of the standoff region.
22. A sealed structure according to any preceding clause wherein the plurality of devices comprise a plurality of micro-mirrors.
23. A sealed structure according to any of clauses I to 22 wherein at least a portion of an incident light surface of the sealing member and at least a portion of a surface of' each of the plurality of recessed regions are coated with an antireflective material.
24. A scaled structure according to any of clauses I to 22 wherein the scaling member comprises a first side and a second side, the first side being parallel to the second side, wherein at least a portion of the first side and at least a portion of the second side are coated with an antireflective material.
25. A sealed structure according to clause 23 or 24 wherein the antireflective material comprises MgF2.
26. A method of sealing devices wherein a plurality of chips including devices arc provided in an array on a substrate with space regions therebetween and wherein a sealing member of a thickness and having a corresponding array of recessed regions within the thickness and bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose each chip within a corresponding recessed region; wherein said sealing member is provided with a filter portion configured to filter light incident on said sealing member.
27. A method according to clause 26 wherein said filter portion comprises a spatial filter.
28. A method according to clause 26 or 27 wherein the filter portion is coupled to the sealing member and is adapted toblock a portion of the light incident on the sealing member.
29. A method according to any of clauses 26 to 28 wherein the filter portion is arranged in a further array.
30. A method according to clause 29 wherein the filter portion array is aligned with the device array.
31. A method according to any of clauses 26 to 30 wherein the filter portion comprises a layer of light absorbing material.
32. A method according to clause 31 wherein the light absorbing material comprises chrome.
33. A method according to clause 31, or 32 wherein the light absorbing material is adapted to absorb both light incident on the surface of the filter portion and light passing through the filter portion and then reflected from the substrate.
34. A method according to any of clauses 26 to 33 wherein the filter portion is disposed on a surface of the seating member opposing a face of the standoff region.
35. A method according to any of clauses 26 to 34 wherein the filter portion is disposed on a surface of each of the plurality of recessed regions.
36. A method according to any of clauses 26 to 35 wherein the filter portion is disposed on a surface of the scaling member opposing a face of the standoff region.
37. A method according to any of clauses 26 to 36 further comprising forming each of the recessed regions by at least one of dry etching, wet etching, laser machining, acoustic machining, or casting.
38. A method according to any of clauses 26 to 37 wherein the seaLing member comprises a first transparent member overlying a standoff layer including the standoff region.
39. A method according to clause 38 wherein the standoff layer comprises a second transparent member.
40. A method according to any of clauses 26 to 39 wherein the bonding process is selected from at Least one of a plasma activated bonding process, a eutectic bonding process, a glue layer or adhesive bonding process, a welding process, an anodic bonding process, or a fusion bonding process.
41. A method according to any of clauses 26 to 40 wherein the substrate comprises a silicon sUbstrate.
42. A method according to any of clauses 26 to 41 wherein the sealing member comprises a first side and a second side, the first side being parallel to the second side, wherein at least a portion of the first side and at Least a portion of the second side are coated with an antireflective material.
43. A method according to clause 42 wherein the antireflective material comprises MgF2.
44. A sealed structure for micro-electromechanical devices, the sealed structure comprising: a substrate, the substrate including a plurality of chips, each of the chips including a plurality of devices. arranged in a first array; a sealing member having a plurality of recessed regions bordered by standoff regions and arranged in a second array, said second array being arranged in a complementary manner to the first; wherein the sealing member is aligned such that each recessed region is aligned with a respective chip; and each chip is sealed within the respective recessed region by bonding the standoff region to street regions between the chips; wherein said sealing member is provided with a filter portion configured to filter light incident on said sealing member.
45. A method for sealing micro-electromechanical devices in a sealed structure, the method comprising: providing a substrate, the substrate including a plurality of individual chips, each of the chips including a plurality of devices, arranged in a first array; providing a sealing member having a plurality of recessed regions bordered by standoff regions and arranged in a second array, said second array being arranged in a complementary manner to the first; aligning the sealing member such that each recessed region aligns with a respective chip: and sealing the devices of each chip within the respective recessed region by bonding the standoff region to street regions between the chips; wherein said sealing member is provided with a filter portion configured to fiLter light incident on said scaling member.
46. A system of hermetically sealed devices comprising: a plurality of chips including devices provided in an array on a substrate with space regions therebetween; and a transparent member of a thickness and having a corresponding array of recessed regions within the thickness and bordered by a standoff region aligned with the substrate; wherein the stand3ff region is bonded to the space regions to enclose the chip within a corresponding recessed region; and wherein each chip comprises an interconnect region arranged for location external to the corresponding recessed region when aligned.
47. A system according to clause 46 wherein the space regions comprise first street regions and second street regions, the second street regions intersecting the first street regions, wherein: each of the first street regions has a first width ranging from about 0.5 mm to 1.0 mm in dimension and each of the second street regions has a second width ranging from about 0.5 mm to 1.0 mm in dimension.
48. A system according to clause 46 or 47 wherein the transparent member has an optical power transmittance of greater than about 99%.
49. A system according to any of clauses 46 to 48 wherein the transparent member is characterized by a coefficient of thermal expansion aT, the coefficient of thermal expansion is about the same as a coefficient of thermal expansion as of the substrate.
50. A system according to any of clauses 46 to 49 wherein the transparent member comprises an antireflective coating disposed overlying surface regions of each of the plurality of recessed regions.
51. A system according to any of clauses 46 to 50 wherein the transparent member comprises a first transparent member overlying a second transparent member including the standoff region.
52. A system according to any of clauses 46 to 51 wherein the standoff region comprises a second transparent member.
53. A system according to any of clauses 46 to 52 wherein the trinsparent member is characterized by a thickness ranging from about 0.1 mm to 1.2 mm.
54. A system according to any of clauses 46 to 53 wherein each of the plurality of chips is maintained within an inert environment within the one of the plurality of recessed regions.
55. A system according to clause 54 wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.
56. A system according to any of clauses 46 to 55 wherein the substrate comprises a silicon bearing material.
57. A system according to any of clauses 46 to 56 wherein the interconnect region is exposed through a through hole region on the transparent member.
58. A system according to any of clauses 46 to 57 wherein the interconnect region comprises a plurality of bonding pads.
59. A system according to any of clauses 46 to 58 wherein the substrate is a silicon wafer.
60. A system according to any of clauses 46 to 59 wherein each of the plurality of recessed regions comprises a first surface region opposing a second surface region, the first surface region having a root mean square surface roughness of less than or equal to 2 A for a 2 pm by 2 pm area.
61. A system according to any of clauses 46 to 60 wherein each of the plurality of recessed regions is annular in shape.
62. A system according to any of clauses 46 to 61 wherein each of the plurality of recess regions has a depth of about 0.5 mm and less.
63. A system according to any of clauses 46 to 62 wherein the transparent member comprises a first side and a second side, the first side being parallel to the second side, the first side and the second side being coated with an antireflective material. 64. A method according to clause 63 wherein the antireflective material
comprises MgF2.
65:. A system according to any of clauses 46 to 63 wherein each of the plurality of recessed regions has a peripheral region that forms an aperture region overlying a portion of one of the plurality of chips.
66. A M.EMS package comprising: a plurality of MEMS chips, each chip including a plurality of devices provided in an array on a substrate with space regions therebetween; and a transparent member of a thickness and having a corresponding array of recessed regions within the thickness and bordered by a standoff region aligned with the substrate; wherein the standoff region is bonded to the space regions to enclose the chip within a corresponding recessed region; and wherein each chip comprises an interconnect region arranged for location external to the corresponding recessed region when alignecL 67. A MEMS package according to clause 66 wherein an interface between the standoff region and the substrate comprises a hermetic seal.
68. A MEMS package according to clause 66 cr67 wherein each of the plurality of MEMS chips are hermetically sealed within one of the plurality of recessed regions.
69. A MEMS package according to any of clauses 66 to 68 wherein the plurality of devices comprise at least one of charge coupled devices, sensing devices, or integrated circuit devices.
70. A MEMS package according to any of clauses 66 to 69 wherein the plurality of devices comprise deflection devices.
71. A MEMS package according to clause 70 wherein the deflection devices comprise miCro-mirror structures.
72. A MEMS package according to any of clauses 66 to 71 wherein the interconnect region comprises a plurality of bond pads.
73. A MEMS package according to clause 72 wherein the plurality of bond pads comprise a first two sets of bond pads located on opposite sides of each of the plurality of MEMS chips.
74. A MEMS package according to clause 73 the plurality of bond pads comprise a further two sets of bond pads located on opposite sides of each of the plurality of MEMS chips, the further two sets of bond pads being oriented 90 with respect to the first two sets of bond pads.
75. A MEMS package according to any of clauses 66 to 74 wherein the space regions comprise first street regions and second street regions, wherein the plurality of bond pads are located in at least one of the plurality of first street regions or the plurality of second street regions.
76. A MEMS package according to any of clauses 66 to 75 wherein the transparent member comprises an antireflective coating disposed overlying surface regions of each of the plurality of recessed regions.
77. A MEMS package according to any of clauses 66 to 76 wherein the transparent member comprises a first transparent member overlying a second transparent member including the standoff region.
78. A MEMS package according to any of clauses 66 toll wherein the transparent member is characterized by a thickness ranging from about 0.1 mm to 1.2 mm.
79. A MEMS package according to any of clauses 66 to 78 wherein each of the plurality of MEMS chips is maintained within an inert environment within one of the plurality of recessed regions.
80. A MEMS package according to clause 79 wherein the inert environment is selected from nitrogen, argon, or a miAture of nitrogen and argon.
81. A MEMS package according to any of clauses 66 to 80 wherein each of the plurality of recessed regions comprises a first surface region opposing a second surface region, the first surface region having a root mean square surface roughness of less than or equal to 2 A for a 2 j.tm by2marea.
82. A MEMS package according to any of clauses 66 to 81 wherein each of the plurality of recess regions has a depth of about 0.5 mm and less.
83. A MEMS package according to any of clauses 66 to 83 wherein the transparent member comprises a first side and a second side, the first side being parallel to the second side, the first side and the second side being coated with an antireflective material.
84. A MEMS package according to any of clauses 66 to 84 wherein each of the plurality of recessed regions has a peripheral region that forms an aperture region overlying a portion of one of the plurality of MEMS chip.
85. A system for hermetically sealing devices, the system comprising: a substrate, the substrate including a plurality of chips, each of the chips including a plurality of devices, arranged in a first array; a transparent member having a plurality of recessed regions bordered by standoff regions and arranged in a second array, said second array being arranged in a complementary manner to the first; wherein the transparent member is aligned such that each recessed region is aligned with a respective chip; and each chip is sealed within the respective recessed region by bonding the standoff region to street regions between the chips; wherein each chip comprises an interconnect region arranged for location externaL to the corresponding recessed region when aligned.
86. A MEMS package comprising: a substrate, the substrate including a plurality of chips, each of the chips including a plurality of devices, arranged in a first array; a transparent member having a plurality of recessed regions bordered by standoff regions and arranged in a second array, said second array being arranged in a complementary manner to the first; wherein the transparent member is aligned such that each recessed region is aligned with a respective chip; and each chip is sealed within the respective recessed region by bonding the standoff region to Street regions between the chips; wherein each chip comprises an interconnect region arranged for location external to the corresponding recessed region when aligned.
87. A method for hermetically sealing devices wherein a plurality of chips including devices are provided in an array on a substrate with space regions therebetween and wherein a transparent member of a thickness and having a corresponding array of recessed regions within the thickness and bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose and hermetically seal each chip within a corresponding recessed region; wherein each chip comprises an interconnect region arranged for location external to the corresponding recessed region when aligned.
88. A system for wafer-level packaging of a plurality of MEMS devices wherein a plurality of chips including a plurality of MEMS devices are provided in an array on a substrate with space regions therebetween and wherein a transparent member of a thickness and having a corresponding array of recessed regions within the thickness and bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose and individually seal each of the plurality of chips within one of the recessed regions.
89. A system according to clause 88 wherein the standoff layer comprises a second transparent member.
90. A system according to clause 88 or 89 wherein the thickness of the transparent member ranges from about 0.5 mm to 3.0 mm.
91. A system according to clause 90 wherein the thickness of the transparent member ranges from about 2.0 mm to 3.0 mm.
92. A system according to any preceding clause wherein the depth of each of the plurality of recessed regions ranges from about 0.1 mm to 1.0 mm.
93. A system according to clause 92 wherein the depth of each of the plurality of recessed regions ranges from about 0.5 mm to 1.0 mm.
94. A system according to any preceding clause wherein each of the plurality of individual chips is maintained within an inert environment within the one of the plurality of recessed regions.
95. A system according to clause 94 wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.
96. A system according to any preceding clause wherein the substrate comprises a silicon bearing material.
97. A system according to any preceding clause wherein the transparent member comprises a filter mask disposed on a surface of the transparent member.
98. A system according to clause 97 wherein the surface of the transparent member comprises an upper surface of the transparent member.
99. A system according to clause 97 wherein the filter mask forms an aperture region around a periphery of each of the plurality of individual chips.
100. A system according to any preceding clause wherein the plurality of MEMS devices comprise deflection devices.
101. A system according to clause 100 wherein the deflection devices comprise micro-mirror structures.
102. A system for wafer-level packaging of a plurality of MEMS devices, the system comprising: a substrate, the substrate including a plurality of MEMS chips, each of the chips including a plurality of MEMS devices, arranged in a first array; a transparent member having a plurality of recessed regions bordered by standoff regions and arranged in a second array, said second array being arranged in a complementary manner to the first; wherein the transparent member is aligned such that each recessed region is aligned with a respective chip; and each cf the plurality of MEMS chips is enclosed and individually seated within one of the recessed regions by bonding the standoff region to street regions between the chips to form a sealed interface.

Claims (44)

  1. Claims 1. A system for wafer-level packaging of a plurality of MEMS
    devices wherein a substrate comprising a chip having a plurality of MEMS devices and bordered by space regions is provided and wherein a transparent member of a thickness and having a recessed region within the thickness and bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose and individually seal the chip within the recessed region.
  2. 2. A system according to claim 1 wherein a plurality of said chips including a plurality of MEMS devices are provided in an array on the substrate with said space regions therebetween and wherein said recess of said transparent member is bonded to the substrate to enclose and individually seal one of said chips within the recessed region.
  3. 3. A system according to claim I wherein said transparent member comprises a plurality of said recessed regions arranged in an array each recessed region being bordered by a standoff region, wherein one of said recessed regions is aligned with the substrate and the corresponding standoff region bonded to the space regions to enclose and individually seal said chip within said one of the recessed regions.
  4. 4. A system according to claim I wherein: a plurality of said chips including a plurality of MEMS devices are provided in an array on the substrate with said space regions therebetween, and said transparent member comprises a plurality of said recessed regions arranged in an array each recessed region being bordered by a standoff region; and wherein said transparent member is aligned with the substrate, and the standoff regions bonded to the space regions, to enclose and individually seal each of the plurality of chips within one of the recessed regions.
  5. 5. A system according to any preceding claim wherein the standoff layer comprises a second transparent member.
  6. 6. A system according to any preceding claim wherein the thickness of the transparent member ranges from about 0.5 mm to 3.0 mm.
  7. 7. A system according to claim 6 wherein the thickness of the transparent member ranges from about 2.0 mm to 3.0 mm.
  8. 8. A system according to any preceding claim wherein the depth of each of the plurality of recessed regions ranges from about 0.1 mm to 1.0 mm.
  9. 9. A system according to claim 8 wherein the depth of each of the plurality of recessed regions ranges from about 0.5 mm to 1.0 mm.
  10. 10. A system according to any preceding claim wherein each of the plurality of individual chips is maintained within an inert environment within the one of the plurality of recessed regions.
  11. Ii. A system according to claim 10 wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.
  12. 12. A system according to any preceding claim wherein the substrate comprises a silicon bearing material.
  13. 13. A system according to any preceding claim wherein the transparent member comprises a filter mask disposed on a surface of the transparent member.
  14. 14. A system according to claim 13 wherein the surface of the transparent member comprises an upper surface of the transparent member.
  15. 15. A system according to claim 13 wherein the filter mask forms an aperture region around a periphery of each of the plurality of individual chips.
  16. 16. A system according to any preceding claim wherein the plurality of MEMS devices comprise deflection devices.
  17. 17. A system according to claim 16 wherein the deflection devices comprise micro-mirror structures.
  18. 18. A system according to any preceding claim wherein the substrate comprises CMOS circuitry.
  19. 19. A system according to any preceding claim wherein the sealed interface comprises a covalent bond interface or a eutectic bond interface.
  20. 20. A method for wafer-level packaging of a plurality of MEMS devices wherein a substrate comprising a chip having a plurality of MEMS devices and bordered by space regions is provided and wherein a transparent member of a thickness and having a recessed region within the thickness and bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose and individually seal the chip within the recessed region.
  21. 21. A method according to claim 20 wherein a plurality of said chips including a plurality of MEMS devices are provided in an array on the substrate with said space regions therebetween and wherein said recess of said transparent member is bonded to the substrate to enclose and individually seal one of said chips within the recessed region.
  22. 22. A method according to claim 20 wherein said transparent member comprises a plurality of said recessed regions arranged in an array each recessed region being bordered by a standoff region, wherein one of said recessed regions is aligned with the substrate and the corresponding standoff region bonded to the space regions to enclose and individually seal said chip Within said one of the recessed regions.
  23. 23. A method according to claim 20 wherein: a plurality of said chips including a plurality of MEMS devices are provided in an array on the substrate with said space regions therebetween, and said transparent member comprises a plurality of said recessed regions arranged in an array each recessed region being bordered by a standoff region; and wherein said transparent member is aligned with the substrate, and the standoff regions bonded to the space regions, to enclose and individually seal each of the plurality of chips within one of the recessed regions.
  24. 24. A method according to any of claims 20 to 23 wherein the standoff layer comprises a second transparent member.
  25. 25. A method according to any of claims 20 to 24 wherein the thickness of the transparent member ranges from about 0.5 mm to 3.0 mm.
  26. 26. A method according to claim 25 wherein the thickness of the transparent member ranges from about 2.0 mm to 3.0 mm.
  27. 27. A method according to any of claims 20 to 26 wherein the depth of each of the plurality of recessed regions ranges from about 0.1 mm to 1.0 mm.
  28. 28. A method according to claim 27 wherein the depth of each of the plurality of recessed regions ranges from about 0.5 nun to 1.0 mm.
  29. 29. A method according to any of claims 20 to 28 wherein each of the plurality of individual chips is maintained within an inert environment within the one of the plurality of recessed regions.
  30. 30. A method according to claim 29 wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.
  31. 31. A method according to any of claims 20 to 30 wherein the substrate comprises a silicon bearing material.
  32. 32. A method according to any of claims 20 to 31 wherein the transparent member comprises a filter mask disposed on a surface of the transparent member.
  33. 33. A method according to claim 32 wherein the surface of the transparent member comprises an upper surface of the transparent member.
  34. 34. A method according to claim 32 wherein the filter mask forms an aperture region around a periphery of each of the plurality of individual chips.
  35. 35. A method according to any of claims 20 to 34 wherein the plurality of MEMS devices comprise deflection devices.
  36. 36. A method according to claim 35 wherein the deflection devices comprise micro-mirror structures.
  37. 37. A method according to any of claims 20 to 36 wherein the substrate comprises CMOS circuitry.
  38. 38. A method according to any of claims 20 to 37 wherein the sealed interface comprises a covalent bond interface or a eutectic bond interface.
  39. 39. A system for wafer-level packaging of a plurality of MEMS devices wherein a substrate comprising a chip baying a plurality of MEMS devices and bordered by space regions is provided and wherein a cover member of a thickness and having a recessed region within the thickness and bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose and individually seal the chip within the recessed region.
  40. 40. A system for wafer-level packaging of a plurality of MEMS devices, the system comprising: a substrate, the substrate including a plurality of MEMS chips, each of the chips including a plurality of MEMS devices, arranged in a first array; a cover member having a plurality of recessed regions bordered by standoff regions and arranged in a second array, said second array being arranged in a complementary manner to the first; wherein the cover member is aligned such that each recessed region is aligned with a respective chip; and each of the plurality of MEMS chips is enclosed and individually sealed within one of the recessed regions by bonding the standoff region to street regions between the chips to form a sealed interface,
  41. 41. A system as claimed in claim 39 or 40 wherein said cover member comprises silicon bearing material.
  42. 42. A method for wafer-level packaging of a plurality of MEMS devices wherein a substrate comprising a chip having a plurality of MEMS devices and bordered by space regions is provided and wherein a cover member of a thickness and having a recessed region within the thickness and bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose and individually seal the chip within the recessed region.
  43. 43. A method for wafer-level packaging of a plurality of MEMS devices, the method comprising: providing a substrate including a plurality of MEMS chips, each of the chips including a plurality of MEMS devices, arranged in a first array; providing a cover member having a plurality of recessed regions bordered by standoff regions and arranged in a second array, said second array being arranged in a complementary manner to the first; aligning the cover member with the substrate such that each recessed region is aligned with a respective chip; and enclosing and individually sealing each of the plurality of MEMS chips within one of the recessed regions by bonding the standoff region to street regions between the chips to form a sealed interface.
  44. 44. A method as claimed in claim 42 or 43 wherein said cover member comprises silicon bearing material.
GB0801228A 2003-10-24 2004-10-22 Method and system for hermetically sealing packages for optics Expired - Fee Related GB2443573B (en)

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US10/693,323 US7303645B2 (en) 2003-10-24 2003-10-24 Method and system for hermetically sealing packages for optics
GB0801228A GB2443573B (en) 2003-10-24 2004-10-22 Method and system for hermetically sealing packages for optics
GB0703881A GB2439403B (en) 2003-10-24 2004-10-22 Method and system for hermetically sealing packages for optics

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001029890A2 (en) * 1999-10-19 2001-04-26 Imego Ab Method relating to anodic bonding

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001029890A2 (en) * 1999-10-19 2001-04-26 Imego Ab Method relating to anodic bonding

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GB2443573B (en) 2008-08-27

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