WO2001024256A1 - Method for the tri-dimensional integration of micro-electronic systems - Google Patents

Method for the tri-dimensional integration of micro-electronic systems Download PDF

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Publication number
WO2001024256A1
WO2001024256A1 PCT/DE2000/003309 DE0003309W WO0124256A1 WO 2001024256 A1 WO2001024256 A1 WO 2001024256A1 DE 0003309 W DE0003309 W DE 0003309W WO 0124256 A1 WO0124256 A1 WO 0124256A1
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substrate
via holes
main surface
trenches
metallization
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PCT/DE2000/003309
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German (de)
French (fr)
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Andreas Kux
Herbert Palm
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Infineon Technologies Ag
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Publication of WO2001024256A1 publication Critical patent/WO2001024256A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a method for three-dimensional integration of microelectronic systems in which, for example, semiconductor substrates in the form of disks or chips are connected to one another and then filled with metal as prefabricated via holes which are intended to produce the electrical contact between the metallization levels of the disks or chips.
  • a metallization layer must then be applied and phototechnically structured in order to obtain the desired microelectronic system.
  • Such a method is known from DE 44 33 846 AI, in which individual component layers in different substrates are processed independently of one another and subsequently joined together.
  • a first, completely processed substrate with one or more metallization levels is provided on the front with via holes.
  • the via holes are opened at the point where vertical contact with the underlying component layers of a second substrate is later to be created.
  • an auxiliary substrate is applied to the front of the first substrate via an adhesive layer.
  • the first substrate is then thinned from the back until the via holes are reached, so that they are then opened on both sides of the substrate.
  • a second, also finished, substrate is then connected to the first substrate by an adhesive layer, the front of the second substrate being provided with a transparent adhesive layer.
  • the handling substrate is removed, and the existing via holes are now extended from the front of the first substrate to the metallization level of the second substrate, and via these via holes, the electrical contact between the metallization of a metallization level of the first substrate and the metallization of a metallization level of the second substrate.
  • Metallic material is then deposited on the top of the first substrate and into the via and contact holes. This material must then be structured, whereupon the vertical integration of the component layers of the first and second substrates is completed.
  • JP 63-213943 A2 discloses a method for the vertical integration of microelectronic systems, in which the processing of two component levels takes place in different substrates (top and bottom substrates).
  • the top substrate is first provided with via holes which penetrate all layers with circuit structures of this substrate.
  • the top substrate is then connected on the front to an auxiliary substrate, thinned on the back and applied to the front of the bottom substrate.
  • the auxiliary substrate is removed and the existing via holes are opened until the bottom substrate is metallized.
  • the via holes are filled and the connection to the metallization level of the top substrate is established via contact holes.
  • thinning the top substrate before joining it to the bottom substrate requires a special handling technique for the top substrate.
  • the handling technique consists in the application and later removal of an auxiliary substrate
  • connection metallization which was produced by depositing metallic material on the surface of the upper component level, is structured.
  • the lithography steps necessary for this have the following disadvantages: high demands on the coating and exposure technology due to the non-standard substrate material (stack of thinned and glued substrates) and reduction in yield in the lithography for metal structuring due to the strong topography after the completed via Technology resulting from paint thickness inhomogeneities and paint wetting problems up to paint breaks.
  • the phototechnical structuring in the systems described above has the disadvantage that these structuring must be carried out on the background of extreme topology.
  • the bumps can be so large that the depth of field of a phototechnical structuring is overwhelmed.
  • the reasons for this can be seen in the fact that slices that have been thinned are placed on top of one another and this thinning process is subject to thick fluctuations of a few ⁇ m.
  • chips are installed that can come from different regions of a disk, and the can therefore have different thicknesses, which leads to steps in the chip surface.
  • trenches between the chips have to be planarized, and this planarization is also problematic and often does not turn out to be sufficiently good.
  • the invention has for its object to provide a method for three-dimensional integration of microelectronic systems in which a phototechnical structuring of the conductor tracks after the connection of the two substrates or the wafer / chip connection is avoided.
  • the method for three-dimensional integration of microelectronic systems according to the invention comprises the following method steps:
  • Provision of a first substrate which has at least one metallization in the region of a first main surface provision of a second substrate which has first ends of via holes and a structure of graves in the region of a second main surface and second ends of the via holes in a third main surface connecting the first substrate to the second substrate, the side of the first main surface of the first substrate being joined to the side of the third main surface of the second substrate, the via holes ending in the metallization of the first main surface of the first substrate, - filling the via holes and the trenches with a conductive layer and
  • the advantages of the method according to the invention result primarily from the fact that the structures which are later filled with metal or a conductive material are produced before the chip / wafer assembly and are therefore produced on a conventional wafer material, as has been the case up to now two-dimensional integration was common.
  • the photolithography technology is thus carried out on a surface that is sufficiently flat and therefore unproblematic. After the wafer / chip assembly, which creates an uneven surface, there is no longer any need for photolithographic structuring, and there is only metal deposition with subsequent etching, which is largely independent of the planarity of the chip surface.
  • An advantageous embodiment of the method according to the invention is characterized in that the via holes and / or the trenches are produced by photolithography and etching, which are unproblematic and tried-and-tested methods for producing this structure.
  • a further advantageous embodiment of the method according to the invention is characterized in that the substrates are connected to one another by an adhesive layer, so that on the one hand a secure connection of the two substrates and on the other hand readjustment of the two substrates is possible.
  • a further advantageous embodiment of the method according to the invention is characterized in that the adhesive layer is removed before the via holes and the trenches are filled with conductive material at the via holes, and in principle it is possible that when filling the via holes the Adhesive layer is removed by thermal action. In order to ensure safe removal of the adhesive layer on the via holes, however, it is preferred that the adhesive layer on the via holes be removed.
  • the method is characterized in that a metal layer is deposited on the second main surface of the second substrate in order to fill the via holes and trenches with a conductive layer, which is an advantageous procedure both with regard to the electrical conductivity of the conductor tracks produced thereby and with regard to the production technology is.
  • a further advantageous embodiment of the process according to the invention is characterized in that the metal deposition - fertilization in a PVD (physical vapor deposition process) -, CVD (chemical deposition from the vapor phase) - or a plating process is carried out.
  • PVD physical vapor deposition process
  • CVD chemical deposition from the vapor phase
  • plating process is carried out.
  • a further advantageous embodiment of the method according to the invention is characterized in that the conductive layer or the metal layer is removed by etching back or a CMP (chemical mechanical polishing) method.
  • CMP chemical mechanical polishing
  • FIG. 1 is a schematic representation of a standard processed first substrate, in the following bottom wafer
  • Figure 2 is a schematic representation of a standard processed second substrate, in the following top wafer with via holes
  • FIG. 3 shows a schematic representation of the top wafer with a trench for a later conductor track
  • FIG. 4 shows a schematic representation of a microelectronic structure, consisting of a top wafer and a bottom wafer, which are bonded
  • FIG. 5 shows a schematic illustration of a microelectronic system, a metal layer having been applied to the top wafer
  • FIG. 6 shows a schematic illustration of a microelectronic structure, parts of the metallization of the top wafer having been removed.
  • FIG. 1 shows a schematic representation of a bottom wafer 2 with two metallizations 4, 6, so-called landing pads, on a first main surface 10 of the bottom wafer 2.
  • FIG. 2 shows a schematic illustration of a top wafer 12 with two via holes 14, 16, which extend from a second main surface 18 of the top wafer 12 to a third main surface 20 of the top wafer 12.
  • FIG. 3 shows the schematic representation of the top wafer 12 after a trench 22 has been formed between the two via holes 14, 16 and is to become a conductor track after further processing.
  • the via holes 14, 16 and the trench 22 can be produced by a photolithographic process and etching in the second substrate 12, which consists of a dielectric material.
  • the two substrates 2, 12 are bonded or bonded to one another with the aid of an adhesive layer 24.
  • the adhesive layer 24 is removed in this process stage, that is to say before the via holes 14, 16 and the trench 22 are filled with conductive material at the via holes.
  • FIG. 5 shows a schematic representation of the microelectronic system, the via holes 14, 16 and the trench 20 and the second main surface 18 of the top wafer 12 being filled or covered by a metallization layer 26.
  • the metallization layer 26 makes at the via holes 14, 16 contact with the metallizations 4, 6 of the bottom wafer 2.
  • FIG. 6 shows a schematic representation of the microelectronic system, the metal layer 6 being removed to such an extent that only the metallization remains in the via holes 14, 16 as plaques and in the trench 22 as a conductor track.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a method for the tri-dimensional integration of micro-electronic systems, comprising the following steps: preparing a first substrate (12), which has at least one metallic coating (4, 6)in the area of a first main surface (10); preparing a second substrate (12) which has the first ends of via-holes (14, 16) and a trench structure (22) in a dielectric layer in the area of a second main surface (18) and the second ends of the via-holes in a third main surface (20); connecting said first substrate (2) to said second substrate (12), the side of the first main surface (10) of the first substrate being joined to the side of the third main surface (20) of the second substrate and the via-holes (14, 16) ending at the metallic coating (4, 6) on the first main surface; filling the via-holes and the trenches with a conductive layer (26); and trimming said conductive layer (26) until the conductive material is only present in the via-holes and the trenches, the conductors present in the trenches being conductively connected to the metallic coating (4, 6) on the first main surface of the first substrate.

Description

Beschreibungdescription
Verfahren zur dreidimensionalen Integration mikroelektronischer SystemeProcess for three-dimensional integration of microelectronic systems
Die Erfindung betrifft ein Verfahren zur dreidimensionalen Integration mikroelektronischer Systeme, bei denen beispielsweise Halbleitersubstrate in Form von Scheiben oder Chips miteinander verbunden und danach als vorgefertigte Via- Löcher, die den elektrischen Kontakt zwischen den Metallisierungsebenen der Scheiben oder Chips herstellen sollen, mit Metall gefüllt werden. In der Regel muß danach eine Metallisierungslage aufgebracht und phototechnisch strukturiert werden, um das gewünschte mikroelektronische System zu erhalten.The invention relates to a method for three-dimensional integration of microelectronic systems in which, for example, semiconductor substrates in the form of disks or chips are connected to one another and then filled with metal as prefabricated via holes which are intended to produce the electrical contact between the metallization levels of the disks or chips. As a rule, a metallization layer must then be applied and phototechnically structured in order to obtain the desired microelectronic system.
Ein derartiges Verfahren ist aus der DE 44 33 846 AI bekannt, bei der einzelne Bauelementelagen in unterschiedlichen Substraten unabhängig voneinander prozessiert und nachfolgend zusammengefügt werden. Dabei wird zunächst ein erstes, fertig prozessiertes Substrat mit einer oder mehreren Metallisierungsebenen vorderseitig mit Via-Löchern versehen. Die Via- Löcher werden an der Stelle geöffnet, an der später ein vertikaler Kontakt zu den darunterliegenden Bauelementelagen eines zweiten Substrates erzeugt werden soll. Nach Prozessieren der Via-Löcher wird auf der Vorderseite des ersten Substrates über eine Haftschicht ein Hilfssubstrat aufgebracht. Anschließend wird das erste Substrat von der Rückseite her gedünnt, bis die Via-Löcher erreicht sind, so daß diese danach nach beiden Seiten des Substrates hin geöffnet sind. An- schließend wird ein zweites, ebenfalls fertig prozessiertes Substrat mit dem ersten Substrat durch eine Haftschicht verbunden, wobei die Vorderseite des zweiten Substrats mit einer transparenten Haftschicht versehen wird. Nach dem Zusammenfü- gen der beiden Substrate wird das Handlingsubstrat entfernt, und die vorhandenen Via-Löcher werden nun von der Vorderseite des ersten Substrates her bis zu der Metallisierungsebene des zweiten Substrates verlängert, und über diese Via-Löcher wird schließlich der elektrische Kontakt zwischen der Metallisierung einer Metallisierungsebene des ersten Substrates und der Metallisierung einer Metallisierungsebene des zweiten Substrates hergestellt. Anschließend wird auf der Oberseite des ersten Substrates und in die Via- und Kontaktlöcher metalli- sches Material abgeschieden. Dieses Material muß dann strukturiert werden, worauf die vertikale Integration der Bauelementelagen von erstem und zweitem Substrat abgeschlossen ist.Such a method is known from DE 44 33 846 AI, in which individual component layers in different substrates are processed independently of one another and subsequently joined together. First of all, a first, completely processed substrate with one or more metallization levels is provided on the front with via holes. The via holes are opened at the point where vertical contact with the underlying component layers of a second substrate is later to be created. After processing the via holes, an auxiliary substrate is applied to the front of the first substrate via an adhesive layer. The first substrate is then thinned from the back until the via holes are reached, so that they are then opened on both sides of the substrate. A second, also finished, substrate is then connected to the first substrate by an adhesive layer, the front of the second substrate being provided with a transparent adhesive layer. After merging Towards the two substrates, the handling substrate is removed, and the existing via holes are now extended from the front of the first substrate to the metallization level of the second substrate, and via these via holes, the electrical contact between the metallization of a metallization level of the first substrate and the metallization of a metallization level of the second substrate. Metallic material is then deposited on the top of the first substrate and into the via and contact holes. This material must then be structured, whereupon the vertical integration of the component layers of the first and second substrates is completed.
Aus der JP 63-213943 A2 ist ein Verfahren zur vertikalen In- tegration mikroelektronischer Systeme bekannt, bei dem die Prozessierung zweier Bauelementeebenen in unterschiedlichen Substraten (Top- und Bottomsubstrat) erfolgt. Bei dem Verfahren wird das Topsubstrat zunächst mit Via-Löchern versehen, die sämtliche Lagen mit Schaltungsstrukturen dieses Substra- tes durchdringen. Das Topsubstrat wird dann vorderseitig mit einem Hilfssubstrat verbunden, rückseitig gedünnt und auf die Vorderseite des Bottomsubstrates aufgebracht. Das Hilfssubstrat wird entfernt und die vorhandenen Via-Löcher werden bis zur Metallisierung des Bottomsubstrates geöffnet. Die Via- Löcher werden aufgefüllt und die Verbindung zur Metallisierungsebene des Topsubstrates wird über Kontaktlöcher hergestellt. Das Dünnen des Topsubstrates vor dem Zusammenfügen mit dem Bottomsubstrat erfordert jedoch eine spezielle Handlingtechnik für das Topsubstrat. Die Handlingtechnik besteht im Aufbringen und späteren Entfernen eines HilfssubstratesJP 63-213943 A2 discloses a method for the vertical integration of microelectronic systems, in which the processing of two component levels takes place in different substrates (top and bottom substrates). In the method, the top substrate is first provided with via holes which penetrate all layers with circuit structures of this substrate. The top substrate is then connected on the front to an auxiliary substrate, thinned on the back and applied to the front of the bottom substrate. The auxiliary substrate is removed and the existing via holes are opened until the bottom substrate is metallized. The via holes are filled and the connection to the metallization level of the top substrate is established via contact holes. However, thinning the top substrate before joining it to the bottom substrate requires a special handling technique for the top substrate. The handling technique consists in the application and later removal of an auxiliary substrate
(Handlingsubstrat) . Diese zusätzlichen Fertigungsschritte erhöhen die Herstellungskosten. Das Wiederentfernen des Hilfssubstrates nach erfolgtem Dünnen des Topsubstrates verringert zudem die Ausbeute der Bauteile, da hierbei Bauelementeschichten beschädigt werden können.(Handling substrate). These additional manufacturing steps increase manufacturing costs. The removal of the auxiliary substrate after the top substrate has been thinned is reduced also the yield of the components, since component layers can be damaged.
Bei den bekannten Verfahren ist es erforderlich, daß nach dem Zusammenfügen der Substrate zu einem Bauelementestapel die Verbindungsmetallisierung strukturiert wird, die durch Abscheidung metallischen Materials auf der Oberfläche der oberen Bauelementebene erzeugt wurde. Die hierzu notwendigen Lithographieschritte bringen die folgenden Nachteile mit sich: hohe Anforderungen an die Lack- und Belichtungstechnik wegen des nicht dem Standard entsprechenden Substratmaterials (Stapel gedünnter und geklebter Substrate) sowie Ausbeuteminderung bei der Lithographie für die Metallstrukturierung wegen der vorliegenden starken Topographie nach ausgeführter Via- Technik in Folge von Lackdickeninhomogenitäten und Lackbenet- zungsproblemen bis hin zu Lackabrissen.In the known methods, it is necessary that after the substrates have been assembled to form a component stack, the connection metallization, which was produced by depositing metallic material on the surface of the upper component level, is structured. The lithography steps necessary for this have the following disadvantages: high demands on the coating and exposure technology due to the non-standard substrate material (stack of thinned and glued substrates) and reduction in yield in the lithography for metal structuring due to the strong topography after the completed via Technology resulting from paint thickness inhomogeneities and paint wetting problems up to paint breaks.
Die Nachteile der genannten Verfahren bestehen also insbesondere in hohen Durchlaufzeiten der Substrate bei der Ferti- gung, hohen Fertigungskosten, Ausbeuteminderung oder in der notwendigen Anwendung von Sonderprozessen, die inkompatibel zur Standard-Halbleiterfertigung sind.The disadvantages of the methods mentioned are, in particular, the long throughput times of the substrates during production, high production costs, reduction in yield or the need to use special processes that are incompatible with standard semiconductor production.
Mit anderen Worten haben die phototechnischen Strukturierun- gen in den oben beschriebenen Systemen den Nachteil, daß diese Strukturierungen auf dem Untergrund extremer Topologie durchgeführt werden müssen. Die Unebenheiten können so groß sein, daß die Tiefenschärfe einer phototechnischen Strukturierung überfordert wird. Gründe hierfür sind darin zu sehen, daß Scheiben aufeinandergesetzt werden, die gedünnt wurden, und dieser Dünnungsprozeß mit dicken Schwankungen von einigen μm behaftet ist. Ferner werden Chips montiert, die aus verschiedenen Regionen einer Scheibe stammen können, und die deshalb verschiedene Dicke aufweisen können, was zu Stufen in der Chipoberfläche führt. Schließlich müssen im Falle der Chipmontage Gräben zwischen den Chips planarisiert werden, und diese Planarisierung ist ebenfalls problematisch und fällt oft nicht hinreichend gut aus.In other words, the phototechnical structuring in the systems described above has the disadvantage that these structuring must be carried out on the background of extreme topology. The bumps can be so large that the depth of field of a phototechnical structuring is overwhelmed. The reasons for this can be seen in the fact that slices that have been thinned are placed on top of one another and this thinning process is subject to thick fluctuations of a few μm. In addition, chips are installed that can come from different regions of a disk, and the can therefore have different thicknesses, which leads to steps in the chip surface. Finally, in the case of chip mounting, trenches between the chips have to be planarized, and this planarization is also problematic and often does not turn out to be sufficiently good.
Demgegenüber liegt der Erfindung die Aufgabe zugrunde, ein Verfahren zur dreidimensionalen Integration mikroelektronischer Systeme bereitzustellen, bei dem eine phototechnische Strukturierung der Leiterbahnen nach der Verbindung der beiden Substrate bzw. der Scheiben- /Chip-Verbindung vermieden wird.In contrast, the invention has for its object to provide a method for three-dimensional integration of microelectronic systems in which a phototechnical structuring of the conductor tracks after the connection of the two substrates or the wafer / chip connection is avoided.
Zur Lösung dieser Aufgabe umfaßt das Verfahren zur dreidimen- sionalen Integration mikroelektronischer System gemäß der Erfindung die folgenden Verfahrensschritte :To achieve this object, the method for three-dimensional integration of microelectronic systems according to the invention comprises the following method steps:
Bereitstellung eines ersten Substrates, das im Bereich einer ersten Hauptfläche zumindest eine Metallisierung aufweist, - Bereitstellung eines zweiten Substrates, das im Bereich einer zweiten Hauptfläche erste Enden von Via-Löchern und eine Struktur von Gräber und in einer dritten Hauptfläche zweite Enden der Via-Löcher aufweist, Verbinden des ersten Substrates mit dem zweiten Substrat, wobei die Seite der ersten Hauptfläche des ersten Substrates mit der Seite der dritten Hauptfläche des zweiten Substrates zusammengefügt werden, wobei die Via-Löcher an der Metallisierung der ersten Hauptfläche des ersten Substrates enden, - Ausfüllen der Via-Löcher und der Gräben mit einer leitfähigen Schicht undProvision of a first substrate which has at least one metallization in the region of a first main surface, provision of a second substrate which has first ends of via holes and a structure of graves in the region of a second main surface and second ends of the via holes in a third main surface connecting the first substrate to the second substrate, the side of the first main surface of the first substrate being joined to the side of the third main surface of the second substrate, the via holes ending in the metallization of the first main surface of the first substrate, - filling the via holes and the trenches with a conductive layer and
Abtragen der leitfähigen Schicht, bis zur noch in den Via- Löchern und den Gräben leitfähiges Material vorhanden ist, wobei in den Gr ben verlaufende Leiter mit der Metallisierung auf der ersten Hauptfläche des ersten Substrates elektrisch leitend verbunden werden.Removing the conductive layer until conductive material is still present in the via holes and the trenches, wherein conductors running in the trenches are electrically conductively connected to the metallization on the first main surface of the first substrate.
Dreidimensionale Integrierungsverfahren, insbesondere Chip- zu-Scheibe (Wafer) -Verfahren konnten bisher nicht nennenswert zum Einsatz kommen wegen der obengenannten Probleme. Da die bisher verwendeten Verfahren nicht in hoher Volumenfertigung ausgeführt werden, können durch die hohe Wertschöpfung des einzelnen Bausteins die hohen Ausbeuteprobleme ausgeglichen werden. Durch das erfindungsgemäße Verfahren wird es nun möglich, eine hohe Volumenfertigung zu fahren, da die eingangs genannten Probleme durch das erfindungsgemäße Verfahren gelöst werden.Three-dimensional integration processes, in particular chip-to-wafer (wafer) processes, have so far not been able to be used appreciably because of the problems mentioned above. Since the processes used up to now are not carried out in high volume production, the high yield problems of the individual building blocks can be compensated for. The method according to the invention now makes it possible to run a high volume production, since the problems mentioned at the beginning are solved by the method according to the invention.
Die Vorteile des erfindungsgemäßen Verfahrens ergeben sich hauptsächlich daraus, daß die Strukturen, die später mit Metall oder einem leitfähigen Material ausgefüllt werden, bereits vor der Chip-/Scheiben-Montage erzeugt werden und daher an einem konventionellen Scheibenmaterial hergestellt werden, wie es bisher schon bei zweidimensionaler Integration üblich war. Damit erfolgt die Photolithographietechnik auf einem Untergrund, der hinreichend eben und damit unproblematisch ist. Nach der Scheiben- /Chip-Montage, die einen unebenen Unter- grund schafft, muß keine photolithographische Strukturierung mehr vorgenommen werden, und es erfolgt nur noch die ganzflächige Metallabscheidung mit nachfolgender Rückätzung, die weitgehend unabhängig von der Planarizität der Chipoberfläche ist .The advantages of the method according to the invention result primarily from the fact that the structures which are later filled with metal or a conductive material are produced before the chip / wafer assembly and are therefore produced on a conventional wafer material, as has been the case up to now two-dimensional integration was common. The photolithography technology is thus carried out on a surface that is sufficiently flat and therefore unproblematic. After the wafer / chip assembly, which creates an uneven surface, there is no longer any need for photolithographic structuring, and there is only metal deposition with subsequent etching, which is largely independent of the planarity of the chip surface.
Eine vorteilhafte Ausgestaltung des erfindungsgemäßen Verfahrens ist dadurch gekennzeichnet, daß die Via-Löcher und/oder die Gräben durch Photolithographie und Ätzen erzeugt werden, wobei es sich um unproblematische und im Stand der Technik erprobte Verfahren zur Herstellung dieser Struktur handelt. Eine weitere vorteilhafte Ausgestaltung des erfindungsgemäßen Verfahrens ist dadurch gekennzeichnet, daß die Substrate durch eine Klebeschicht miteinander verbunden werden, so daß einerseits eine sichere Verbindung der beiden Substrate und andererseits eine Nachjustierung der beiden Substrate möglich wird.An advantageous embodiment of the method according to the invention is characterized in that the via holes and / or the trenches are produced by photolithography and etching, which are unproblematic and tried-and-tested methods for producing this structure. A further advantageous embodiment of the method according to the invention is characterized in that the substrates are connected to one another by an adhesive layer, so that on the one hand a secure connection of the two substrates and on the other hand readjustment of the two substrates is possible.
Eine weitere vorteilhafte Ausgestaltung des erfindungsgemäßen Verfahrens ist dadurch gekennzeichnet, daß die Klebeschicht vor dem Ausfüllen der Via-Löcher und der Gräben mit leitfähigem Material an den Via-Löchern entfernt wird, und prinzipiell ist es möglich, daß bei dem Ausfüllen der Via-Löcher die Klebeschicht durch thermische Einwirkung entfernt wird. Um eine sichere Entfernung der Klebeschicht an den Via-Löchern zu gewährleisten, wird jedoch bevorzugt, daß die Klebeschicht an den Via-Löchern entfernt wird.A further advantageous embodiment of the method according to the invention is characterized in that the adhesive layer is removed before the via holes and the trenches are filled with conductive material at the via holes, and in principle it is possible that when filling the via holes the Adhesive layer is removed by thermal action. In order to ensure safe removal of the adhesive layer on the via holes, however, it is preferred that the adhesive layer on the via holes be removed.
Eine weitere vorteilhafte Ausgestaltung des erfindungsgemäßenAnother advantageous embodiment of the invention
Verfahrens ist dadurch gekennzeichnet, daß zum Ausfüllen der Via-Löcher und Gräben mit einer leitfähigen Schicht eine Metallschicht auf der zweiten Hauptfläche des zweiten Substrats abgeschieden wird, was sowohl im Hinblick auf die elektrische Leitfähigkeit der dadurch erzeugten Leiterbahnen als auch hinsichtlich der Herstellungstechnologie eine vorteilhafte Vorgehensweise ist .The method is characterized in that a metal layer is deposited on the second main surface of the second substrate in order to fill the via holes and trenches with a conductive layer, which is an advantageous procedure both with regard to the electrical conductivity of the conductor tracks produced thereby and with regard to the production technology is.
Eine weitere vorteilhafte Ausgestaltung des erfindungsgemäßen Verfahrens ist dadurch gekennzeichnet, daß die Metallabschei - düng in einem PVD (physikalisches Aufdampfverfahren) - , CVD (chemische Abscheidung aus der Dampfphase) - oder ein Plattie- rungsverfahren durchgeführt wird. Mit diesen Verfahren können in vorteilhafterweise die unterschiedlichsten Abscheidungsbe- dingungen je nach den verwendeten Abscheidungsmaterialien eingesetzt werden.A further advantageous embodiment of the process according to the invention is characterized in that the metal deposition - fertilization in a PVD (physical vapor deposition process) -, CVD (chemical deposition from the vapor phase) - or a plating process is carried out. With these procedures you can the most varied of deposition conditions are advantageously used, depending on the deposition materials used.
Schließlich ist eine weitere vorteilhafte Ausgestaltung des erfindungsgemäßen Verfahren dadurch gekennzeichnet, daß die leitfähige Schicht bzw. die Metallschicht durch Zurückätzen oder ein CMP (chemisch mechanisches Polieren) -Verfahren abgetragen wird. Beide Verfahren eignen sich insofern für das Ab- tragen der leitfähigen Schicht als es auf eine extreme Genauigkeit bei der Abtragungshöhe nicht ankommt, weil nur sichergestellt werden muß, daß von der Metallisierung nur die Leiterteile in den Via-Löchern (sogenannte Plaques) und die Leiterbahnen übrigbleiben müssen.Finally, a further advantageous embodiment of the method according to the invention is characterized in that the conductive layer or the metal layer is removed by etching back or a CMP (chemical mechanical polishing) method. Both methods are suitable for removing the conductive layer insofar as extreme accuracy in the removal height is not important because it only has to be ensured that only the conductor parts in the via holes (so-called plaques) and the conductor tracks of the metallization must remain.
Ausführungsbeispiele der Erfindung werden nun anhand der beiliegenden Zeichnungen beschrieben. Es zeigen:Embodiments of the invention will now be described with reference to the accompanying drawings. Show it:
Figur 1 eine schematische Darstellung eines standardmäßig prozessierten ersten Substrates, im folgenden Bottom Wafer; Figur 2 eine schematische Darstellung eines standardmäßig prozessierten zweiten Substrates, im folgenden Top Wafer mit Via-Löchern; Figur 3 eine schematische Darstellung des Top Wafers mit einem Graben (trench) für eine spätere Leiterbahn; Figur 4 eine schematische Darstellung einer mikroelektronischen Struktur, bestehend aus einem Top Wafer und einem Bottom Wafer, die gebondet sind; Figur 5 eine schematische Darstellung eines mikroelektronischen Systems, wobei eine Metallschicht auf das Top Wafer aufgebracht worden ist; und Figur 6 eine schematische Darstellung einer mikroelektronischen Struktur, wobei Teile der Metallisierung des Top Wafers abgetragen sind.Figure 1 is a schematic representation of a standard processed first substrate, in the following bottom wafer; Figure 2 is a schematic representation of a standard processed second substrate, in the following top wafer with via holes; FIG. 3 shows a schematic representation of the top wafer with a trench for a later conductor track; FIG. 4 shows a schematic representation of a microelectronic structure, consisting of a top wafer and a bottom wafer, which are bonded; FIG. 5 shows a schematic illustration of a microelectronic system, a metal layer having been applied to the top wafer; and FIG. 6 shows a schematic illustration of a microelectronic structure, parts of the metallization of the top wafer having been removed.
Figur 1 zeigt eine schematische Darstellung eines Bottom Wafers 2 mit zwei Metallisierungen 4, 6, sogenannten Landing Pads, auf einer ersten Hauptfläche 10 des Bottom Wafers 2.FIG. 1 shows a schematic representation of a bottom wafer 2 with two metallizations 4, 6, so-called landing pads, on a first main surface 10 of the bottom wafer 2.
Figur 2 zeigt eine schematische Darstellung eines Top Wafers 12 mit zwei Via-Löchern 14, 16, die von einer zweiten Hauptfläche 18 des Top Wafers 12 bis zu einer dritten Hauptfläche 20 des Top Wafers 12 reichen.FIG. 2 shows a schematic illustration of a top wafer 12 with two via holes 14, 16, which extend from a second main surface 18 of the top wafer 12 to a third main surface 20 of the top wafer 12.
Figur 3 zeigt die schematische Darstellung des Top Wafers 12, nachdem zwischen den beiden Via-Löchern 14, 16 ein Graben 22 ausgebildet wurde, der nach der weiteren Verarbeitung zu einer Leiterbahn werden soll. Die Via-Löcher 14, 16 und der Graben 22 können durch ein photolithographisches Verfahren und Ätzen in dem zweiten Substrat 12, welches aus einem die- lektrischen Material besteht, erzeugt werden.FIG. 3 shows the schematic representation of the top wafer 12 after a trench 22 has been formed between the two via holes 14, 16 and is to become a conductor track after further processing. The via holes 14, 16 and the trench 22 can be produced by a photolithographic process and etching in the second substrate 12, which consists of a dielectric material.
Gemäß Figur 4 werden die beiden Substrate 2, 12 mit Hilfe einer Klebeschicht 24 gebondet oder miteinander verbunden. Die Klebeschicht 24 wird bei dieser Verfahrensstufe, fdas heisst vor dem Ausfüllen der Via-Löcher 14, 16 und des Grabens 22 mit leitfähigem Material an den Via-Löchern entfernt.According to FIG. 4, the two substrates 2, 12 are bonded or bonded to one another with the aid of an adhesive layer 24. The adhesive layer 24 is removed in this process stage, that is to say before the via holes 14, 16 and the trench 22 are filled with conductive material at the via holes.
Figur 5 zeigt eine schematische Darstellung des mikroelektronischen Systems, wobei die Via-Löcher 14, 16 und der Graben 20 sowie die zweite Hauptfläche 18 des Top Wafers 12 durch eine Metallisierungsschicht 26 ausgefüllt bzw. abgedeckt sind. Die Metallisierungsschicht 26 macht an den Via-Löchern 14, 16 Kontakt mit den Metallisierungen 4, 6 des Bottom Wafers 2.FIG. 5 shows a schematic representation of the microelectronic system, the via holes 14, 16 and the trench 20 and the second main surface 18 of the top wafer 12 being filled or covered by a metallization layer 26. The metallization layer 26 makes at the via holes 14, 16 contact with the metallizations 4, 6 of the bottom wafer 2.
Schließlich zeigt Figur 6 eine schematische Darstellung des mikroelektronischen Systems, wobei die Metallschicht 6 soweit abgetragen ist, daß nur noch die Metallisierung in den Via- Löchern 14, 16 als Plaques und in dem Graben 22 als Leiterbahn übrigbleibt. Damit ist die Herstellung des mikroelektronischen Systems abgeschlossen, welches nun als Einheit wei- terverarbeitet werden kann. Finally, FIG. 6 shows a schematic representation of the microelectronic system, the metal layer 6 being removed to such an extent that only the metallization remains in the via holes 14, 16 as plaques and in the trench 22 as a conductor track. This completes the manufacture of the microelectronic system, which can now be further processed as a unit.

Claims

Patentansprüche claims
1. Verfahren zur dreidimensionalen Integration mikroelektro- nischer Systeme mit folgenden Verfahrensschritten:1. Process for three-dimensional integration of microelectronic systems with the following process steps:
Bereitstellen eines ersten Substrates, das im Bereich einer ersten Hauptfläche zumindest eine Metallisierung aufweist , Bereitstellen eines zweiten Substrates, das im Bereich ei- ner zweiten Hauptfläche erste Enden von Via-Löchern und eine Struktur von Gräben in einer dielektrischen Schicht und in einer dritten Hauptfläche zweite Enden der Via- Löcher aufweist, Verbinden des ersten Substrates mit dem zweiten Substrat, wobei die Seite der ersten Hauptfläche des ersten Substrates mit der Seite der dritten Hauptfläche des zweiten Substrates zusammengefügt werden, wobei die Via-Löcher an der Metallisierung an der ersten Hauptfläche enden; Ausfüllen der Via-Löcher und der Gräben mit einer leitfä- higen Schicht, undProviding a first substrate that has at least one metallization in the area of a first main area, providing a second substrate that has first ends of via holes in the area of a second main area and a structure of trenches in a dielectric layer and second in a third main area Having ends of the via holes, connecting the first substrate to the second substrate, the side of the first main surface of the first substrate being joined to the side of the third main surface of the second substrate, the via holes ending at the metallization on the first main surface ; Filling the via holes and the trenches with a conductive layer, and
Abtragen der leitfähigen Schicht, bis nur noch in den Via- Löchern und den Gräben leitfähiges Material vorhanden ist, wobei in den Gräben vorhandene Leiter mit der Metallisierung auf der ersten Hauptfläche des ersten Substrates elektrisch leitend verbunden werden.Removal of the conductive layer until conductive material is only present in the via holes and the trenches, conductors present in the trenches being electrically conductively connected to the metallization on the first main surface of the first substrate.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Via-Löcher und/oder die Gräben durch ein photolithographisches Verfahren und Ätzen erzeugt werden.2. The method according to claim 1, characterized in that the via holes and / or the trenches are produced by a photolithographic method and etching.
Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Substrate durch eine Klebeschicht miteinander verbunden werden. A method according to claim 1, characterized in that the substrates are connected to one another by an adhesive layer.
. Verfahren nach Anspruch 3, dadurch gekennzeichnet, daß die Klebeschicht vor dem Ausfüllen der Via-Löcher und der Gräben mit leitfähigem Material im Kontaktbereich zwi- sehen Metallisierung der 1. Hauptfläche und den Via- Löchern entfernt wird., A method according to claim 3, characterized in that the adhesive layer is removed before filling the via holes and the trenches with conductive material in the contact area between the metallization of the 1st main surface and the via holes.
5. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß zum Ausfüllen der Via-Löcher und Gräben mit einer leitfä- higen Schicht eine Metallschicht auf der zweiten5. The method according to claim 1, characterized in that for filling the via holes and trenches with a conductive layer, a metal layer on the second
Hauptfläche des zweiten Substrates abgeschieden wird.Main surface of the second substrate is deposited.
6. Verfahren nach Anspruch 5, dadurch gekennzeichnet, daß die Metallabscheidung in einem PVD-, einem CVD- oder Plattierungsverfahren durchgeführt wird.6. The method according to claim 5, characterized in that the metal deposition is carried out in a PVD, a CVD or plating process.
7. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die leitfähige Schicht bzw. die Metallschicht durch Zurückätzen oder ein CMP-Verfahren abgetragen wird. 7. The method according to claim 1, characterized in that the conductive layer or the metal layer is removed by etching back or a CMP process.
PCT/DE2000/003309 1999-09-29 2000-09-22 Method for the tri-dimensional integration of micro-electronic systems WO2001024256A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008072165A1 (en) * 2006-12-12 2008-06-19 Nxp B.V. Method of manufacturing openings in a substrate, a via in a substrate, and a semiconductor device comprising such a via

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5380681A (en) * 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
EP0907206A1 (en) * 1997-10-01 1999-04-07 Matsushita Electronics Corporation Substrate through-contact and its fabrication method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH063837B2 (en) * 1987-03-03 1994-01-12 シャープ株式会社 Method for manufacturing three-dimensional semiconductor integrated circuit
DE4433846C2 (en) * 1994-09-22 1999-06-02 Fraunhofer Ges Forschung Method of making a vertical integrated circuit structure
DE19516487C1 (en) * 1995-05-05 1996-07-25 Fraunhofer Ges Forschung Vertical integration process for microelectronic system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5380681A (en) * 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
EP0907206A1 (en) * 1997-10-01 1999-04-07 Matsushita Electronics Corporation Substrate through-contact and its fabrication method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008072165A1 (en) * 2006-12-12 2008-06-19 Nxp B.V. Method of manufacturing openings in a substrate, a via in a substrate, and a semiconductor device comprising such a via
US7927966B2 (en) 2006-12-12 2011-04-19 Nxp B.V. Method of manufacturing openings in a substrate, a via in substrate, and a semiconductor device comprising such a via

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