WO2001022475A2 - Method for dicing mesa-diodes - Google Patents
Method for dicing mesa-diodes Download PDFInfo
- Publication number
- WO2001022475A2 WO2001022475A2 PCT/EP2000/008977 EP0008977W WO0122475A2 WO 2001022475 A2 WO2001022475 A2 WO 2001022475A2 EP 0008977 W EP0008977 W EP 0008977W WO 0122475 A2 WO0122475 A2 WO 0122475A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor
- substrate
- semiconductor body
- mask pattern
- crystal orientation
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000013078 crystal Substances 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 238000005422 blasting Methods 0.000 claims abstract description 13
- 239000000843 powder Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24C—ABRASIVE OR RELATED BLASTING WITH PARTICULATE MATERIAL
- B24C3/00—Abrasive blasting machines or devices; Plants
- B24C3/32—Abrasive blasting machines or devices; Plants designed for abrasive blasting of particular work, e.g. the internal surfaces of cylinder blocks
- B24C3/322—Abrasive blasting machines or devices; Plants designed for abrasive blasting of particular work, e.g. the internal surfaces of cylinder blocks for electrical components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3046—Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
Definitions
- the invention relates to a method of manufacturing a semiconductor device having a semiconductor body comprising a monocrystalline semiconductor substrate of silicon the surface of which has a crystal orientation, in which semiconductor substrate a semiconductor element is formed, and the surface of the semiconductor body is covered with a mask pattern, after which a part of the semiconductor body is removed by means of powder blasting.
- Such a method is employed, for example, in the manufacture of (discrete) diodes.
- An important advantage of this method resides in that it is comparatively clean and inexpensive, and in that it is extremely suited for mass-production.
- Such a method is known from United States patent specification 3,693,302, published on 26-09-1972. Said patent specification shows how a silicon substrate, which comprises a pn-junction, is placed on a carrier, after which a mask pattern is provided on the substrate. Parts of the silicon semiconductor body situated between the mask pattern are then removed by means of powder blasting, in which process individual semiconductor elements, in this case semiconductor diodes, are formed as mesa-shaped parts. After a possible passivation of the edges of the mesa, individual diodes can be detached from the carrier and are ready for processing.
- a method of the type mentioned in the opening paragraph is characterized in that the (111) crystal orientation is chosen as the crystal orientation of the substrate, and the longitudinal direction of the mask pattern is aligned with respect to the (111) crystal orientation of the substrate in such a way that the removed part of the semiconductor body has a symmetric profile when viewed in cross-section.
- the invention is based on the following recognitions. First of all, that silicon with a (111) crystal orientation i.e. the surface of the substrate lies in a (1 11) plane, can very suitably be used for the manufacture of, in particular, discrete semiconductor devices such as diodes, which are obtained as mesa-shaped diodes (akkoord ?, zie Ned.
- the invention is further based on the recognition that the quality of the I-V characteristic of such devices, which is not high and insufficiently reproducible, is caused by crystal damage at the side faces of a mesa-shaped diode, particularly at the location where a pn-junction of the device is exposed, which damage is caused by powder blasting.
- greater symmetry of the profile formed by removing a part of the semiconductor body situated next to the mesa to be formed results in less damage to and a higher quality of the devices obtained and in a better reproducibility of the manufacturing process.
- the invention is based on the recognition that a more symmetrical profile of the removed part of the semiconductor body can be achieved if, contrary to what is customary, the mask pattern used in the manufacture is not randomly provided on the semiconductor body but instead is provided so as to be aligned in a specific way on the (111) crystal orientation of the substrate. It has been found in experiments that if the longitudinal direction of the mask pattern includes an angle (60) of approximately 30 degrees (plus or minus an integral number of times 60 degrees) with a projected (110) or (100) direction of the (111) silicon, the above- mentioned symmetrical profile is obtained over a substantial part of the circumference (particularly the part of the circumference where the distance to an adjacent diodes is smallest) of the device to be formed.
- a noticeable improvement is achieved already if said angle lies in the range between 20 and 40 degrees.
- the improvement is substantially maximal if said angle lies in the range between 28 and 32 degrees.
- a mesa-shaped body is formed from the semiconductor body
- the mask pattern is formed by a number of rows of sub-masks, with two adjacent rows being shifted with respect to each other over half the distance between two sub-masks.
- the mask pattern of this embodiment looks like a close sphere packing when viewed in projection.
- the sub-masks are provided with the shape of a regular hexagon. In this variant, the material loss is minimal.
- this variant results in a symmetrical profile of the removed part of the semiconductor body substantially throughout the circumference of the semiconductor element to be formed. Only at the six angular points, the above-mentioned profile is still slightly asymmetrical.
- Optimum results are achieved if the ratio of the width of the removed part of the semiconductor body to the thickness of the removed part of the semiconductor body is chosen to be in the range between 3 and 1/3, and preferably between 2 and Vz. Below the lower limit of the first-mentioned range, the process takes up too much time, while above the upper limit of said range, too much loss of material occurs. In the last-mentioned range, optimum results are achieved as regards the symmetry of the profile of the removed part of the semiconductor body. In this range, the risk that a powder particle is repeatedly incident on the semiconductor body is minimal. It has been found that such repeated incidence leads to an increase of the asymmetry of the profile of the removed part of the semiconductor body.
- a method in accordance with the invention can also be used in the manufacture of an IC (Integrated Circuit), it is particularly suited to manufacture discrete semiconductor elements, such as diodes.
- IC Integrated Circuit
- discrete semiconductor elements such as diodes.
- Fig. 1 and Fig. 2 diagrammatically show, partly as a plan view and partly as a cross-sectional view at right angles to the thickness direction, a semiconductor device comprising a semiconductor element in successive stages of the manufacturing process, using a method in accordance with the invention
- Fig. 3 is a diagrammatic plan view of a crystallographic representation of a substrate used in the method in accordance with the invention.
- Fig. 4 is a diagrammatic plan view of another semiconductor device comprising a semiconductor element in a stage of the manufacturing process which corresponds to Fig. 1 and which manufacturing process is carried out using a method in accordance with the invention .
- the Figures are diagrammatic and not drawn to scale, particularly the dimensions in the thickness direction being exaggerated strongly for clarity. Corresponding areas bear the same reference numerals whenever possible.
- Fig. 1 and Fig. 2 diagrammatically show, partly in a plan view and partly in a cross-sectional view at right angles to the thickness direction, a semiconductor device comprising a semiconductor element in successive stages of the manufacturing process, using a method in accordance with the invention.
- the semiconductor device (see Fig. 2) comprises a semiconductor body 11 which includes a monocrystalline silicon substrate 32 wherein a semiconductor element 10, in this example a diode 10, is formed.
- the diode 10 comprises, in this case, the substrate 32 a part 32B of which is provided with the p- conductivity type by means of diffusion of boron atoms.
- the remaining part 32A of the substrate 32 is of the n-conductivity type.
- the lower side and the upper side of the diode 10 are provided with connection conductors 33, 34.
- the diode 10 is formed (see Fig. 1) by providing the surface of the monocrystalline substrate 32 having a crystal orientation with a mask pattern 40, which in this case is composed of a number of round sub-masks 41 , and subsequently removing a part 50 of the semiconductor 11 by means of powder blasting.
- the crystal orientation (111) is chosen as the crystal orientation of the substrate 32, and the longitudinal direction M of the mask pattern 40 is aligned with respect to the crystal orientation of the substrate 32 in such a manner that the removed part 50 of the semiconductor body 11 has a symmetrical profile when viewed in cross-section (perpendicularly to the thickness direction).
- the invention is based on the following surprising recognitions. First of all, the recognition that (11 l)-oriented silicon can very suitably be used to manufacture, in particular, a discrete semiconductor device such as the mesa-shaped diode 10.
- the invention is further based on the recognition that powder blasting may cause crystal damage at the side faces of such a diode 10, which may adversely affect the electrical characteristics of the pn-junction of diode 10.
- powder blasting may cause crystal damage at the side faces of such a diode 10, which may adversely affect the electrical characteristics of the pn-junction of diode 10.
- a more symmetrical profile of the part 50 of the semiconductor body 11 removed in the manufacture of the diode 10 results in a reduction of the crystal damage and, particularly, in more uniform and better reproducible damage.
- the quality of a diode 10 manufactured by means of a method in accordance with the invention is higher but also the spread in properties of the diodes 10 obtained is smaller and the reproducibility of the properties is improved.
- the invention is based on the recognition that a suitable, highly symmetrical profile of the removed part 50 of the semiconductor body 11 can be obtained if, contrary to what is customary, the mask pattern 40 used in the manufacture is not randomly provided on the surface of the semiconductor body 1 1, but instead is provided so as to be oriented in a specific way on the (111) crystal orientation.
- Such a suitable alignment includes the provision of the longitudinal direction M of the mask pattern 40 at an angle 60 with respect to the projected (100) or (110) axes of symmetry of the (111) substrate 32, which angle ranges between 20 and 40 degrees plus or minus an integral number of times 60 degrees, and is preferably chosen to be approximately equal to 30 degrees plus or minus an integral number of times 60 degrees. All of this can be explained in the following manner with reference to Fig. 1 and Fig. 3.
- Fig. 3 is a diagrammatic plan view of a crystallographic representation of a substrate 32 used in the method according to the invention.
- the crystal structure of silicon can be construed as the superposition of two f.c.c.
- the triangle O represents the (111) plane of the silicon crystal which is situated in the surface of the substrate 32.
- the directions referenced 100 and 110 then correspond to projections of, respectively, the (100) and (110) directions on the (111) plane of the silicon crystal.
- Fig. 1 shows that the orientations of the silicon crystal referenced Ol and O2 form the limits, with respect to (the longitudinal direction M of) the mask pattern 40, within which a random orientation exists (?). The reason for this being that the senary symmetry of the mask pattern 40 and of said projections of the (100) and (110) directions, cause all possible orientations to be equivalent to orientations situated within this domain.
- the projected crystal axis L coincides with the direction M of the mask pattern 40.
- the part 50 of the semiconductor body 11 which is removed in the powder-blasting operation and which substantially coincides with apertures 1, 2, 3, 4, 5, 6 between the round sub-masks 41.
- the walls of the channels formed in the powder-blasting operation which are situated between the apertures 2-3, 4-5 and 6-1 extend in the (100) direction for the central sub-mask 41 in Fig. 1.
- the other three channel walls 1-2, 3-4 and 5-6 extend in the (110) direction and exhibit a higher silicon-removal rate (?) during the powder-blasting operation. The same applies to adjacent sub-masks 41.
- the channel wall extends in the (110) direction, towards the diode 10 on the outside, the wall extends in the (100) direction (identical to the wall 4-5 for the central sub-mask 41). Due to the difference in silicon-removal rate (?), in this case, the channel 1-2 is not dug symmetrically, which leads to a risk of under-radiation (?). This in turn leads to a deviation of the symmetry of the diode 10 as a result of the non-symmetric channels. The geometry of the diode 10 will exhibit a triangular deviation from the round mask geometry. The deviation is not directed towards the larger apertures 1 through 6 but towards the narrower channels between these apertures.
- the apertures 1, 3, 5 extend in the 110 direction.
- All the walls around the apertures 2, 4, 6 extend in the 110 direction.
- the walls around the odd apertures will become larger and steeper more rapidly than the walls around even apertures due to the more rapid blasting behavior. This too leads to a triangular deformation of the diode 10, in this instance, however, in the direction of the apertures. In this case, however, a similar material decrease is expected, in all cases, on the narrowest parts of the channels between the apertures.
- the configuration in accordance with the invention which is referenced O2
- the longitudinal direction M of the mask pattern 40 should be rotated through (approximately) 30 degrees with respect to one of the (projected) crystal axes 100, 110.
- the mask pattern 40 chosen in Fig. 1 consists of round sub-masks 41 having a diameter of, for example, 1 mm, and the geometry of said mask pattern, viewed in projection, corresponds to a close sphere packing.
- the method in accordance with the invention results in a small loss of material and hence a high yield.
- the sub-masks 41 are depicted so as to be in contact with each other, however, in practice there will be a small interspace between the sub-masks 41, for example, of 100 or 150 ⁇ m.
- the thickness of the substrate 32 is 240 ⁇ m.
- Fig. 4 is a diagrammatic plan view of another semiconductor device comprising a semiconductor element in a stage of the manufacturing process which corresponds to Fig. 1, and which manufacturing process is carried out using a method in accordance with the invention.
- the sub-masks 41 of the mask pattern 40 are provided with a hexagonal shape.
- the removed part 50 of the semiconductor body 11 has a symmetrical profile substantially throughout the circumference of each diode 10. Only at the angular points of the hexagon 41 there is still a slight asymmetry.
- the semiconductor body 11 is metallized bilaterally and secured with the substrate side on a carrier plate 30 of glass, for example by means of a sugar solution.
- the upper side is subsequently provided with a self-adherent mask layer 41 of, for example, Ordyl (Trademark of Ohka Kogyo, Tokyo, Japan) BF05 having a thickness of 50 ⁇ m.
- the layer 41 is provided with the mask pattern 40 by means of photolithography and etching.
- the alignment of the mask pattern 40 with respect to the (111) orientation of the substrate 32 is achieved in a simple manner by aligning with respect to a facet, not shown in the Figure, with which the substrate 32 is provided already during the manufacture thereof.
- the device may be subjected, in this stage, to a thermal treatment.
- the subsequent powder-blasting process is carried out, in this case, on a machine which is commercially available, for example, under the trade name Schlick.
- For the powder use can be made, for example, of sand.
- a powder of aluminium oxide particles having a diameter of 23.5 ⁇ m is used at a pressure of 3 bar and a rate of 172 g/min.
- these semiconductor diodes are removed from the carrier plate 30 and are ready for further processing, for example final assembly.
- the dimensions of the device manufactured are chosen as follows.
- the thickness of the substrate 32 which corresponds to the thickness D of the removed part 50 of the semiconductor body 11, is 240 ⁇ m in this case.
- the diameter of the substrate is 4 inch.
- the diameter of the sub-masks 41 is 1000 ⁇ m in this case, and the interspace between the sub-masks, i.e. the minimum channel width W, is 150 ⁇ m.
- the ratio W/D is approximately 2/3.
- the ratio W/D is chosen in the range between 3 and 1/3. It has been found that such a choice leads to a maximum symmetry of the profile of the removed part 50 of the semiconductor body 11.
- W/D is chosen in the range between 2 and l ⁇ , as in this example.
- semiconductor elements other than diodes may be used, such as (discrete) transistors.
- the semiconductor body may comprise, in addition to a silicon substrate, one or more epitaxial layers.
- the invention can also be applied to make holes or wells in a semiconductor body. In that case, the invention can also be applied to non-discrete semiconductor elements.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Dicing (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00964168A EP1131850A2 (en) | 1999-09-22 | 2000-09-13 | Method for dicing mesa-diodes |
JP2001525751A JP2003510811A (en) | 1999-09-22 | 2000-09-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99203099.9 | 1999-09-22 | ||
EP99203099 | 1999-09-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001022475A2 true WO2001022475A2 (en) | 2001-03-29 |
WO2001022475A3 WO2001022475A3 (en) | 2001-05-25 |
Family
ID=8240664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2000/008977 WO2001022475A2 (en) | 1999-09-22 | 2000-09-13 | Method for dicing mesa-diodes |
Country Status (4)
Country | Link |
---|---|
US (1) | US6508693B1 (en) |
EP (1) | EP1131850A2 (en) |
JP (1) | JP2003510811A (en) |
WO (1) | WO2001022475A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7208803B2 (en) * | 2004-05-05 | 2007-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a raised source/drain and a semiconductor device employing the same |
US11780054B2 (en) * | 2021-08-18 | 2023-10-10 | Taichi Metal Material Technology Co., Ltd. | Cutting method by using particle beam of metallic glass |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3693302A (en) | 1970-10-12 | 1972-09-26 | Motorola Inc | Abrasive dicing of semiconductor wafers |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1527154A (en) * | 1967-04-19 | 1968-05-31 | Silec Liaisons Elec | Process for cutting semiconductor devices |
NL177866C (en) * | 1976-11-30 | 1985-12-02 | Mitsubishi Electric Corp | METHOD FOR MANUFACTURING SEPARATE SEMICONDUCTOR ELEMENTS, WITH SEMICONDUCTOR MEMORY CONDUCTED IN A DISC-SHAPED BODY MATERIAL. |
JPH01133703A (en) * | 1987-11-20 | 1989-05-25 | Hitachi Ltd | Semiconductor wafer and semiconductor device using the same |
US6067062A (en) * | 1990-09-05 | 2000-05-23 | Seiko Instruments Inc. | Light valve device |
US5401690A (en) | 1993-07-08 | 1995-03-28 | Goodark Electronic Corp. | Method for making circular diode chips through glass passivation |
CA2217084A1 (en) * | 1996-10-30 | 1998-04-30 | Tin-Tack Peter Cheung | Hydrogenation catalysts and processes therewith |
TW419442B (en) * | 1996-12-18 | 2001-01-21 | Koninkl Philips Electronics Nv | Method of post-etching a mechanically treated substrate |
JP3755228B2 (en) * | 1997-04-14 | 2006-03-15 | 株式会社ニコン | Charged particle beam exposure system |
-
2000
- 2000-09-13 JP JP2001525751A patent/JP2003510811A/en not_active Withdrawn
- 2000-09-13 EP EP00964168A patent/EP1131850A2/en not_active Withdrawn
- 2000-09-13 WO PCT/EP2000/008977 patent/WO2001022475A2/en active Application Filing
- 2000-09-21 US US09/666,232 patent/US6508693B1/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3693302A (en) | 1970-10-12 | 1972-09-26 | Motorola Inc | Abrasive dicing of semiconductor wafers |
Also Published As
Publication number | Publication date |
---|---|
JP2003510811A (en) | 2003-03-18 |
WO2001022475A3 (en) | 2001-05-25 |
EP1131850A2 (en) | 2001-09-12 |
US6508693B1 (en) | 2003-01-21 |
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