WO2001020648A3 - Quantum corrections for modeling semiconductor behavior - Google Patents

Quantum corrections for modeling semiconductor behavior Download PDF

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Publication number
WO2001020648A3
WO2001020648A3 PCT/US2000/040790 US0040790W WO0120648A3 WO 2001020648 A3 WO2001020648 A3 WO 2001020648A3 US 0040790 W US0040790 W US 0040790W WO 0120648 A3 WO0120648 A3 WO 0120648A3
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WO
WIPO (PCT)
Prior art keywords
implementation
semiconductor behavior
discretized
corrections
quantum
Prior art date
Application number
PCT/US2000/040790
Other languages
French (fr)
Other versions
WO2001020648A2 (en
Inventor
Eugeny Lyumkis
Boris Polsky
Oleg Penziz
Original Assignee
Eugeny Lyumkis
Boris Polsky
Oleg Penziz
Ise Integrated Systems Enginee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eugeny Lyumkis, Boris Polsky, Oleg Penziz, Ise Integrated Systems Enginee filed Critical Eugeny Lyumkis
Publication of WO2001020648A2 publication Critical patent/WO2001020648A2/en
Publication of WO2001020648A3 publication Critical patent/WO2001020648A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/20Design optimisation, verification or simulation
    • G06F30/23Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A method for implementation of a model of MOS transistor with enhanced accuracy, with selected quantum effects included. The implementation provides zero current at equilibrium, which corresponds to a differential formulation, in a discretized formulation. At least one of electron concentration, hole concentration and electrostatic potential is reformulated and transformed in this discretized implementation.
PCT/US2000/040790 1999-09-17 2000-08-30 Quantum corrections for modeling semiconductor behavior WO2001020648A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39893899A 1999-09-17 1999-09-17
US09/398,938 1999-09-17

Publications (2)

Publication Number Publication Date
WO2001020648A2 WO2001020648A2 (en) 2001-03-22
WO2001020648A3 true WO2001020648A3 (en) 2002-04-25

Family

ID=23577424

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/040790 WO2001020648A2 (en) 1999-09-17 2000-08-30 Quantum corrections for modeling semiconductor behavior

Country Status (1)

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WO (1) WO2001020648A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2002356476A1 (en) * 2002-08-27 2004-03-19 Freescale Semiconductor, Inc. Fast simulation of circuitry having soi transistors

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DORT VAN M J ET AL: "A SIMPLE MODEL FOR QUANTISATION EFFECTS IN HEAVILY-DOPED SILICON MOSFETS AT INVERSION CONDITIONS", SOLID STATE ELECTRONICS, ELSEVIER SCIENCE PUBLISHERS, BARKING, GB, vol. 37, no. 3, March 1994 (1994-03-01), pages 411 - 414, XP001031086, ISSN: 0038-1101 *
ZHIPING YU ET AL: "Circuit/device modeling at the quantum level", COMPUTATIONAL ELECTRONICS, 1998. IWCE-6. EXTENDED ABSTRACTS OF 1998 SIXTH INTERNATIONAL WORKSHOP ON OSAKA, JAPAN 19-21 OCT. 1998, PISCATAWAY, NJ, USA,IEEE, US, 19 October 1998 (1998-10-19), pages 222 - 229, XP002184978, ISBN: 0-7803-4369-7 *

Also Published As

Publication number Publication date
WO2001020648A2 (en) 2001-03-22

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