AU2002356476A1 - Fast simulation of circuitry having soi transistors - Google Patents

Fast simulation of circuitry having soi transistors

Info

Publication number
AU2002356476A1
AU2002356476A1 AU2002356476A AU2002356476A AU2002356476A1 AU 2002356476 A1 AU2002356476 A1 AU 2002356476A1 AU 2002356476 A AU2002356476 A AU 2002356476A AU 2002356476 A AU2002356476 A AU 2002356476A AU 2002356476 A1 AU2002356476 A1 AU 2002356476A1
Authority
AU
Australia
Prior art keywords
circuitry
soi transistors
fast simulation
simulation
fast
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002356476A
Inventor
Yury Borisovich Egorov
Sergei Vitalievich Gavrilov
Alexei Lvovich Glebov
Dmitry Yurievich Nadezhin
Rajendran Venkatachari Panda
Vladimir Petrovich Zolotov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2002356476A1 publication Critical patent/AU2002356476A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU2002356476A 2002-08-27 2002-08-27 Fast simulation of circuitry having soi transistors Abandoned AU2002356476A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/RU2002/000397 WO2004021252A1 (en) 2002-08-27 2002-08-27 Fast simulation of circuitry having soi transistors

Publications (1)

Publication Number Publication Date
AU2002356476A1 true AU2002356476A1 (en) 2004-03-19

Family

ID=31974190

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002356476A Abandoned AU2002356476A1 (en) 2002-08-27 2002-08-27 Fast simulation of circuitry having soi transistors

Country Status (3)

Country Link
US (1) US7127384B2 (en)
AU (1) AU2002356476A1 (en)
WO (1) WO2004021252A1 (en)

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US8020122B2 (en) * 2005-06-07 2011-09-13 The Regents Of The University Of California Circuit splitting in analysis of circuits at transistor level
US8063713B2 (en) * 2005-06-29 2011-11-22 The Regents Of The University Of California Differential transmission line having a plurality of leakage resistors spaced between the transmission line
US7581199B1 (en) * 2005-08-08 2009-08-25 National Semiconductor Corporation Use of state nodes for efficient simulation of large digital circuits at the transistor level
US7412695B1 (en) * 2005-08-08 2008-08-12 National Semiconductor Corporation Transient state nodes and a method for their identification
US20070136044A1 (en) * 2005-12-13 2007-06-14 Beattie Michael W Efficient simulation of dominantly linear circuits
US20070234253A1 (en) * 2006-03-29 2007-10-04 International Business Machines Corporation Multiple mode approach to building static timing models for digital transistor circuits
US8060355B2 (en) * 2007-07-27 2011-11-15 Synopsys, Inc. Automatic, hierarchy-independent partitioning method for transistor-level circuit simulation
US9405870B2 (en) * 2007-09-06 2016-08-02 Globalfoundries Inc. Generating coverage data for a switch frequency of HDL or VHDL signals
US8245165B1 (en) * 2008-04-11 2012-08-14 Cadence Design Systems, Inc. Methods and apparatus for waveform based variational static timing analysis
US8499230B2 (en) 2008-05-07 2013-07-30 Lsi Corporation Critical path monitor for an integrated circuit and method of operation thereof
US8868395B2 (en) * 2008-10-27 2014-10-21 Synopsys, Inc. Fast simulation method for integrated circuits with power management circuitry
US8594989B2 (en) * 2009-04-09 2013-11-26 International Business Machines Corporation Compensating for variations in device characteristics in integrated circuit simulation
US8093916B2 (en) * 2009-06-05 2012-01-10 United Microelectronics Corp, Method of characterizing a semiconductor device and semiconductor device
US8239805B2 (en) * 2009-07-27 2012-08-07 Lsi Corporation Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method
US8463587B2 (en) * 2009-07-28 2013-06-11 Synopsys, Inc. Hierarchical order ranked simulation of electronic circuits
FR2949564B1 (en) * 2009-08-28 2012-01-06 Commissariat Energie Atomique METHOD AND DEVICE FOR EVALUATING THE ELECTRIC PERFORMANCES OF AN FDSOI TRANSISTOR
US8327302B2 (en) * 2009-10-16 2012-12-04 International Business Machines Corporation Techniques for analysis of logic designs with transient logic
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US8849643B2 (en) * 2011-05-13 2014-09-30 International Business Machines Corporation Table-lookup-based models for yield analysis acceleration
US9002692B2 (en) * 2012-03-13 2015-04-07 Synopsys, Inc. Electronic circuit simulation method with adaptive iteration
US8645883B2 (en) * 2012-05-08 2014-02-04 Oracle International Corporation Integrated circuit simulation using fundamental and derivative circuit runs
US8464199B1 (en) * 2012-05-16 2013-06-11 International Business Machines Corporation Circuit design using design variable function slope sensitivity
US8990739B2 (en) * 2012-12-04 2015-03-24 The Mathworks, Inc. Model-based retiming with functional equivalence constraints
US9779195B2 (en) 2012-12-04 2017-10-03 The Mathworks, Inc. Model-based retiming with functional equivalence constraints
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US9898564B2 (en) * 2014-01-15 2018-02-20 Sage Software, Inc. SSTA with non-gaussian variation to second order for multi-phase sequential circuit with interconnect effect
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US10394999B2 (en) 2015-11-18 2019-08-27 International Business Machines Corporation Analysis of coupled noise for integrated circuit design
US11100268B1 (en) * 2017-08-29 2021-08-24 Cadence Design Systems, Inc. Fast and accurate simulation for power delivery networks with integrated voltage regulators
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Also Published As

Publication number Publication date
WO2004021252A1 (en) 2004-03-11
US7127384B2 (en) 2006-10-24
US20040044510A1 (en) 2004-03-04

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase