Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
  • H04L25/40—Transmitting circuits; Receiving circuits
  • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
  • H04L25/4902—Pulse width modulation; Pulse position modulation

Definitions

• the present invention relates to a method and system for data transmission via a data bus from a transmitter to a receiver or between several transceivers, the transmitter generating data signal transitions to the transmission bus.
• the present invention can be applied instead of any traditional data transmission protocol, such as CAN-protocol, in Intelligent Wiring Systems (IWS) for vehicles, such as described in the applicants patent applications WO 99/25585, WO 99/25586, WO 99/26331 , WO 95/15594, WO 97/4901 and PCT/F 198/00710.
• IWS Intelligent Wiring Systems
• the invention can be applied also in intelligent wiring systems for building automation in homes and offices.
• the object of the present invention is to achieve an improved method for data transmission such that the above mentioned problems can be substantially reduced.
• This object can be achieved by a method according to the features of claim 1.
• the object can also be achieved by a system according to the features of claim 14.
• Fig. 1 shows an example of a data bit quartet composed transferred by the method of modulating the time delay between successive transitions
• Fig. 2 shows an example of a message sent by several data bit quartets in packet format, each bit quartet being composed according to the principle of Fig. 1 ;
• Fig. 3 shows an example of a part of an Intelligent wiring system (IWS) wherein the new method for data transmission can be advantageously applied.
• IWS Intelligent wiring system
• Fig. 4 shows an example of a message composed of several transition delay modulated bit quartets according to the principle of Fig. 1 , the message being planned to be applied in the system part according to Fig. 3.
• Fig. 5 shows an example of a driver unit (transceiver) operating under the new IWS protocol.
• IWS data transfer is based on pulse width modulation of bit quartets.
• Each quartet contains or represents four data bits.
• the binary value of each quartet is used to adjust the delay between successive output transitions.
• a receiver measures delays between transitions and converts them back to the original data.
• This modulation method generates less transitions and less EMI-interference than ordinary bit-wise transfer methods when sending random data at the same average bit rate, because every transition in signal path can transfer one quar- tet (four bits) of data.
• the modulation method depends on signal transitions instead of signal states. There is no high / low or dominant / recessive states or bits as needed for prior data transportation implementations for automotive industry.
• a transition in the IWS (Intelligent Wiring System) cable is signaled by complementing the electric charge of signal wires and then leaving the new state of electric charge passively or using only a weak output driver to maintain the signal state in the cable. Synchronization ( Figures 1 , 2 and 4)
• a special synchronization pattern is used to find the start and the end of each data frame.
• the synchronization pattern contains two successive transitions.
• the time delay between synchronization transitions is one transmit clock cycle. Because all other quartets and heart beat signals have longer delay between transitions no transmitted signal can interfere with the synchronization signal. This signal is possible to insert and detect at any time during the data transfer. Every synchronization pattern starts a new data frame reception.
• Every unit is responsible for generating the heartbeat signal at specified periods.
• the heartbeat signal is also used for detecting the condition of the transmission line. If, for some reason, the heart beat signal does not work in proper way the supervisory system can immediately alert the user about the damage and change the data transmission protocol into emergency mode.
• the master junction unit disconnects all data lines which can not generate proper heartbeat signals to get the rest of the system to working condition. All supervisory elements are doubled independently. Every single data cable fault will be detected and corrected without major functional disadvantages.
• a transmitter is not allowed to send a new transition immediately after detection of a new transition. This safeguard delay prevents the possibility that two or more transmitters could simultaneously set different charges to the signal cable and cause a true collision situation.
• Any transmitter can start transmitting when it detects the synchronization signal. In the case, that there is no active transmissions running, the transmitter can start transmitting of a new synchronization signal itself.
• an active transmitter detects at any time an extra transition in the signal cable, it should stop transmission immediately. This happens normally during the first quartets of the data packet.
• the transmitter which have shorter quartet, sends the transition of the quartet earlier than transmitters with a longer message.
• the transmitter with the shorter message quartet can continue without interruption and the transmitter with the longer message quartet gives up.
• the extra transition situation may also happen when a very high priority transmitter breaks a transmission of a low priority transmitter by sending a new synchronization pattern in the middle of the low priority data frame.
• the receiver uses a receive clock frequency which is a multiple of the transmit signal frequency. This allows the receiver to measure the delay between transitions more precisely and to perform a digital signal conditioning before actual reception of the transition event.
• the receiver After a reception of a transition, the receiver evaluates the time delay value measured from the last successive transition and decides how to translate the received time information. Only narrow time windows are allowed for possible data quartets. Between allowed signal width windows there is a fail safe areas for detecting incorrect random transitions. If the measured delay value is not belonged to any allowed signal windows, it is discarded by the receiver. This procedure prevents efficiently a random signal pattern to be accidentally received as a valid data packet.
• a receiver If a receiver detects an illegal transition when it is actively receiving a message, it may generate an extra synchronization signal to break this transmission and to start the retransmission immediately.
• All messages have same basic format. 32 data bits delivered either to all receivers or to a single receiver with an acknowledge. All unused bit space (zero value quartets) will be spontaneously optimized to the shortest length during the modulation.
• a message contains following parts:
• This part of the message starts from the synchronization signal of the previous message or a new synchronization signal generated by the transmitter itself. All active transmitters may then start transmitting of message priority selection quartet. Possible values for the priority quartet are from 1 to 15. Zero value is reserved for acknowledge field. Many transmitters may have the same message priority. All transmitters start sending of their messages simultaneously. During the transmission any transmitter trying to send a longer message quartet than others will be efficiently eliminated due to collision prevention mecha- nism. At the end of the packet only one transmitter should be actively transmitting.
• This part of the message contains two quartets which uniquely selects the receiver for the message. If both target quartets have zero value then every receiver should receive a broadcast message. All receivers must have an unique pair of address quartets. This limits the maximum number of receivers to 255 units leaving one address for the broadcast. Data field ( Figures 1 , 2 and 4)
• This part of the message contains eight quartets used for actual data. Maxi- mum data bits in one message packet is 32-bits. Unused space will be spontaneously optimized to the shortest length during the modulation.
• This part of the message contains two quartets representing a 8-bit ECC value calculated from the target address field and the data field.
• the error check can detect unusual errors passed from other error checking procedures.
• This part of the message contains three quartets followed by a synchronization pattern sent by the receiver of the message.
• the first quartet is zero and next two quartets contains the address of the acknowledging receiver.
• the transmitter should immediately send a new synchronization signal to restart transmitting of the message. If no correct acknowledge has received after three retries the transmitter should delay the message and try again later. Messages which are addressed to every receiver are not acknowledged.
• Quality of the received signal timing is checked during the reception. This quality detection is important to prevent a random noise signal to be recognized to a valid message. No error checking methods used for short messages is reliable enough to withstand a pure random signal without the signal quality check.
• the transmitter compares the transmitted signal to received signal. If there is any difference between those two signals the transmitter stops sending the message before it will be received.
• the receiver When receiving a message the receiver checks the ECC code from the end of the data packet to confirm that the contents is logically correct and not messed up during the transmission.
• the signal can be selected to contain a bit pattern which is not near to any other used bit pattern. This way the probability of accidental reception of this specially selected signal is highly decreased.
• the system according to Fig. 3 includes IWS (Intelligent Wiring System) cable which includes two wires for power supply and two wires for data bus.
• IWS Intelligent Wiring System
• the block of master junction units is in data communication with adaptation and monitoring block, through which any external programming of the system can be made, which monitors the "heart beat" and fault messages from the system and which controls the on-line display to show the use the status of the system.
• Each cable branch has been provided by several intelligent sockets, which control the power supply from the IWS-cable to various loads, such as trunk light L1 , in response to various in- puts, such as closing the trunk hatch switch S1 , from any socket of the system.
• the number of sockets in the whole system for vehicle implementation is typically between 30-50, but may vary substantially depending on the application (e.g. in busses, ships, homes and offices).
• the operation of system part of Fig. 3 takes place in view of Fig. 4 according to following steps:
• Trunk hatch opens and closes the trunk light switch S1 - Input pin 11 connects to the ground and wakes up the CPU of socket 11
• the contents and/or tasks of the transceiver blocks A-L are as follows:
• a Transmit line driver contains a complementary slew rate limited push pull type line driver
• Bus arbitration detector stops the transmitter when the bus arbitration has lost
• D Transmit control logic contains a state machine which controls all transmit logic units
• E IDLE delay detector detects long delays needed for the heart beat generation
• F Short edge filter utilizes 2 ⁇ s delay line to remove signal noise G Sync signal detector restarts both transmit and receive logic when new sync is detected
• H CRC control logic is used for error detection calculations during transmit and receive I Receive line driver contains a differential low pass filterering amplifier and a Schmitt trigger
• J Long edge filter utilizes 4 ⁇ S delay line to remove signal noise
• K Pulse width demodulator converts delayed transitions back to binary quartets
• Receive control logic contains a state machine which controls all receive logic units.

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• Physics & Mathematics (AREA)
• Spectroscopy & Molecular Physics (AREA)
• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Small-Scale Networks (AREA)

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Cited By (1)

Citations (6)

• 1999
  • 1999-09-08 FI FI991911A patent/FI112548B/sv active
• 2000
  • 2000-08-25 AU AU68449/00A patent/AU6844900A/en not_active Abandoned
  • 2000-08-25 WO PCT/FI2000/000725 patent/WO2001018964A1/en active Application Filing

Patent Citations (6)

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