WO2001008380A1 - Acoustic and electronic echo cancellation using high resolution delay line - Google Patents
Acoustic and electronic echo cancellation using high resolution delay line Download PDFInfo
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- WO2001008380A1 WO2001008380A1 PCT/US2000/040441 US0040441W WO0108380A1 WO 2001008380 A1 WO2001008380 A1 WO 2001008380A1 US 0040441 W US0040441 W US 0040441W WO 0108380 A1 WO0108380 A1 WO 0108380A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
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- This invention relates to echo cancellation in telephone systems and, in particular, to cancellation of acoustic echoes and electronic echoes in telephone systems by means of a high resolution delay line.
- acoustic echo between an earphone or a speaker and a microphone and electrical echo generated in the switched network for routing a call between stations.
- acoustic echo is typically not much of a problem.
- speaker phones where several people huddle around a microphone and loudspeaker, acoustic feedback is much more of a problem.
- Hybrid circuits located at terminal exchanges or in remote subscriber stages of a fixed network are the principal sources of electrical echo. The distance that a signal travels causes a minimum delay. Digital calling apparatus further delays a signal in the digitizing process and in the batch (packet) mode that signals are often handled. Using a satellite relay can add considerably to the delay; a minimum of 250 milliseconds each way.
- An echo is perceived if a delay is greater than approximately twenty milliseconds.
- Digital packet transmission through a satellite can produce a delay in excess of 600 milliseconds.
- Modern network equipment is incapable of handling a delay longer than about 100 milliseconds.
- Acoustic delays, such as reverberations in a room, can be much longer, up to 1,500 milliseconds.
- echo canceling apparatus operates by subtracting a delayed or reconstructed original signal, or a contrived signal, from a composite signal (original sound plus echo) present in the line.
- the echo canceling apparatus can be either digital or analog. If digital, echo paths having very long propagation delays can be accommodated.
- both electronic delays and acoustic delays can change during a call.
- the settings for an echo canceling circuit are not changed during a call, largely due to a long convergence time in the circuitry for finding and canceling an echo. Changing settings during a call would cause noticeable distortion in the sound, somewhat like a magnetic tape recording when the tape is deformed.
- the sampling rate of analog to digital (A/D) converters in telephone systems is typically 8,000 samples per second. This number was chosen because of the relatively narrow bandwidth of a telephone system, 300 - 3,400 Hz, and because of the speed limitations of digital signal processing (DSP) devices. At 8,000 samples per second, the samples are separated by 125 microseconds and a 3.4 kilohertz signal is sampled only 2.3 times per cycle. This is not particularly good resolution. In order to increase resolution, one must increase the number of samples, which causes a corresponding increase in the number of storage sites. The number of storage sites is limited by the cost of manufacturing suitable integrated circuits and the complexity of addressing the sites in real time. It is desired to have echo canceling apparatus that is both effective and compact in order to fit with handsets, speaker phones, cellular telephones, and the like.
- the signals are not converted to digital data, which simplifies the circuitry.
- the storage time for the samples is presently limited by the characteristics of the storage node to approximately one half second without some sort of refreshing. For longer storage times, A/D conversion and memory storage are necessary.
- a large number of storage sites adversely affects the time for the system to lock onto the delay, referred to herein as convergence.
- convergence In a constantly changing environment, such as a telephone, system delays can change during a call and acoustic delays can change during a call because a person moves about a room.
- the settings for an echo canceling circuit are not changed during a call, largely due to a long convergence time.
- Another object of the invention is to provide a high resolution delay line using relatively few storage elements or delay elements. Another object of the invention is to provide a high resolution delay line that enables a system incorporating the delay line to converge quickly.
- a further object of the invention is to provide a high resolution delay line capable of delaying a signal for one second or more.
- Another object of the invention is to provide a high resolution delay line that can be implemented in either analog form, digital form, or a mixture of the two.
- a further object of the invention is to provide improved apparatus for canceling acoustic echoes and electrical echoes in telephone apparatus. Another object of the invention is to provide echo canceling apparatus that converges quickly on the echo.
- a further object of the invention is to provide acoustic echo canceling apparatus capable of delaying a signal for one second or more.
- Another object of the invention is to provide echo canceling apparatus that can match phase within less than one degree using relatively few delay elements.
- a further object of the invention is to provide echo cancellation apparatus that can adjust to changes in echo during a telephone call.
- a high resolution delay line includes a coarse delay and a fine delay, wherein the total fine delay that is equal to or greater than half the smallest interval of the coarse delay.
- Each delay can be implemented in analog or digital form and the delay line can be implemented with one portion in analog form and the other portion in digital form.
- the digital delay can provide a delay upward of 1,500 milliseconds.
- the fine delay provides a resolution of ten microseconds or less.
- a transmitted signal is coupled through a coarse delay and a fine delay to one input of a correlator. Another input of the correlator is coupled to a received signal. The delays are adjusted for maximum correlation and the output of the fine delay is subtracted from the received signal to reduce or eliminate an echo.
- the delays operate by sampling the signal and storing the samples at successive storage sites.
- the storage sites are read a predetermined time later, producing the delay.
- the read operation for the coarse echo includes three readings from separate sites and using correlation products to indicate the magnitude and direction for changing the delay.
- FIG. 1 illustrates acoustic echo and electrical echo in a telephone system
- FIG. 2 is a diagram of a portion of a telephone including echo canceling circuitry constructed in accordance with the invention
- FIG. 3 schematically illustrates the operation of a system constructed in accordance with the invention
- FIG. 4 illustrates the operation of the invention upon a sinusoidal signal
- FIG. 5 is a schematic of an analog delay line constructed in accordance with the invention.
- FIG. 6 is a block diagram of a digital delay line constructed in accordance with the invention
- FIG. 7 illustrates a system employing the invention to measure an unknown delay
- FIG. 8 illustrates measuring delay in accordance with another aspect of the invention.
- FIG. 9 is an alternative embodiment of FIG. 7.
- block 10 represents a speaker phone including microphone 11 for converting sounds into electrical signals and loudspeaker 12 for converting electrical signals into sounds. As indicated by dashed arrow 14, some sound is coupled from loudspeaker 12 to microphone 11, creating an echo. If there were sufficient coupling between loud speaker 12 and microphone 11, the system would oscillate.
- FIG. 2 is a block diagram of an echo canceling circuit constructed in accordance with the invention.
- the strongest signal coupled from output port 21 to input port 22 is perceived as an echo and is removed before the signal is coupled to a telephone network by output port 23.
- coarse delay 25 and fine delay 26 combine to provide a high resolution measurement of the time required for an original sound to leave output port 21 and arrive at input port 22.
- the signal from fine delay 26 and the composite signal from input port 22 are compared in correlator 27.
- Coarse delay 25 is adjusted for maximum correlation, as indicated by dashed line 28.
- Fine delay 26 is then adjusted, as indicated by dashed line 29, to increase correlation even more.
- correlator There are several types of correlator that can be used for implementing the invention.
- the most complicated correlator is a full multiplier circuit.
- the simplest correlator is a gate for selectively passing or blocking a signal.
- a circuit of intermediate complexity is a binary phase shift modulator. This circuit reverses the polarity of a first signal in accordance with a second signal.
- the correlation product provides both magnitude and direction information for adjusting the amount of delay. For the digital delay devices in particular, adjusting the delay is simply changing an offset for a pointer to memory addresses.
- the operation of coarse delay 25 is illustrated in FIG. 3.
- Memory 31, which can be analog or digital, includes a plurality of storage sites that are written by suitable means, represented by arrow 32.
- arrow 32 moves in the direction indicated to address memory 31 sequentially and repeatedly.
- the data is read by suitable apparatus following arrow 32, thereby introducing a delay into the signal from memory 31.
- the delay can be considerable, in excess of 500 milliseconds.
- memory 31 need only store 48,000 bits of data (48,000 storage sites, preferably addressed as words containing several bits) for one half second of data.
- Such memory is readily available and can easily fit into a cellular telephone, for example.
- only 4,000 storage sites are needed for memory 31.
- the number of storage sites between the write pointer and the read pointer is directly proportional to delay, represented as delta (d) in FIG. 3.
- three storage sites are read simultaneously. The three sites need not be consecutive but the second site is preferably midway between the first site and the third site.
- Signal 40 which can have any waveform, is sampled and written to memory at a time indicated by pointer 41.
- the signal is later read at times indicated by pointers 43, 44, and 45.
- the three signals are correlated with the signal from input port 22 (FIG. 2) to produce correlation products that indicate in which direction to adjust the delay. If, for example, the signal from pointer 43 has the highest correlation, then the delay is increased (greater separation from write pointer 41) until the highest correlation is obtained at pointer 44.
- the delayed signal is being read as the pointers move from left to right, as indicated by dashed line 35 in FIG. 3 and correlation may take place over several cycles of the signal from input port 22 (FIG. 2). In fact, with a coarse delay and a fine delay, convergence takes place in fifty milliseconds or less (within one hundred seventy cycles of a 3,400 Hz signal). Systems of the prior art converge in 500- 3,000 milliseconds.
- FIG. 5 illustrates an analog implementation of delay line 31 (FIG. 3).
- Memory 50 includes a plurality of substantially identical storage sites, such as sites 51, 52, 53, and 54, connected in parallel to input 56.
- Input 56 corresponds to input port 22 (FIG. 2) or may be coupled to input port 22 by intermediate buffers, filters, and the like.
- Storage site 52 includes storage node 61 coupled to input 56 by write gate 62.
- Storage node 61 is preferably the gate of an isolated FET (field effect transistor) that exhibits a capacitance relative to ground or common. The amplitude of the input signal is stored on node 61 during the moment that gate 62 is open.
- Node 61 is coupled through source follower 63 to read gates 65, 66, and 67. These read gates are never open simultaneously, although read gates 58, 66, and 59 may be open simultaneously.
- a preferred embodiment of the invention includes differential voltages for improved performance. Thus, there are actually twice as many storage sites, one half for the signal and one half for the inverted signal. In a read operation, the difference in voltage between node 61 and the corresponding opposite node is read.
- FIG. 7 illustrates a digital implementation of delay line 25 (FIG. 2).
- Memory 70 includes a plurality of storage sites, such as sites 71, 72, 73, and 74. Each site has a unique address and includes a plurality of bits, as determined by the construction of the particular integrated circuit. Preferably, each "word" or group of bits corresponds to the resolution of the A/D converter used for writing data, e.g. twelve bits. The data is preferably stored in sequential addresses but need not be.
- A/D converter 77 is coupled to input port 22 (FIG. 2) by buffers, filters, and the like. An input signal is sampled and the amplitude of the sample is converted into a digital number that is stored in memory 70, e.g. at site 74. Data is read in the same order in which it was stored. As with the analog version, the number of sites between the read pointer and the write pointer determines the delay. The actual amount of delay, in seconds, depends also upon the clock rate.
- Fine delay 26 (FIG. 2) is constructed and operated in the same manner as coarse delay 25, with two exceptions.
- the sample rate is much higher, 100 kHz to 1 MHz or more, and there is only one read line, not three.
- the fine delay is scanned from end to end while monitoring the correlation coefficient for maximum correlation.
- the output from fine delay 26 is coupled through amplitude correction circuit 80 to an inverting input of summing circuit 81.
- Amplitude correction circuit 80 adjusts the amplitude of the artificially delayed signal to match that at port 22.
- Port 22 is coupled to a non-inverting input of summing circuit 81, wherein the delayed signal is subtracted from the composite signal from port 22, thereby reducing or eliminating the acoustic echo.
- Amplitude correction circuit can include an amplitude correlation loop or other means for adjusting amplitude.
- coarse delay 25 operated at 8,000 Hz. and stored 4,000 samples (500 millisecond maximum delay).
- Fine delay 26 operated at 800,000 Hz and stored 400 samples (0.5 millisecond maximum delay). Very little additional storage is required to provide the fine delay.
- the minimum coarse delay increment 0.125 milliseconds, is less than the total fine delay.
- the fine delay can divide each coarse delay increment into one hundred smaller periods, with overlap at each end to ensure continuity.
- the total fine delay is preferably equal to or greater than one half the minimum coarse delay increment.
- Other combinations of sample rates can provide a wide range of delays and resolutions and, most importantly, can provide delays as long as 1.5 seconds or more at a resolution of tens of microseconds or less. This enables one to match phases to within less than one degree at 3,400 Hz. Further, one can combine digital coarse delay with an analog fine delay to provide a relatively easily implemented, inexpensive, yet precise system.
- Correlator 83 receives the signal from the switched network on input port 84 and compares that signal with the signal artificially delayed by coarse delay 85 and fine delay 86.
- Coarse delay 85 is constructed in the same manner as coarse delay 25 and fine delay 86 is constructed in the same manner as fine delay 26.
- the amplitude of the phase matched signal is then adjusted in amplitude correction circuit 88.
- Electronic echoes are removed from the composite signal on input port 84 by summing circuit 89.
- FIG. 7 illustrates a preferred embodiment of the invention in which input 90 is coupled to a first channel including coarse delay 91 and fine delay 92 and to a second channel including unknown delay 93.
- the signals from fine delay 92 and unknown delay 93 are compared in correlator 94 and the coarse delay is adjusted for maximum correlation. The fine delay is then adjusted to increase correlation further.
- FIGS. 8 and 9 are alternative embodiments of FIG. 7 and highlight additional aspects of the invention.
- the locations of the coarse delay and the fine delay are switched as compared to FIG. 7.
- this change should have no effect on the operation of the invention.
- the effect depends on the nature of the filter preceding the fine delay. If a clocked or switched filter is being used, such a filter should operate at the same frequency as fine delay 12, 100 kHz to 1 MHz or more. Such a filter is quite expensive and difficult to make.
- fine delay 12 should follow coarse delay 11.
- FIGS. 7 and 8 have an advantage in that the channel with the unknown delay has a continuous signal, as opposed to a sampled signal, and the correlation is more accurate.
- the channel with the known delay can be analog or digital as desired.
- the signals in both channels are sampled and these advantages are not obtained.
- the system illustrated in FIG. 9 has an additional deficiency in that any adjustment in delay must propagate through the unknown delay before correlation. This can significantly slow convergence.
- the embodiment of FIG. 7 is preferred.
- the invention thus provides an improved apparatus for canceling acoustic echoes and electrical echoes in telephone apparatus.
- the circuit converges quickly to provide echo cancellation apparatus that converges quickly on the echo despite being able to resolve a delay of less than one degree at 3,400 kHz.
- the echo canceling apparatus of this invention is capable of delaying a signal for one second or more and can adjust to changes in echo during a telephone call.
- the composite signal can be broken into bands and each band treated as shown in FIG. 2.
- the echo can be a replica of any original sound, not just speech.
- the number of storage sites, analog or digital, can be adjusted to suit a particular application.
- the period between write and read determines delay, not the frequency of the shift clock input as in a shift register.
- correlator There are several types of correlator that can be used for implementing the invention. The most complicated correlator is a full multiplier circuit. The simplest correlator is a gate for selectively passing or blocking a signal. A circuit of intermediate complexity is a binary phase shift modulator. This circuit reverses the polarity of a first signal in accordance with a second signal.
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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EP00960172A EP1197060A1 (en) | 1999-07-23 | 2000-07-20 | Acoustic and electronic echo cancellation using high resolution delay line |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US09/360,211 | 1999-07-23 | ||
US09/360,211 US6421443B1 (en) | 1999-07-23 | 1999-07-23 | Acoustic and electronic echo cancellation |
US09/361,014 | 1999-07-23 | ||
US09/361,014 US6166573A (en) | 1999-07-23 | 1999-07-23 | High resolution delay line |
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WO2001008380A1 true WO2001008380A1 (en) | 2001-02-01 |
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PCT/US2000/040441 WO2001008380A1 (en) | 1999-07-23 | 2000-07-20 | Acoustic and electronic echo cancellation using high resolution delay line |
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WO (1) | WO2001008380A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4764955A (en) * | 1985-10-30 | 1988-08-16 | International Business Machines Corp. | Process for determining an echo path flat delay and echo canceler using said process |
US5657384A (en) * | 1995-03-10 | 1997-08-12 | Tandy Corporation | Full duplex speakerphone |
US5737410A (en) * | 1993-12-23 | 1998-04-07 | Nokia Telecommunication Oy | Method for determining the location of echo in an echo canceller |
-
2000
- 2000-07-20 EP EP00960172A patent/EP1197060A1/en not_active Withdrawn
- 2000-07-20 WO PCT/US2000/040441 patent/WO2001008380A1/en not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4764955A (en) * | 1985-10-30 | 1988-08-16 | International Business Machines Corp. | Process for determining an echo path flat delay and echo canceler using said process |
US5737410A (en) * | 1993-12-23 | 1998-04-07 | Nokia Telecommunication Oy | Method for determining the location of echo in an echo canceller |
US5657384A (en) * | 1995-03-10 | 1997-08-12 | Tandy Corporation | Full duplex speakerphone |
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