JPH03109828A - Method and instrument for measuring flat delay length, echo canceller and telephone set terminal - Google Patents

Abstract

PURPOSE:To attain accurate measurement even in calling by inputting plural sinusoidal wave signals in mutually prime frequency relation to the input section of an echo path, detecting the signals at the output section of the echo path and measuring the flat delay length depending on the time difference. CONSTITUTION:A means 7 generating two sinusoidal wave signals in prime frequency relation to each other is provided on the input of an echo path and a means 8 detecting the two sinusoidal wave signals is provided on the output of the echo path and the flat delay length of the echo path is measured by a flat delay length measuring circuit 9 depending on the time difference between a generated signal and a detected signal. Thus, the length is detected even in calling without giving any unpleasant feeling to talkers, no calculation processing is required, and the method and instrument for measuring the flat delay length capable of measuring the flat delay length with inexpensive hardware constitution are realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for measuring the flat delay length of a telephone transmission line, and a method for measuring the echo of the telephone transmission line constructed based on the flat delay length obtained by this measuring method. The present invention relates to an echo canceling device for canceling sound and a telephone terminal.

[Conventional technology]

Voice transmission on a telephone line is carried out by a circuit network consisting of a two-wire bidirectional line and a four-wire line consisting of a set of unidirectional lines. The connection between the 2-wire and 4-wire lines is made by a hybrid transformer or high 1/lid conversion circuit.

However, it is difficult for these to operate with impedance matching over the entire frequency band, so
An echo is produced at the junction of the 2-wire and 4-wire lines.

Also, in the unidirectional lines for sending and receiving calls in IE telephone terminals, wrap-around echoes occur due to acoustic coupling from the transmitter to the receiver. In particular, hands-free telephone terminals that use microphones and speakers cause a great reaction.

As a result, a portion of the audio signal on one unidirectional line is sent back to the speaker through the other unidirectional line. In other words, a partial loop of the signal is formed in the circuit network, and if the loop gain exceeds 1, it will cause howling, and if it is less than 1, it will cause noise interference.

In short-distance calls or when the acoustic path is short, the delay between the speech from the speaker's mouth and the feedback to the ear is so short that the acoustic sound is unnoticeable and poses no particular problem. However, long-distance calls, such as calls via communications satellites or hands-free calls in conference rooms (conference calls), result in large delays between the voice signal and the corresponding echoes. It has a big impact on the feel of the call.

Therefore, these echoes must be removed.

Various methods for removing echo sounds have already been proposed.

. These are broadly classified into two types. One method is to suppress reverberant sounds, and the other is to eliminate reverberant sounds.

The former method compares the energy levels on a pair of unidirectional lines and controls switches provided on each line in a complementary manner. In other words, the system automatically switches between sending and receiving calls based on a comparison of energy levels. In principle, with this method, deterioration in speech quality (cutting off the beginnings and endings of words) is unavoidable.

The latter method uses a digital filter to create a replica of the echo from the signal on the - unidirectional line, and subtracts it from the signal disturbed by the echo on the other unidirectional line, thereby canceling the echo. This method is more effective and has higher quality than the former, but the hardware scale is large. This is due to the following reasons.

To reproduce the echo, it is necessary to adjust the tap coefficients of the digital filter by y4 using the signal on the unidirectional line. The impulse response of this filter must be the sum of the echo path responses.

In other words, the delay line of the filter has the same length as the echo path (
(meaning of delay time). This requires adjusting a large number of tap coefficients, and for this,
High computational ability is required.

For example, like an international phone call, the echo path is 400m5 long.
Assuming that the audio signal is sampled at 8 kHz, the tap coefficients of this digital filter are 3200,
Approximately 10,000 times/12 for filter calculation and coefficient adjustment
A multiplication of 5 μS is required. The scale of hardware required for this calculation is enormous.

Incidentally, the impulse response of the echo path can be approximated by a flat delay followed by a smoke impulse response such as a hybrid transformer. In particular, in international links, most of the impulse response length is due to radio wave propagation delay between terrestrial satellites, which is a flat delay.

If this flat delay is precisely adjusted, it can significantly reduce the computational power required for echo cancellers in audio transmission networks. For example, the impulse response length of a hybrid transformer is approximately 6 ms long, which is 400 ms long.
It is only one side root degree of m5 length. At this time, the number of tap coefficients of the digital filter is a mallet.

From the above background, the flat delay length
Various methods have been proposed for estimating len-gth).

For example, as described in Japanese Patent Application Laid-Open No. 62-t16025, before a voice call starts, a training signal is sent out, the impulse response of the echo path is estimated, the maximum value of this sample value series is found, and a flat A method for estimating delay length has been proposed. For this training signal, Gaussian noise or the like consisting of all band components is used to estimate the impulse response.

Although the above method has many advantages, it also has the following problems. Firstly, it is necessary to send and monitor a harsh training signal prior to the call, albeit for a short time.Secondly, estimating the impulse response requires high computational power and memory. It is.

As another method, a method of estimating a flat delay length from a cross-correlation value of energy data of an audio signal has been proposed, for example, as described in Japanese Patent Laid-Open No. 107533/1983. Although this is an improvement over the previously described methods in that it does not require special signaling and does not require as much computational power, it still requires cross-correlation calculations and the hardware cost for this is still high. expensive.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into account the discomfort of the caller or the increase in hardware cost, resulting in a problem of low quality and high cost.

The purpose of the present invention is to enable detection even during a call without causing discomfort to the caller, and to be able to measure flat delay length without the need for calculation processing and with an inexpensive hardware configuration. An object of the present invention is to provide a method and device for measuring flat delay length.

Another object of the present invention is an echo canceler capable of adjusting the flat delay length obtained by the above detection method, reducing the computational power required for the echo canceler, reducing the hardware scale thereof, and lowering the price. and to provide telephone terminals.

[Means to solve the problem]

In order to achieve the above object, the present invention provides means for generating two temporary sinusoidal signals having mutually prime frequency relationships at the input of an echo path, and means for detecting the two temporary sinusoidal signals at the output of the echo path. and is configured such that the time difference between the generated signal and the detected signal measures the flat delay length of the echo path.

To achieve the above and other objects, the present invention provides a filter delay line of an adaptive digital filter that creates an echo replica with a fixed delay length delay line having taps and coefficients and a flat delay in an echo cancellation device. It is constructed on a delay line whose delay length is controlled by the flat delay length of the echo path measured by the signal generating means and the detecting means.

In the present invention, it is preferable that the sinusoidal temporary signal input to the echo path is a burst signal. As this burst signal, for example, one of the DTMF signals in a telephone terminal can be used.

Further, a plurality of the means for generating the temporary sine signal and the means for detecting the sine wave may be provided. In this case, it is possible to generate a plurality of types of burst signals a plurality of times and statistically process the flat delay length obtained each time the burst signal is generated, and use a value as the flat delay length of the echo path.

[Effect]

The two-frequency signal generating means inputs two temporary sinusoidal signals having mutually prime frequencies to the echo path, for example, as a burst signal. The burst signal reaches the two-frequency signal detection means with a delay of a flat delay length of the echo path. The two-frequency signal detection means detects this. The flat delay length of the echo path is obtained by the time difference between the time of signal generation and the time of detection. Since the audio signal has a harmonic structure with the pitch frequency as the fundamental wave, it does not affect the detection of two frequencies having a mutually prime frequency relationship. Therefore, according to this method, an accurate flat delay length can be obtained even during a voice call.

The adaptive digital filter in the echo canceler consists of a fixed delay length delay line with tap coefficients and a flat delay line with the flat delay length obtained by the above method, and produces a signal that exactly replicates the entire response of the echo path. create. This is then subtracted from the echo signal to eliminate the echo signal. The calculation for echo signal replication is only for the fixed delay length with tap coefficients, so compared to the case where all delay lines have tap coefficients, a significant reduction in calculation power and hardware size can be achieved. .

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Prior to explaining the embodiment, a telephone line network to which the embodiment is applied will be explained.

FIG. 2 is a diagram showing the current landline telephone network.

The subscriber telephone terminal device 1 and the opposing subscriber telephone terminal device 2 are as follows:
The subscriber lines L1 and L2 are connected via the terrestrial switched network RPTN, and calls are made.

Each of the subscriber telephone leakage devices I and 2 has a pair of transmitters Tl, T2 and a receiver R1, R2. Sending and receiving signals are transmitted through a pair of unidirectional lines TL, each forming a 2-wire line within the terminal, and both forming a 4-wire line.
I, RLI and TL2. It flows through Rb2. these are,
The hybrid transformers H1 and 'H2 in the terminal convert the 4-wire line into a 2-wire line, and the subscriber lines L1 and
2J are connected.

The subscriber lines L1 and L2, which are two-wire (bidirectional) lines, are connected to hybrid transformers HYBI and )I of a local exchange (not shown), which is the lowest layer in the terrestrial switched network RPTN.
It is converted to a 4-wire line at YB2.

Within the terrestrial switched network RPTN, transmitting and receiving signals are each
It flows through a pair of unidirectional lines Ti and T2, both of which form a four-wire line. For international calls, an international line (not shown) is inserted into the terrestrial switched network RPTN.

FIG. 3 is a diagram showing the current car telephone network.

The mobile telephone terminal M 1 and the subscriber telephone terminal device 2, which corresponds to the mobile telephone terminal M, are connected via the mobile telephone line switching network MPTN, the land line switching network RPTN, and the subscriber line L2, and a telephone call is performed.

Car phone terminal M-I and car's 1-talk line switching network MPT
Base station MB 8 (corresponding to a local exchange), which is the lowest layer of N, has radios RAI and BRA, respectively. These radios RAI and BRA have two independent radio channels, and each transmits a transmitting/receiving signal.

The difference in Fig. 3 from Fig. 2 is that the car phone terminal M
There is no hybrid transformer in Station I, and the transmitting and receiving signals are transmitted from this terminal through the mobile telephone switched network MPTN to the hybrid transformer HYB2 at the local switching office at the lowest layer in the land switched network RPTN. It forms a two-track line,
A pair of unidirectional lines Tl (TLI) both forming a 4-wire line
, T2(R:[,1). The rest is the same as in FIG. 2.

L11 In Figures 2 and 3, the conversion from a 4-wire line to a 2-wire line or vice versa is performed using hybrid transformers H1 and R.
2, HYBl, )iYB2, and at this time, echoes occur due to impedance mismatch.

Now, let us consider the transmission of an audio signal from the transmitter T1.

In FIG. 2, most of the transmit signals are TLI.

T1. Flows on RL2, but part of it flows on Hl, HYBI
, HYB2. Echoed at R2, T2. Flows on RLI.

2.Here, we ignore the reverberations caused by the acoustic coupling between the transmitter and the receiver. However, it should be noted that hands-free telephone terminals that use microphones and speakers have a huge impact and cannot be ignored. The impulse response of the combined echo path between the transmitter T1 and the receiver R1 in this case (FIG. 2) is shown in the fourth factor.

In FIG. 2, the unidirectional line TLI in the terminal.

The line lengths of the RLI and the subscriber lines Ll and R2 are short (the average length of the subscriber lines is 7 mm), and the propagation delay of electrical signals there can be ignored. Therefore, as shown in Fig. 4, an impulse response a1 of the mixed transfer function of transformers H1 and I (YBl) appears at first.This causes the echo sound, that is, the sound from the speaker's mouth and the sound from the speaker's ear to the ear. The feedback delay is as short as about 6ms, so it is not noticeable, so it is not a problem.In fact, it acts as a sidetone, which helps when speaking when you cover your ears with a handset.

Unidirectional line TI in the terrestrial switched network RPTN.

In the case of long-distance or international calls, T2 is several thousand to tens of thousands of meters long, and the propagation delay of electrical signals here can reach several hundreds of meters. This results in a flat delay shown as bl in FIG.

Then, as at the beginning, the impulse response a2 of the mixed transfer function of transformer I (YB2 and R2 appears. The resulting echo, i.e. the delay between the speech from the speaker's mouth and the feedback to the ear, is , from several tens of mB to several hundred m8, and significantly degrades speech quality as echo interference.

The impulse response of the integrated echo path between the transmitter T1 and the receiver R1 in FIG. 3 is shown in the fifth factor.

Similar to the explanation regarding FIG. 4, a flat delay b1 of several hundred mB due to the unidirectional line TI, T2 from the terminal to the mobile phone switched network MPTN, the terrestrial switched network RPTN, and the mixture of transformers HYB 2 and R2. The impulse response is divided into an impulse response a2 based on the transfer function.

The resulting acoustic sound from several tens of m8 to several hundred ma greatly degrades speech quality as a reverberant disturbance, similar to the explanation in FIG.

FIG. 6 shows a conventional echo canceling device for canceling echoes.

In FIG. 6, 1 is a hybrid transformer and 2 is an echo canceller. The echo canceller 2 includes a digital filter 3, a tap coefficient setting circuit 4, and a subtracter 5, and also includes analog/digital (A/D) converters 201 and 203, and a digital/analog (D/A' ) transducers 202 and 204 are connected.

The hybrid transformer 1 is assumed to have an impulse response equivalent to that shown in FIG. 4 or 5.

A digital filter 3 is connected to the output path and supplied with digital signal samples x (n). The tap coefficient h (k) of the filter 3 is set by the tap coefficient setting circuit 4 and the echo signal y (t
) must be generated a signal y (n) that is an exact replica of the digital representation y (n) of y (n).

The output of this filter 3 is subtracted by a subtracter 5, and the echo signal y
Delete (n).

The tap coefficient setting during operation is usually based on the digital signal sample x (n) and the error signal e which is the output signal of the subtracter.
(n) using the steepest descent method, and is performed over a period of several tens to hundreds of m8 to obtain an accurate replica. These settings must be updated from time to time to keep up with changes in line connection conditions.

As explained earlier, the filter 3 requires a large number of taps and their coefficients since it must perfectly match the echo path. The actual operation of filter 3 is sample x
(n) is multiplied by each tap coefficient h (k) and the results are added by a program-controlled processor.

The filter 3, being a perfect replica generator, must have an impulse response that perfectly matches the impulse response of the echo path. The impulse response of the echo path consists of a flat delay and a hybrid transformer impulse response, as shown in FIGS. 4 and 5.

The echo replicator must also give the same total response. However, if the impulse response is 400 m5 long and the sampling frequency is 8 kHz, the taps and coefficients are 3.
200, the amount of calculation work becomes considerably large, and it becomes impossible to perform all the calculations within the predetermined time (125μ8).

A way to reduce this processing load is to effectively utilize the flat delay portions shown in FIGS. 4 and 5.

The flat delay portion corresponds to a tap coefficient of zero, and there is no need to perform multiplication and addition in this portion. Therefore, by using flat delay lines before and after the filter shown in FIG. 6, the processing load can be reduced.

The problem here is how to adjust the length of the flat delay line. In other words, Figure 4.

How to measure the flat delay length in FIG. 5, and how to adjust the length of the flat delay line based on this result.

The present invention solves these problems, and examples thereof will be described in detail below.

FIG. 1 is a diagram illustrating an embodiment for a reverberation path with the impulse response shown in FIG.

This embodiment describes a flat delay length measuring device 100 that detects a flat delay length of a line, and a flat delay length measuring device 100 that detects a flat delay length of a line.
The present invention includes an echo canceling device 2 that performs echo canceling using the flat delay length detected at .

The echo canceling device 2 includes a digital filter 3, a tap coefficient setting circuit 4, a subtracter 5, and a variable flat delay line 6, and also includes A/D converters 201 and 203, and a D/A
It is configured by connecting converters 202 and 204.

Here, the variable flat delay line 6 is, for example, the eleventh delay line described later.
It is constructed as shown in the figure, and the delay length can be varied in accordance with the flat delay length sent from the flat delay length hand device 100, giving a flat delay. Further, other components are the same as those shown in FIG. 6 described above. Therefore, the same reference numerals are given and the description will not be repeated.

The flat delay length measurement device 100 includes a two-frequency signal generation circuit 7 that generates two temporary sinusoidal signals having mutually prime frequency relationships.
and a two-frequency signal detection circuit 8 that detects two temporary sinusoidal signals generated by the two-frequency signal generation circuit 7, and measures the flat delay length using the two-frequency signal generation circuit 7 and the two-frequency signal detection circuit 8, It is configured to include a flat delay length measurement circuit 9 that outputs the result of the variable flat delay line 6#, a measurement control circuit 10 that instructs the flat delay length measurement circuit 9 to start measurement, etc., and a mixing circuit 11.

This flat delay length measurement device 100 has the following characteristics for the echo path:
A composite signal obtained by mixing two temporary sinusoidal signals having relatively prime frequency relationships is input in a burst manner, and the flat delay length is directly measured from the delay time.

FIG. 7 is a diagram showing an embodiment of the two-frequency signal generating circuit 7. In FIG.

This two-frequency signal generation circuit 7 includes a first frequency oscillation circuit 70
1, a second frequency oscillation circuit 702, a mixing circuit 703, and a gate circuit 704.

The first and second frequency oscillation circuits 701 and 702 are
Sine temporary signals S1 and & having a relatively prime frequency relationship (ft and fl) are generated. These outputs are mixed in a mixing circuit 703 to become a two-frequency signal, which is gated in a gate circuit 704 by a gate signal input from a gate signal input terminal 705, and then output to a two-frequency signal output terminal 70.
6 is output as a burst signal.

FIG. 8 shows an embodiment of the dual frequency signal detection circuit 8.

The two-frequency signal detection circuit 8 includes a first frequency band-pass filter (BPF) 802, a second frequency band-pass filter (BPF) 803, a first frequency detection circuit 804, a second frequency detection circuit 805, and an AND circuit 806. It is composed of:

A signal input to the detection signal input terminal 801 is guided to first and second frequency band pass filters 802 and 803. These bandpass filters 802 and 80
3 is the frequency i1b and f which are in the frequency relationship of the mutual compound
, filter only nearby signals. The outputs of the first and second frequency bandpass filters 802 and 803 are output to first and second frequency detection circuits 804 and 805. Here, the sine temporary signals S8 and & are subjected to smooth detection to detect their presence.

These outputs are led to a 7nd circuit 806 and ANDed. This result is output from the detection signal output terminal 807 as a detection signal. In other words, it is output only when & and S exist simultaneously.

FIG. 9 shows an embodiment of the flat delay length measuring circuit 9.

The flat delay length measurement circuit 9 includes a counter 901, a clock signal generation circuit 902, a gate circuit 903, a counter register 904, and a timing circuit 906.

Counter 901 counts clock signals from clock signal generation circuit 902. A clock signal input to the counter 901 is gated at a certain time interval by a gate circuit 903. This time is the flat delay length, which will be explained later.

The count value of the counter 901 is read into the counter register 904 using a register read signal, and the value is output to the measurement result output terminal 905.

A timing circuit 906 generates various timing signals for measuring the flat delay length. This timing circuit 9
06 receives a start signal from the measurement control circuit 1o at a start signal input terminal 907, receives a detection signal from the dual frequency detection circuit 8 at a detection signal input terminal 908, and also receives a counter gate signal, a counter reset signal, and a register lead. In addition to outputting a signal, a signal output gate signal is output to a signal output gate signal output terminal 909.

The tenth factor shows a timing chart for flat delay length measurement. This will be explained below.

The square counter 901 is reset by a start signal from the measurement control circuit 10. Then, the signal output gate signal is sent to the two-frequency signal generation circuit 7, and the two-frequency signal is sent out in bursts to the echo path via the mixing circuit 11. At the same time, a counter gate signal is output and the gate circuit 90
3 is opened, a clock signal is input to the counter 901, and counting is started.

The burst two-frequency signal is delayed and input to the two-frequency signal detection circuit 8, where it is detected. timing circuit 9
06 detects the rising edge of the detection signal and stops outputting the counter gate signal, thereby stopping the counting of the counter 901. Then, with the register read signal, the counter count value is read into the counter register, and this value is output to the measurement result output terminal 905.

If the frequency of the clock signal is 8) kHz, the value obtained by multiplying this counter count value N by 125 μs becomes the flat delay length.

FIG. 11 shows an embodiment of the variable flat delay line 6. The variable flat delay line 6 includes a five-stage shift register 602, a data selector 603, and a decoder 605.

Sample data x (n) is input from a data input terminal 601 to a five-stage shift register 602 . The five-stage shift register 602 repeats data shifts at a constant clock frequency. Furthermore, each M stage (M=4 in the figure) has a data output, and this output is connected to a data selector 603, one of which is selected and output from a data output terminal 604. The decoder 605 has a counting input terminal 606
The flat delay length is input from .

If the data shift clock frequency of the shift register 602 is 8kHz, one stage of the shift register is 125μ.
corresponds to a flat delay of s. Therefore, data selector 60
If the data output selected in step 3 is the first one from the input side of the shift register, MX125μs1Pth, then %
PXMX has a data delay of 125 μS, ie, a flat delay line.

7 When the counter count value is N, the decoder 605
= Select the Pth data output and measure the flat delay length (
This results in a flat delay line equal to PXMX125μ8). Note that if N7M is not an integer, it may be rounded up to an integer value after the decimal point.

Of course, the value of L must be set in consideration of the maximum possible flat delay length.

Note that a variable flat delay line can also be created by configuring a ring buffer in RAM (random access memory) using a program, setting the read/write speed to 1 sample/125 μs, and manipulating this address pointer with the previous counter count value N. Obtainable. And in this case, 1
A flat delay line of 25 μs can be obtained.

In the example of FIG. 11, it is possible to obtain only a unit of MX125 μB. This is because the hardware of the data selector 603 and decoder 605 becomes large if each stage has a data output.

Now, as is well known, the audio signal flowing through the telephone @Renkinu is
It has a harmonic structure with the pitch frequency as the fundamental wave. Therefore, as in the present invention, one of the two temporary sine signals with relatively prime frequency relations is masked by the audio signal, but even when masked, there is a worry that the other temporary sine signal will always be masked. There isn't. Conversely, in the case of an audio signal, there is no detection signal output from the two-frequency signal detection circuit 8. In other words, according to the method of the present invention, it is possible to detect a flat delay length even if a voice signal is present (even during a call).

Furthermore, since the frequency component itself is detected, it is not affected by the transfer function of the echo path. For example, 697
Although the level and phase of the Hz temporary sinusoidal signal vary depending on the transfer function of the echo path, the frequency remains at 697 Hz.

FIG. 12 shows the structure of another embodiment of the present invention.

This embodiment is an embodiment for the echo path having an impulse response shown in FIG.
0 and an echo canceller 2.

The echo canceller [2 is the same as that shown in FIG. 1 described above, except that a digital filter 12 is added. Further, the flat delay length measuring device 100 is also the same as that shown in FIG. 1 described above. Therefore, the same components will be given the same reference numerals and the description will not be repeated here.

The digital filter 12 reproduces the echo caused by the impulse response of the 81 part shown in the fourth part.

Next, the operation of this embodiment will be explained.

The operation of the embodiment shown in the twelfth factor is essentially the same as that of the embodiment shown in FIG. 1, but the counter gate signal generated by the timing circuit 906 in the flat delay length measuring circuit 9 is different. FIG. 13 shows the timing chart of FIG. 12.

As shown in FIG. 13, a signal is input to the two-frequency signal detection circuit 8 at the same time as the two-frequency signal is sent out. This is a reverberant sound due to the impulse response of section 81 shown in FIG. The signal is then input again after a long flat delay. This is a reverberation sound due to the impulse response of the a2 portion.

The counter gate signal is generated from the first counter gate signal obtained by performing the logical product of the signal output gate signal and the first reverberant detection signal, and the second reverberant sound from the falling edge of the first reverberant detection signal. and a second counter gate signal up to the rising edge of the detection signal. The tail portion of the latter half of the human input to the two-frequency signal detection circuit 8 is a delay due to the impulse response a1, and this portion is handled by the digital filter 12, so the portion excluding this delay time is shown in FIG. This corresponds to the flat delay b1 of the impulse response shown. For this reason, the counter gate signal is divided into two parts as described above. Other operations are the same as those in FIG. 1, so explanations will be omitted.

Figure g14 shows the configuration of yet another embodiment of the present invention.

This embodiment differs from the embodiment shown in FIG.
The flat delay length measuring device 100 and the echo canceling device 2 are applied to the echo path caused by the acoustic coupling i between the speaker 14 and the speaker 14.

In the case of a reverberation path consisting of microphone 13 and speaker 14, the flat delay is the sound wave propagation delay due to the direct wave between microphone 13 and speaker 14. In particular, in hands-free telephone terminals such as conference telephone terminals in which microphones and speakers are installed at a long distance, this flat delay reaches several tens of milliseconds, and this flat delay leads to an increase in the hardware scale of the echo canceling device. This embodiment prevents this.

All other configurations and operations in this embodiment are the same as those in the embodiment shown in FIG.

Next, FIG. 15 shows the configuration of yet another embodiment of the present invention.

In FIG. 15, the same symbols as in FIG. 1 indicate the same parts.

This embodiment is configured to automatically correct the detection delay of the dual-frequency signal detection circuit 8, and a changeover switch 15 is used for this purpose.
is provided in the flat delay length measuring device 100. Note that the other configurations are the same as those of the embodiment shown in FIG. 1, so the same reference numerals are given and the explanation will be omitted.

2 Switch the input signal. This switching is performed by the measurement control circuit 10.
controlled by

The two-frequency signal detection circuit 8 has a time delay (
(time lag). Therefore, the flat delay length measurement is correct.
This delay has an effect, and there is a possibility that accurate measurement may not be possible.

In this embodiment, in order to prevent this, the changeover switch 1
5, the two-frequency signal detection circuit 8 is first connected to the output of the two-frequency signal generation circuit 7 and then to the output of the echo path so that the flat delay length measurement includes the time delay. I tried to avoid it.

FIG. 16 shows a timing chart of this embodiment.

The operation of this embodiment differs from the timing chart shown in FIG. 10 in the counter gate signal generated by the timing circuit 906. The counter gate signal is switched from the e side, that is, the rise of the detection signal when the two-frequency signal detection circuit 8 is connected to the output of the two-frequency signal generation circuit 7, to the f side, that is, the original echo path output side. is output until the rising edge of the detection signal when connected to

In the embodiment shown in FIG. 1, the counter gate signal is output from the rising edge of the signal output gate signal. According to such an operation, flat delay length measurement that is not affected by the detection delay of the two-frequency signal detection circuit 8 becomes possible.

FIG. 17 is a diagram showing the configuration of another embodiment of the present invention.

This embodiment is an application of the present invention to a hands-free car telephone terminal, and is a combination of an echo canceling device similar to that shown in the embodiment shown in FIG. 1 and a conventional echo canceling device 17. Therefore, only the feature points will be explained here, and the same components as those mentioned above will be explained.
The same reference numerals are used to omit the explanation.

The echo canceler 16 cancels the echo sound in the echo path consisting of a hybrid transformer, etc., and the echo canceler 17 cancels the echo sound in the echo path caused by sound going around from the speaker 14 to the microphone 13 (acoustic coupling). It works like that. Signals are transmitted between the two echo cancellers as sample values.

Further, a volume adjustment circuit 18 is arranged in the reception signal path between both devices. This adjusts the listening volume of the speaker 14 by multiplying the sample value by a predetermined value.

The reason why the volume adjustment circuit 18 is placed in this position is because the echo path gain (from the D/A converter to the A
This is to prevent the gain up to the /D converter from changing due to volume adjustment. If a volume adjustment circuit is inserted between the D/A converter and the speaker, the echo path gain will change due to the volume adjustment, and the echo cancellation ability (ER) of the echo cancellation device 17 will change.
LE) deteriorates.

In this example, a conventional configuration was used for the echo canceller [17], but in the case of a car phone, the distance between the microphone and the speaker is approximately 1 m, and the flat delay length due to this is approximately 3 m.
ms, and the effect of introducing a variable flat delay line is small. Of course, if the distance between the microphone and the speaker is long, such as in a conference telephone terminal, the embodiment shown in FIG. 14 should be applied to the echo canceling device 17. Other operations have been explained with reference to FIGS. 1 and 6, and will therefore be omitted here.

As described above, according to this embodiment, a low-cost hands-on IJ + car telephone terminal can be obtained.

In each of the embodiments described above, two-frequency signals having a relatively prime frequency relationship are used for simplicity, but the present invention
It is clear that the present invention is not limited to this, and that multi-frequency signals of three or more frequencies having a mutually prime frequency relationship may be used. However, in that case, the signal generation circuit 7
It is undeniable that the hardware scale of the detection circuit 8 increases proportionally.

Some telephone terminals have a so-called DTMF signal generator as a pushbutton (PB) dial signal generator. The two-frequency signals (697 Hz and 1209 Hz) corresponding to the number 1 of this generator, for example, have a mutually prime frequency relationship, and therefore can be used in the two-frequency signal generating circuit 7 of the present invention.

By utilizing this, it becomes possible to reduce the cost required for flat delay length measurement.

Although it has been mentioned that the dual frequency signal detection circuit 8 does not respond to audio signals, it may output a detection signal in response to noise on the line.

In the case of responding to noise, the counter gate signal ends at the rising edge of the detection signal as shown in the timing chart of FIG. 1θ, resulting in an error in measuring the flat delay length. In order to prevent this, taking advantage of the fact that the detection signal does not continue for a long time due to noise etc., a time filter (time dom-ain filter) is applied to the detection signal, for example, from the impulse response length (about 6m8) of the hybrid transformer. If the detection signal is too short, it may be ignored.

Alternatively, the duration of the detection signal is measured and compared to the signal length of the burst signal, i.e. the duration of the signal output gate signal (which is known as it is controlled by the timing circuit), and the difference is determined by a predetermined value (hybrid transformation If the impulse response length of the device is larger than the reference value, the measured flat delay length can be ignored and the measurement can be performed again.

Furthermore, in the above explanation, the flat delay length is measured using one two-frequency burst signal, and the variable flat delay line is controlled using this. It occurs multiple times at time intervals, the flat delay length is measured multiple times, these results are subjected to statistical processing, for example, the average value is calculated, and this value is used to control the variable flat delay line 6. Become something.

Furthermore, a plurality of two-frequency generation circuits 7 and two-frequency detection circuits 8 are prepared, a plurality of two-frequency burst signals are generated multiple times as described above, the flat delay length is measured multiple times, and the statistically processed values are used. Good too.

The measured flat delay length includes an error. Therefore, if the true flat delay length of the impulse response in FIG. 5 is DFLma, the measured flat delay length is DPI.

±α (α is the error). It is assumed that the length of the delay line of the digital filter 3 is such that a fixed ADFL sufficiently covers the impulse response a2 of the hybrid transformer.

Now, the measured flat delay length is DFL+α, and if the variable flat delay line is controlled with this value, the filter delay line of the adaptive digital filter will have a length D as shown in FIG.
FL+α flat delay line and length A that can set tap coefficients
It can be seen that the impulse response configured by the DFL delay line and replicated by the adaptive filter can only be that shown in 1ffl (b).

In other words, the impulse response shown by the broken line in the figure cannot be duplicated.
It is clear that the cancellation ability of the echo cancellation device is degraded.

This is an unavoidable risk even if the measured flat delay length is statistically processed to ensure accuracy.

The nineteenth doctor is a diagram showing the configuration of another embodiment of the present invention.

In FIG. 19, this embodiment uses the same echo canceling device 2 and flat delay length measuring device 10 as shown in FIG.
0, and the flat delay length measuring device 100 includes a statistical processing circuit 19, a predetermined value circuit 20, and a subtracter 21. Note that the other components are the first
Since it is the same as that shown in the figure, the explanation will be omitted.

The statistical processing circuit 19 stores the flat delay lengths measured a plurality of times in a memory, performs statistical processing on the flat delay lengths, for example, calculates the average fif X, and outputs it. The predetermined value circuit stores a predetermined value β. The subtracter 21 subtracts a predetermined value β from the average value Ma and outputs X−β to the variable flat delay line 6.

If β is set to a value larger than the possible error α, the replicated impulse response given in this embodiment can be as shown in FIG. 18(b). (x; DFL) In other words, a value shorter than the measured flat delay length is used to avoid the danger described above. In this case, it is necessary to allow a margin for the fixed delay line length ADFL of the digital filter 3 to compensate for the shorter length.

In this example, the case of multiple measurements is shown, but it is also effective to shorten the measured value (-β) and control the variable flat delay line even for one measurement. it is obvious.

In addition, although the predetermined value β is a predetermined fixed value, this value can be changed to β using, for example, the variance value σ2 obtained by statistical processing.
= 3σ may be used.

The other operations are the same as those in FIG. 1, so their explanation will be omitted.

As described above, according to this embodiment, it is possible to obtain an echo canceling device that has high echo canceling ability and is inexpensive.

FIG. 20 shows the configuration of another embodiment of the present invention.

In FIG. 20, this embodiment has the same echo canceling device 2 and flat delay long hand side device 100 as shown in FIG.
and a means for detecting an increase or decrease in the cancellation ability of the echo canceling device 2, that is, an increase in the amount of echo attenuation, and a variable flat delay line based on the detection result and the flat delay length measured by the flat delay length measuring device 100. and control means. Note that the other components are the same as those shown in the first figure.

In FIG. 20, the means for detecting the echo attenuation enhancement is as follows:
The power measurement circuit 22 includes a power measurement circuit 22, a power measurement circuit 22, and an ERI and E calculation circuit. The means for controlling the long, flat delay line consists of a flat delay length measuring circuit.

Power measurement circuits 22 and 23 connected before and after the subtractor 5 of the echo canceling device 2 measure the power of the input signal and the output signal of the echo signal to the device, respectively. The cancellation ability of the echo cancellation device 2 is given by the ratio P+/R of the measured power P of the power measuring circuit 22 and the measured power P of the measuring circuit n. This is generally referred to as echo attenuation enhancement.
n Lama Enhancement: ERL
E). The ERL, E calculation circuit 24 calculates this ER
Calculate the LE value.

Based on this ERLE value, the flat delay length adjustment circuit 25
The flat delay length obtained by the flat delay length measurement circuit 9 is adjusted, corrected, and output to the variable flat delay line 6.

If the measured flat delay length includes an error, as described in the explanation of the trick in Figure 18, the echo cancellation ability will be reduced. In other words, the ERLE value is small. Therefore, this ERL
The gist of this embodiment is to finely adjust the measured flat delay length so that the E value increases.

FIG. 21 shows an embodiment of the flat delay length adjustment circuit 25.

In FIG. 21, 251 is a changeover switch, 252 is a buffer register, 253 is a force σ calculator, 254 is a selection switch, 255 is a cut width circuit, 256 is a cut width selection control circuit, 257 is an increase/decrease detection circuit, and 258 is an ERLE. It is a value register.

The operation of the embodiment shown in FIG. 4 will be explained based on FIG. 21.

In addition, the measured flat delay length is temporarily stored in the buffer register 252 through the changeover switch 251, and the variable flat delay line 6 is controlled by this flat delay length, and the echo canceling device 2 is operated. The ERLE value at this time is stored in the ERLE value register 258.

Next, the kizami width selection control circuit 256 selects the selection switch 2.
54 to select one of the increment widths Δ (for example, a counter value of ±100 or zero corresponding to ±1.25 m5) stored in the increment width circuit 255 (excluding zero);
Input the adder 253 as . Now, plus width +Δ
Suppose you select

Adder 253 adds 10 to the flat delay length of the buffer register.
The value with 0 added is input into the buffer register again. Then, the increase/decrease detection circuit 257 compares the ERLE value at this time with the previously stored ERLE value, and outputs information on whether the ERLE value increases, decreases, or remains unchanged to the kizami width selection control circuit 256.

The incision width selection control circuit 256 selects the incision width value again from this result. For example, if the ERLE value decreases, -Δ is selected, and if it increases, 10Δ is selected again to update the flat delay length of the buffer register.

By repeating the above operations and converging, the optimal (ER
It is possible to obtain a flat delay length in which the LE value is maximum.

As described above, in this embodiment, the initially measured flat delay length is sequentially updated by a certain increment width using the increase/decrease in the ERLE value as a guide to obtain the optimal flat delay length.

The embodiments of the present invention have been described above, but the present invention includes
The present invention is not limited to these examples. For example, it is possible to combine the features of each embodiment.

〔Effect of the invention〕

Since the present invention is configured as described above, it produces the effects described below.

(1) Even during a call, the flat delay length of the echo path can be accurately measured.

(2) The measurement can be configured with simple hardware and is economical. Furthermore, if the hardware is a DTMF signal, which is a dial signal in a telephone terminal, the economic effect will be even greater.

(3) The filter extension line of the adaptive digital filter of the echo canceller is configured with a fixed delay length delay line having a tap coefficient and a variable flat delay line controlled by the flat delay length measured by the present invention. This makes it possible to achieve a significant reduction in computing power and hardware scale, making it economical.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing the current landline telephone line network, Fig. 3 is a block diagram showing the current car telephone line network, and Fig. 4 and M5 are waveform diagrams showing impulse responses, FIG. 6 is a block diagram showing a conventional echo canceller, FIG. 7 is a block diagram showing an embodiment of a two-frequency signal generation circuit, and FIG. 8 is a two-frequency signal FIG. 9 is a block diagram showing an embodiment of the detection circuit; FIG. 9 is a block diagram showing an embodiment of the flat delay length measuring circuit;
0 is a timing chart showing signals in the embodiment of FIG. 1, FIG. 11 is a block diagram showing an embodiment of the variable flat delay line, and FIG. 12 is a block diagram showing the configuration of another embodiment of the present invention. Figure 13 is a timing chart showing the signals in the embodiment of Figure 12, Figure 14 is a block diagram showing the configuration of another embodiment of the present invention, and Figure 15 is another embodiment of the present invention. A block diagram showing the configuration of the
A timing chart showing signals in the embodiment of FIG. 5,
FIG. 17 is a block diagram showing the configuration of another embodiment of the present invention, FIG. 18 is a waveform diagram showing an impulse response, and FIG. 19 is a block diagram showing the configuration of another embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention, and FIG. 21 is a block diagram showing an embodiment of a flat delay length adjustment circuit. 2... Echo cancellation device 3... Digital filter 4... Tap coefficient setting circuit 5... Subtractor 6... Variable flat delay line 7
... Two-frequency signal generation circuit 8 ... Two-frequency signal detection circuit 9 ... Flat delay length measurement circuit 15 ... Changeover switch 20 ... Predetermined value circuit 25 ... Flat delay length adjustment circuit 100 ...・Flat delay length measuring device 19...Statistical processing circuit 21...Subtractor 7

Claims (1)

[Claims] 1. A plurality of sine wave signals having mutually prime frequency relationships are input to the input section of the echo path, the sine wave signals are detected from the output section of the echo path, and the input signal is A method for measuring a flat delay length of an echo path, characterized in that the flat delay length of the echo path is measured based on the time difference between the detection signal and the detection signal. 2. means connected to the input of the echo path for generating a plurality of pseudo sinusoidal signals having mutually prime frequency relationships; means connected to the output of the echo path for detecting the sinusoidal signal; A device for measuring a flat delay length of an echo path, comprising means for measuring a flat delay length of the echo path based on a time difference between a generated signal and the detection signal. 3. The echo path flat delay length measuring device according to claim 2, wherein the generated signal is a burst signal. 4. An echo cancellation device having an adaptive digital filter that creates a replica of the echo signal from an input signal to the echo path, and canceling the echo signal by subtracting the replica of the echo signal from the echo signal of the echo path, A delay line with a fixed delay length that taps the filter delay line of the filter and has a coefficient, and a variable flat delay line that gives a flat delay and whose delay length is controlled by the flat delay length obtained from the flat delay length measurement means of the echo path. 4. An echo cancellation device comprising: a flat delay length measuring device according to claim 2 or 3 connected as said flat delay length measuring means. 5. An echo cancellation device having an adaptive digital filter that creates a replica of the echo signal from an input signal to the echo path, and canceling the echo signal by subtracting the replica of the echo signal from the echo signal of the echo path, The filter delay line of the filter is tapped and has first and second fixed delay length delay lines having coefficients and a flat delay, and the delay length is controlled by the flat delay length obtained from the flat delay length measuring means of the echo path. 4. A flat delay length according to claim 2, wherein the variable flat delay line is provided between the first and second delay lines, and the flat delay length measuring means is a flat delay length measuring means. An echo canceling device characterized by connecting a measuring device. 6. A telephone terminal comprising the echo canceling device according to claim 4 or 5. 7. A car telephone terminal comprising the echo canceling device according to claim 4 or 5. 8. An adaptive digital filter that creates a replica of a reverberation signal from an input signal to an acoustic reverberation path due to acoustic coupling between a microphone and a speaker; an acoustic echo canceler for canceling the signal; and an adaptive digital filter for creating a replica of the echo signal from the input signal to the line echo path, such as by a hybrid transformer in the telephone line; 6. A telephone terminal having a line echo canceling device for canceling echo signals by subtracting copies of echo signals, characterized in that said line echo canceling device is the echo canceling device according to claim 4 or 5. 9. The telephone terminal according to claim 8, wherein the acoustic echo canceling device is the echo canceling device according to claim 4. 10. An echo cancellation device comprising an adaptive digital filter that creates a replica of the echo signal from an input signal to the echo path, and cancels the echo signal by subtracting the replica of the echo signal from the echo signal of the echo path, A filter delay line of the filter is formed of a fixed delay length delay line having taps and coefficients, and a variable flat delay line that gives a flat delay and whose delay length is variable, and detects an increase or decrease in the cancellation ability of the echo cancellation device. flat delay length adjusting means for controlling the variable flat delay line from the increase/decrease information and the flat delay length of the echo path obtained from the flat delay length measuring means; The device has a function of repeatedly adding or subtracting a predetermined value to the flat delay length in a direction in which the flat delay length increases, and the flat delay length measuring device according to claim 2 or 3 is connected as the flat delay length measuring means. An echo canceling device characterized by: