WO2001006725A2 - Procede et systeme de traitement de paquets en parallele - Google Patents

Procede et systeme de traitement de paquets en parallele Download PDF

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Publication number
WO2001006725A2
WO2001006725A2 PCT/IL2000/000392 IL0000392W WO0106725A2 WO 2001006725 A2 WO2001006725 A2 WO 2001006725A2 IL 0000392 W IL0000392 W IL 0000392W WO 0106725 A2 WO0106725 A2 WO 0106725A2
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WO
WIPO (PCT)
Prior art keywords
packet
stage
data
pipeline
receiving
Prior art date
Application number
PCT/IL2000/000392
Other languages
English (en)
Other versions
WO2001006725A3 (fr
Inventor
Joseph Lifshitz
Ran Kahn
Shlomo Cohen
Original Assignee
Coresma Ltd.
Brightcom Technologies Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IL13079699A external-priority patent/IL130796A/xx
Priority claimed from IL13262899A external-priority patent/IL132628A0/xx
Application filed by Coresma Ltd., Brightcom Technologies Ltd. filed Critical Coresma Ltd.
Priority to AU57032/00A priority Critical patent/AU5703200A/en
Publication of WO2001006725A2 publication Critical patent/WO2001006725A2/fr
Publication of WO2001006725A3 publication Critical patent/WO2001006725A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/2801—Broadband local area networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements

Definitions

  • the invention generally relates to broadband communication systems for
  • the invention relates to a system
  • modems are also used for conveying data over other types of mediums, for
  • Wireless and/or broad band are examples, over TV cables, or satellite links.
  • Wireless and/or broad band are examples, over TV cables, or satellite links.
  • modems are used, for example, in mobile communications, e.g., for
  • any modem comprises two main sections.
  • the first section, the modulator-demodulator section, is a mixed signal section for interfacing
  • the modem and the medium of transfer, for example, a telephone
  • modulator-demodulator the term “modulator-demodulator” is used, it should be understood to refer
  • modem the whole apparatus
  • modem the whole apparatus commonly called modem.
  • the second section of any modem is digital, generally referred to as the
  • the MAC module operates in the
  • the purpose of the MAC module is to manage
  • the MAC module is the heart of any modem.
  • the MAC module receives a
  • sequence of data stream from a host creates packets of data that are then
  • modems may need for assuring a reliable communication, i.e., for enabling
  • Access Control handles error correction, regulates the data flow, handles the
  • MAC module when used e.g., in a modem for TV cables are, to carry out the synchronization with the CMTS (Cable Modem Termination System), to
  • the MAC module should comply with certain predefined standards, in order to enable the modem to properly
  • processor if such exists, takes control only at the packet level or IP
  • This configuration is rigid, and cannot be changed or
  • IL 130796 provides a tool for handling a high rate of data and performing
  • Application No. 130796 is used as a MAC module of a modem.
  • the invention of copending IL 130796 further provides a structure for a
  • the packet processor is able to
  • PHY modulator-demodulator
  • the said Packet processor can be easily integrated in a single Very Large
  • VLSI Scale Integration
  • the said Packet Processor of Copending IL 130796 is characterized by that
  • Each of the said two parts includes at least one
  • processing-unit and preferably at least two processing-units.
  • processing- units of the transmitting part frame the data, and combine with
  • error detection and correction e.g., CRC - Cyclic Data Redundancy.
  • processing-unit/s of the transmitting part further organize the data in
  • the receiving processing-units deframe the received data
  • Processor in its basic structure further comprises a management bus by
  • packet processor that comprises two separate parts, a receiving part and a
  • each of said parts comprises at least one processing unit.
  • the received and transmitted data streams are processed in parallel, while
  • broadband modems such as MCNS, DOCSIS and DVB/DAVIC, possibly
  • the invention relates to a process for carrying out the processing of received and
  • each section comprises of at least one processing unit; b.
  • the receiving section :
  • processing tasks are performed simultaneously when possible
  • processing tasks over the data stream are performed
  • the transmitting pipeline and the receiving pipeline are one way
  • pipelines comprising a plurality of segments.
  • the said pipelines may comprise
  • the invention relates to a process for carrying out processing of
  • Processor the process comprising:
  • A. a receiving process comprising:
  • each packet mainly comprises a header and a payload section
  • timing information when exists
  • addressing information while forwarding the payload downstream
  • step d information as extracted in step d with a list of valid addresses
  • step d the validity check of the header (step d) fails
  • step e the validity check if the payload fails (step e).
  • step g From any address in said list of valid addresses (step g); or
  • a. Providing a transmitting pipeline, and at least one processing unit; b. Receiving by the pipeline a payload from a host, and at least a
  • step f If no error is detected in step f, forwarding the resulting packet to a
  • a receiving section comprising:
  • a receiving tubular bus b. At least one processing unit connecting between segments of
  • a transmitting section comprising:
  • At least one processing unit connected between segments of
  • a Host interface for receiving data from a Host and conveying it to
  • the transmitting tubular bus for receiving data from the receiving
  • tubular bus and for conveying it to the Host;
  • the invention also relates to a system for carrying out the processing of received
  • the system comprising:
  • a modulator/demodulator section for transmitting and receiving
  • a Packet Processor comprising a transmitting section for
  • transmitting and receiving sections comprising at least one
  • processing unit a tubular bus connecting the processing units, and a
  • the process of the invention is carried out by a microcode residing in
  • the modulator/demodulator section for carrying out real-time processing in the
  • the microcode part of the process preferably
  • a receiving section comprising: a. A one way pipeline made of segments, said pipeline receives data
  • a Packet Filtering stage for comparing addressing information
  • ansmitting section comprising:
  • a one way transmitting pipeline made of segments, said pipeline
  • a Security stage for optionally receiving framed data packets
  • the Transmission Management stage assigns transmission timing
  • the information for assigning transmission timing slots is stored in a
  • the system of the invention further comprises a CMMS 867 high level
  • the system further comprises a GUI high-level language
  • the validity check is at least a checksum check. More preferably, the
  • validity check is a checksum check and error correction.
  • - Fig. 1 is a scheme showing the input/output buses of the packet
  • - Fig. 2 is a more expanded scheme of Fig. 1, showing the input/output
  • FIG. 3 shows a basic structure of a packet processor, according to one
  • - Fig. 4 shows a structure of a packet processor, according to another
  • FIG. 5 shows a structure of one processing unit in the packet processor of
  • FIG. 6 shows a structure of a packet processor, according to still another
  • Fig. 7 shows a structure of one processing unit in the packet processor of
  • FIG. 8 is a general block diagram illustrating the process of the present
  • FIG. 9 is a more detailed block diagram illustrating the process of the
  • Copending application IL 130796 discloses a Packet Processor that
  • DVB Digital Video Broadcast
  • P/DAVTC Digital Video Broadcast
  • IEEE802.14 IEEE's Cable TV MAC and physical
  • Figure 1 illustrates a basic structure of the Packet Processor of IL 130796,
  • the Packet Processor 1 is a Field Programmable Processors Array (FPPA) having four main interfaces
  • FPPA Field Programmable Processors Array
  • the processor array 2 includes plurality of processors, their associated
  • a host interface 3 connects the Packet Processor to a host.
  • the host is
  • a general-purpose interface 7 connects the Packet Processor with
  • components such as, for example, a keyboard, a debugging processor, a
  • the General Purpose Bus 7 is a relatively slow
  • the External Bus Interface 4 connects the plurality of processing units of
  • the main memory unit is external to the main memory unit
  • each processing unit comprises an internal Instruction Cache (Icache) containing a portion of the code needed for its
  • the PHY (physical) interface 6 connects the Packet Processor with the
  • a data stream is conveyed from the Packet Processor to the modulator for
  • the PHY interface 6 is generally a programmable state
  • FIG. 2 depicts in more detail the environment of a Packet Processor
  • the modem generally a transceiver, which operates in the physical layer.
  • the External bus 14 connects the Packet Processor 2 with the external
  • the Packet Processor 2 communicates with the packet data
  • the modulator-demodulator unit of the modem The modulator-demodulator 10
  • the modulator-demodulator 10 receives the modulated data
  • the data is typically
  • CTMS Cable Modem Termination Modem also known as CTMS
  • transmitted data refers herein to the data that is
  • modulator-demodulator section 10 of the modem which in turn modulates it
  • the modulated data is
  • CMTS also a CMTS
  • first part 23 for handling the flow of
  • the receiving part receives data (hereinafter, this will be referred to as the "receiving part"), and a second part 24 (hereinafter, the “transmitting part") for handling the
  • Each of the said two parts mainly comprises at
  • part further organizes the data in packets that are then optionally
  • Digital data that is received from the demodulator is
  • the receiving processing-unit/s 21 deframes
  • the received data detects and corrects errors by processing the error
  • Ring Bus 44 is actually a "management" bus of the Packet Processor.
  • processing-units, 23 and 24 communicate with other components in the Packet Processor, or with external components, and over this bus data, addresses or instructions flow between the Packet Processor
  • Processor is downloaded from an external data storage, e.g., a diskette, a
  • main memory unit by itself is external of the Packet Processor and is not
  • Ring Bus 44 may optionally be used for enabling communication of the Packet Processor with a keyboard, with a
  • debugging unit or with other different units or devices external to the
  • the Packet Processor 1 further comprises FIFO storage components 60, 61,
  • timing unit 65 for timing and synchronizing the operation of the Packet
  • Fig. 4 depicts in even more detail the structure of the Packet Processor
  • the receiving and the transmitting parts 21 and 22 preferably comprise at least two processing-units each.
  • two or more processing-units are used in
  • the receiving part comprises a
  • Tubular Bus of the Packet Processor of Fig. 4 is 9 bits, and the width of the
  • Backbone Bus is 32 bits.
  • the received data is preferably processed in two
  • the first phase done by Processing- unit- 1 51, includes the
  • Processing-unit-2 52 includes the handling of the main CRC of the content
  • the transmitted data is preferably processed in
  • the first phase done by Processing-unit-3 53, includes the handling of the creation of the header CRC (16 bit error correction),
  • processing-unit-4 54 includes the creation of the main CRC (32 bit
  • processing-units of the Packet Processor 1 is optional, although preferable,
  • the Packet Processor is programmable, and the code according to the
  • invention is downloaded to the memory from an external source (not
  • Modifications to the code can be made at any time, and such
  • each of the four processing-units in the embodiment of Fig. 4 comprises a RISC-type (Reduced Instruction Set Computer) processor.
  • RISC-type Reduced Instruction Set Computer
  • Each processing unit also comprises an internal memory, which
  • SCRAM Scratch PAD RAM Memory
  • a first, input bus 91, to the RISC processing-unit is mainly
  • bus 93 of the processing-unit is bdirectional, and is used by the RISC
  • processing-unit to gain access to the Backbone Bus 44, in order, for example, to communicate with internal or external peripheral components, or to load
  • Ring Bus 44 peripheral components via the Ring Bus 44 is used, among other purposes,
  • FIFO storage elements 70, 71, 72, 73, 74 and 75 The
  • FIFOs FIFOs
  • the said FIFOs enable each of the
  • processing-units to sequentially process a flow of data, and to process and carry out operations on a portion of the data flow which is conveyed to it
  • Each FIFO of the Packet Processor 1 is basically a RAM stage for storing a
  • RAM stage size is generally identical, but the RAM stage size may differ from one
  • the size of the RAM stage in different FIFOs ranges between 32 to 64 words of 9 bits.
  • the FIFO sequentially receives words of data or
  • the macro instructions are
  • FIFO is empty or the processing-unit which should receive it is busy.
  • the Address Filter 82 comprises a table of addresses. When an address is detected in a header of the data
  • next data should be forwarded for a further processing or whether the data
  • An ignoring of data may occur, for example, when the
  • the Packet Processor 1 further comprises a timer 77, which administers the
  • the Packet Processor controls the essential task of slot timing assignments associated with the Packet Processor.
  • it also controls the essential task of slot timing assignments associated with the
  • the bus arbiter 79
  • the ICU (Interrupt Central Unit) 80 administers the ICU (Interrupt Central Unit) 80.
  • External Interface stage 78 are also included in the Packet Processor of the
  • the module comprises a serial interface, preferably
  • Bus Arbiter 99 is used for arbitrating the usage of the external bus 97,which
  • main memory unit (not shown), which, as said, is external to the Packet
  • one port of the memory unit is connected to the Backbone Bus, and the
  • second port of the internal memory unit is connected to a processing- unit.
  • processing-units The structure of the processing-units, and their connection with the internal memory unit, is discussed in more detail hereinafter.
  • the four processing-units 51, 52, 53, and 54 of the Packet Processor have
  • FIG. 5 depicts the structure of a preferred embodiment
  • processing-unit 100 comprises two main components, a RISC processor 101,
  • processor 101 The number of the various tasks that are performed by processor 101
  • the internal memory 109 of the processing unit 100 comprises
  • an instruction cache memory section 110 preferably of the SRAM type, and
  • the internal memory 109 is generally sufficient for the operation of the
  • the co-processor is made via the Auxiliary Bus 105, having a width of
  • the processing unit 100 also comprises a clock unit 115, an Interrupt Control Unit 116, and optionally, a Debug Interface Unit 117.
  • the Interrupt Control unit 116 provides interrupts to the Interrupt
  • the RISC processor 101 has several internal registers other than the
  • Fig. 6 shows the structure of a Packet Processor according to a more
  • Figs 3, 4, and 5 comprises two main buses, a Tubular Bus 29, and a
  • the communication with the external memory unit is
  • the Tubular Bus 242 is preferably a 9-bit bus, and the Backbone Bus 244
  • External Access Bus 245 are preferably buses of 32-bits.
  • the Packet Processor of Fig. 6 comprises, as before, four processing units,
  • the Tubular Bus 243 is
  • demodulator of the modem flows, while being processed, to the host, and
  • the modulator and the demodulator are parts of the
  • Ethernet interface 351 Such an Ethernet interface 351.
  • Timer 277 provides control and timing signals to
  • the optional Debug Interface Unit is
  • the Interrupt Central Unit 280 administers the interrupts to different components of the module, as
  • the Packet Processor of Fig. 6 optionally further comprises a Serial
  • the Packet Processor of Fig. 6 comprises four processing units, 251,
  • the received data is preferably processed in two phases.
  • the first phase done by Processing-unit- 1 251, includes the processing of the header CRC (handling of the 16 bit error correction) and the deframing
  • the transmitted data is preferably processed in two phases.
  • Processing-unit-3 253 includes the handling of the
  • processing-unit-4 254 includes the creation of the main CRC (32 bit error
  • file 295 comprises additional external registers for optional use of any of the
  • each processing unit may have a specific
  • Each of the processing units of the Packet Processor of Fig. 6 mainly comprises a
  • processing unit 251, the processor-1 and its associated co-processor, are indicated as stage 361, and the sub-unit controller is indicated as stage 261;
  • stage 352 the Sub-Unit Controller is indicated as stage 352
  • stage 263 the processor-4 and
  • stage 364 the Sub-Unit
  • the processors are preferably
  • RISC type processors as such processors are capable of performing
  • processing unit 251 of the Packet Processor of Fig. 6 The structure of processing unit 251 of the Packet Processor of Fig. 6,
  • processor- 1 is preferably of
  • a RISC type processor more preferably of the type known as ARC (by ARC
  • Processor 400 receives data from the Tubular Bus 2430, more
  • processor 400 and the coprocessor 401 have each access to the tubular bus.
  • processor 400 performs mainly operations which are related to the
  • coprocessor 401 do mainly specific tasks, i.e., carrying out the DES
  • peripheral bus 444 is a memory mapped local bus through which processor
  • processor 400 to the peripheral bus is made through the memory bus 414.
  • the DES Busy and CRC busy status lines 445 and 446 respectively are used by the coprocessor 401 to indicate to the processor 400 its being in a busy
  • the processor further comprises a Status Core register 407, and it
  • auxiliary registers 410 also communicates with auxiliary registers 410 via an auxiliary bus 411,
  • the memory of the processing unit comprises
  • MAC media access control
  • controller 414 controls the communication between the processor 400 and
  • the Instruction Fetch Bus 420 is used by
  • the Sub-Unit Controller 290 also regulates
  • timing clock 441 provides a timing clock 441 to the processor 400, and optionally also to other
  • the processing unit serves as a time-out
  • DMA Direct Memory Addressing
  • Each channel can enable various of DMA channels.
  • Each channel can be any channel that can enable various of DMA channels.
  • Each channel can be any channel that can enable various of DMA channels.
  • a DMA channel transfer can be initiated by a processor of a
  • processing unit or optionally by another controller or interface that has
  • the DMA channels are divided into
  • processing units in each part significantly improves the rate and the
  • architecture of this invention is scaleable, allowing the use of more than two
  • processing units in each part may improve even more the performance of
  • the rate of that improvement may be less
  • the modem may receive data that is actually
  • the modem for example, in modems for TV cables.
  • the modem for example, in modems for TV cables.
  • the of the invention preferably further comprises an address filter 272.
  • address filter according to the invention is located on the Tubular Bus of the
  • the list of addresses contains, for
  • addresses are treated as unicast, i.e. the address filter looks for an exact address
  • Each address can be marked as "invalid”.
  • the address filter drops from further processing any packet causing a hit on an "invalid"
  • the structure of the Packet Processor of IL 130796 enables performing the
  • modem is a general purpose and programmable, as its code can be
  • IL 130796 is flexible, as it can easily adapt to changes in standards, or data
  • the Packet Processor also preferably employs the concept of Inband
  • macro-instructions are the in-band commands which are passed between the
  • the macro-instructions are used to allow control and "message" passing
  • MI Indicator MI Group Specific MI code
  • the performance of the module is best when its tasks are divided between
  • the Venturi Pipeline model describes a general data communication
  • Venturi Pipeline as is known from classical fluid theory, is a variable
  • dM/dt i.e., the mass flow ratio is naturally kept equal along the pipeline
  • the physical layer level is very high, making the latency cycle required to
  • the size of the information element increases, and at the same time, the
  • processing level increases more and more.
  • Back layers (or group of layers) of information can use a dedicated processor
  • Pipeline the processing units can be very small and simple, dedicated
  • processing unit-1 51 and processing unit-4 53 perform simple tasks on small units of data at a very high rate, while processing unit-2 52 and
  • processing unit-3 54 perform more complicated tasks on larger units of data
  • Such a processor is the ARC RISC microprocessor that can be parameterized in
  • the present invention provides a process for processing
  • the present invention further relates to a packet processing system.
  • system comprises a software process for processing received and transmitted data streams, and hardware for carrying out such process.
  • the system is used as
  • the Host may be a PC or any combination thereof.
  • the internal cable modem may be located external of the Host, may be a card that is plugged into the Host, or may be embedded on
  • the hardware of the system comprises a
  • Such Packet Processor may be, for example,
  • the hardware of the system comprises:
  • a Host Bus Interface such as a PCI interface for communicating with
  • a Microcode that resides in the modem's board and implements the real
  • the software subsystem may further comprise
  • GUI Graphic User Interface
  • the Microcode runs on the modem's board. It mainly carries out the "hard
  • a convergence layer such as MPEG2 in the case
  • the Device Driver866 is responsible for keeping the connection between the
  • the main tasks of the Device Driver are:
  • IP filtering QoS (Quality of QoS)
  • CMMS Common Modem Management Service
  • RSVP provides configuration to the Device Driver and modem's board
  • the CMMS 867 main tasks are:
  • GUI 868 (when used). (d) Managing the registration of high level services, such as QoS and
  • Fig. 9 illustrates in a block diagram form the basic structure of the process
  • the Host processor 816 provides data packets for
  • the Host 827 further communicates
  • the receiving and the transmitting paths 740 and 750 respectively comprise
  • each at least one processing unit and preferably at least two processing units.
  • Each of these paths further comprises a pipeline, that is generally
  • the pipeline itself can be a hardware
  • the first stage 814 of the transmitting path performs mainly the packets
  • This stage also receives transmission timing
  • Stage 807 receives a data stream from the modulator/demodulator section
  • Filter 809 performs packet filtering. More particularly, it compares the
  • Stage 813 performs management analysis, interfacing

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne un procédé de traitement de flux de données reçues et transmises par paquets dans un processeur de paquets. Ce procédé consiste (A) à recevoir un flux de paquets dans un pipeline, chaque paquet comprenant essentiellement un en-tête et une section de charge utile, à analyser l'en-tête du paquet pour en déterminer la validité, les informations de synchronisation et les informations d'adressage, à effectuer, parallèlement à l'analyse de l'en-tête, un contrôle de validité de la charge utile, à procéder éventuellement à un décryptage de la charge utile si celle-ci est cryptée, et, si au moins l'un des contrôles échoue au cours des étapes susmentionnées, à mettre fin au traitement du paquet. Ledit procédé consiste également (B) à créer un pipeline de transmission, à recevoir, par l'intermédiaire de ce pipeline, une charge utile en provenance d'un hôte et au moins une adresse de destination, à créer un en-tête associé et à ajouter des informations de validité à cet en-tête, à associer ledit en-tête à la charge utile et à les réacheminer dans le pipeline, à décrypter éventuellement la charge utile, et, si une erreur survient au cours des opérations susmentionnées, à mettre fin au traitement dudit paquet à transmettre.
PCT/IL2000/000392 1999-07-05 2000-07-04 Procede et systeme de traitement de paquets en parallele WO2001006725A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU57032/00A AU5703200A (en) 1999-07-05 2000-07-04 Process and system for carrying out parallel packet processing

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IL13079699A IL130796A (en) 1999-07-05 1999-07-05 Packet processor
IL130796 1999-07-05
IL132628 1999-10-28
IL13262899A IL132628A0 (en) 1999-10-28 1999-10-28 Process and system for carrying out parallel packet processing

Publications (2)

Publication Number Publication Date
WO2001006725A2 true WO2001006725A2 (fr) 2001-01-25
WO2001006725A3 WO2001006725A3 (fr) 2001-07-19

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001061935A1 (fr) * 2000-02-17 2001-08-23 Conexant Systems, Inc, Modem cable comprenant une commande d'acces au support (mac) programmable

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0765061A2 (fr) * 1995-09-22 1997-03-26 Hewlett-Packard Company Modem de transmission de données à grande vitesse

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0765061A2 (fr) * 1995-09-22 1997-03-26 Hewlett-Packard Company Modem de transmission de données à grande vitesse

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
GOLDBERG L: "MCNS/DOCSIS MAC CLEARS A PATH FOR THE CABLE-MODEM INVASION" ELECTRONIC DESIGN,US,PENTON PUBLISHING, CLEVELAND, OH, vol. 45, no. 27, 1 December 1997 (1997-12-01), pages 69-70,74,78,80, XP000755759 ISSN: 0013-4872 *
PHILIP S ET AL: "A high-speed parallel DSP architecture dedicated to digital modem applications" 1998 IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS. SURFING THE WAVES OF SCIENCE AND TECHNOLOGY (CAT. NO.98EX196), 1998 IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS. SURFING THE WAVES OF SCIENCE AND TECHNOLO, pages 477-480 vol.1, XP002158526 1998, Piscataway, NJ, USA, IEEE, USA ISBN: 0-7803-5008-1 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001061935A1 (fr) * 2000-02-17 2001-08-23 Conexant Systems, Inc, Modem cable comprenant une commande d'acces au support (mac) programmable
US6816940B2 (en) 2000-02-17 2004-11-09 Conexant Systems, Inc. Cable modem having a programmable media access controller

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AU5703200A (en) 2001-02-05

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