WO2001001266A8 - Digital delay locked loop with output duty cycle matching input duty cycle - Google Patents

Digital delay locked loop with output duty cycle matching input duty cycle

Info

Publication number
WO2001001266A8
WO2001001266A8 PCT/US2000/012690 US0012690W WO0101266A8 WO 2001001266 A8 WO2001001266 A8 WO 2001001266A8 US 0012690 W US0012690 W US 0012690W WO 0101266 A8 WO0101266 A8 WO 0101266A8
Authority
WO
WIPO (PCT)
Prior art keywords
duty cycle
clock signal
rising edge
system clock
falling edge
Prior art date
Application number
PCT/US2000/012690
Other languages
French (fr)
Other versions
WO2001001266A1 (en
WO2001001266A9 (en
Inventor
Reuven Holzer
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Priority to EP00932225A priority Critical patent/EP1105808A1/en
Priority to JP2001507208A priority patent/JP2003503797A/en
Publication of WO2001001266A1 publication Critical patent/WO2001001266A1/en
Publication of WO2001001266A9 publication Critical patent/WO2001001266A9/en
Publication of WO2001001266A8 publication Critical patent/WO2001001266A8/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Pulse Circuits (AREA)

Abstract

An I/O port can synchronize the transmission of data on both the rising edge and falling edge of a system clock signal (SCLK) by matching the duty ratio of the internal clock (MCLK) with the duty ratio of the system clock SCLK. This is accomplished by individually delaying both the rising edge and falling edge of the input clock SCLK. By individually delaying both the rising edge and falling edge, the rising edge and falling edge of the system clock SCLK and internal clock MCLK are synchronized. This synchronization ensures that data can be accurately transmitted on both edges of the clock signal. To accomplish this, an I/O port for a CPU has an input port configured to receive a system clock signal, and a digital delay locked loop configured to synchronize a rising edge of an internal clock signal with a rising edge of the received system clock signal and configured to synchronize a falling edge of the internal clock signal with a falling edge of the received system clock signal.
PCT/US2000/012690 1999-06-29 2000-05-10 Digital delay locked loop with output duty cycle matching input duty cycle WO2001001266A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP00932225A EP1105808A1 (en) 1999-06-29 2000-05-10 Digital delay locked loop with output duty cycle matching input duty cycle
JP2001507208A JP2003503797A (en) 1999-06-29 2000-05-10 Digital delay-locked loop where output duty cycle matches input duty cycle

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34285399A 1999-06-29 1999-06-29
US09/342,853 1999-06-29

Publications (3)

Publication Number Publication Date
WO2001001266A1 WO2001001266A1 (en) 2001-01-04
WO2001001266A9 WO2001001266A9 (en) 2001-07-05
WO2001001266A8 true WO2001001266A8 (en) 2001-08-09

Family

ID=23343555

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/012690 WO2001001266A1 (en) 1999-06-29 2000-05-10 Digital delay locked loop with output duty cycle matching input duty cycle

Country Status (3)

Country Link
EP (1) EP1105808A1 (en)
JP (1) JP2003503797A (en)
WO (1) WO2001001266A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100477808B1 (en) 2002-05-21 2005-03-21 주식회사 하이닉스반도체 Digital dll apparatus for correcting duty cycle and method thereof
KR100685604B1 (en) 2005-06-22 2007-02-22 주식회사 하이닉스반도체 Delay locked loop for generating a internal clock signal with decreased jitter components
DE102006051284B4 (en) * 2005-10-26 2011-06-16 Samsung Electronics Co., Ltd., Suwon Duty cycle correction circuit, integrated circuit, phase locked loop circuit, delay locked loop circuit, memory device and method for generating a clock signal
KR102540232B1 (en) * 2017-12-21 2023-06-02 삼성전자주식회사 A digital measurment circuit and a memory system using the same
CN112698683A (en) * 2020-12-28 2021-04-23 深圳市合信自动化技术有限公司 Method and device for solving error of transmission delay data by configurable bus and PLC

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2830735B2 (en) * 1994-04-19 1998-12-02 日本電気株式会社 Phase-locked timing generator
US5815016A (en) * 1994-09-02 1998-09-29 Xilinx, Inc. Phase-locked delay loop for clock correction
US5712884A (en) * 1995-03-31 1998-01-27 Samsung Electronics Co., Ltd. Data receiving method and circuit of digital communication system
US5828257A (en) * 1995-09-08 1998-10-27 International Business Machines Corporation Precision time interval division with digital phase delay lines

Also Published As

Publication number Publication date
JP2003503797A (en) 2003-01-28
WO2001001266A1 (en) 2001-01-04
WO2001001266A9 (en) 2001-07-05
EP1105808A1 (en) 2001-06-13

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