Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
  • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
  • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

• FIG. 3 shows further features of the burst buffers structure of Figure 2;
• FIGS 11A and 11B show alternative pipeline architectures employing further embodiments of the present invention.
• the control interface for the burst buffers system 5 is based around a pair of tables: a Memory Access Table (MAT) 65 describing regions of main memory for bursting to and from the burst buffer memory, and a Buffer Access Table (BAT) 66 describing regions of burst buffer memory.
• MAT Memory Access Table
• BAT Buffer Access Table
• a homogeneous area of dual-port SRAM is used for the burst buffer memory area 26.
• the storeburst instruction (BB_STOREBURST) indexes parameters in the MAT and BAT, which define the characteristics of the requested transfer. If the block increment bit is set, the memaddr field of the indexed entry in the MAT is automatically updated when the transfer completes (as is discussed below).
• the coprocessor controller 9 also acts to control the execution of the CHESS array comprising coprocessor 2 so that it will run for a specified number of clock cycles. This is achieved by the counter in the control finite state machine 42 ticking for the specified number of cycles before "freezing” the CHESS array by "gating" (that is, stopping) its internal clock, in a way that does not affect the internal state of the pipelines in the coprocessor 2.. This number of ticks is specified using the CC START EXEC instruction, described below.
• Coprocessor controller 9 is programmed by processor 1 through the use of the coprocessor instruction queue 8. A possible instruction set for this coprocessor controller 9 is shown in Table 2 below.
• CC_CURRENT_PORT selects one of the ports as the recipient of all the following CC_PORT_xxx instructions, until the next CC_CURRENT_PORT
• a piece of C code to run processor 1 which achieves on the architecture of Figure 1 the same functionality as the original vector addition loop nest is as follows:
• CIQ_ST(cycleno) inserts a CC_EXECUTE_START(cycleno) instruction in order to let the coprocessor 2 execute for cycleno ticks of counter 42;
• Lines 39 to 42 perform the last burst transfer to main memory 3 from burst buffers memory 5, compensating for the absence of a storeburst instruction in the first iteration of the loop body.
• Loadbursts 601 are the first activity (as until these are completed the coprocessor 2 is stalled by the load/execute semaphore), and when these are completed the coprocessor 2 can begin to execute 602.
• the next instruction in the burst instruction queue 6 is another loadburst 601, which is carried out as soon as the first two loads have finished.
• the next instruction in the burst instruction queue 6 is a storeburst 603, which has to wait until the XS semaphore 11 signals that the first computation on coprocessor 2 has completed. This process continues throughout the loop.
• the backend of the compilation toolchain has certain basic functions. One is to schedule and retime the extended dependence graph obtained from the frontend. This is necessary to obtain a fully functional CHESS configuration. Scheduling involves determining a point in time for each of the nodes 82 in the extended dependence graph to be activated, and retiming involves, for example, the insertion of delays to ensure that edges propagate values at the appropriate moment. Scheduling can be performed using shifted-linear scheduling, a technique widely used in hardware synthesis. Retiming is a common and quite straightforward task in hardware synthesis, and merely involves adding an appropriate number of registers to the circuit so that different paths in the circuit meet at the appropriate point in time.
• the input array (src[]) is split into several bursts of appropriate sizes, such that all the address range needed for the algorithm is covered.
• This toolchain uses bursts of length B ⁇ en (where B ⁇ en is a power of 2, and is specified as an execution parameter to the toolchain) to cover as much of the input address space as possible.
• B ⁇ en is a power of 2
• the toolchain uses bursts of decreasing lengths: B
• Replication has been used to enhance the source image by KERNEL_HEIGHT-1 pixels in the vertical direction and KERNEL_WIDTH-1 pixels in the horizontal direction in order to simplify boundary conditions.
• Two kernels are used in evaluating system performance: a 3x3 kernel and a 5x5 kernel, both performing median filtering.
• Figures 9 and 10 illustrate the performance of the architecture according to an embodiment of the invention (indicated as BBC) as against a conventional processor using burst buffers (indicated as BB) and a conventional processor-and-cache combination (indicated as Cache).
• BB burst buffers
• Cache processor-and-cache combination
• Each of the command processors 106, 108 could operate by issuing a command to the coprocessor or burst buffers (as appropriate), and then do nothing until that command has completed its execution, then issue another command, and so on. This would complicate the design, but would free the main processor 1 from its remaining trivial task of issuing instructions into the queues. The only work to be carried out by processor 1 would then be the initial setting up of these two processors, which would be done just before the beginning of the computation. During the computation, the processor 1 would thus be completely decoupled from the execution of the coprocessor 2 and the burst buffers memory 5.
• Two conventional, but smaller, microprocessors could be used, each one of them running the relevant part of the appropriate code (loop nest).
• two general state machines could be synthesised whose external behaviour would reflect the execution of the relevant part of the code (that is, they would provide the same sequence of instructions).
• the hardware complexity and cost of such state machines would be significantly smaller than that of the equivalent dedicated processors.
• Such state machines would be programmed by the main processor 1 in a way similar to that described above. The main difference would be that the repetition of events would be encoded as well: this is necessary for processor 1 to be able to encode the behaviour of one algorithm in a few (if complex) instructions. In order to obtain the repetition of an event x times, the processor 1 would not have to insert x instructions in a queue, but would have to encode this repetition parameter in the instruction definition.

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• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Advance Control (AREA)
• Executing Machine-Instructions (AREA)

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• 1999
  • 1999-06-15 EP EP99304659A patent/EP1061439A1/en not_active Withdrawn
• 2000
  • 2000-06-15 WO PCT/GB2000/002331 patent/WO2000077627A1/en not_active Ceased
  • 2000-06-15 JP JP2001503043A patent/JP5283810B2/ja not_active Expired - Fee Related
  • 2000-06-15 US US09/763,021 patent/US6782445B1/en not_active Expired - Fee Related
  • 2000-06-15 DE DE60045093T patent/DE60045093D1/de not_active Expired - Lifetime
  • 2000-06-15 EP EP00942188A patent/EP1104562B1/en not_active Expired - Lifetime

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