Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B37/00—Lapping machines or devices; Accessories
  • B24B37/11—Lapping tools
  • B24B37/20—Lapping pads for working plane surfaces
  • B24B37/26—Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B21/00—Machines or devices using grinding or polishing belts; Accessories therefor
  • B24B21/04—Machines or devices using grinding or polishing belts; Accessories therefor for grinding plane surfaces
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24D—TOOLS FOR GRINDING, BUFFING OR SHARPENING
  • B24D11/00—Constructional features of flexible abrasive materials; Special features in the manufacture of such materials
  • B24D11/001—Manufacture of flexible abrasive materials
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24D—TOOLS FOR GRINDING, BUFFING OR SHARPENING
  • B24D11/00—Constructional features of flexible abrasive materials; Special features in the manufacture of such materials
  • B24D11/04—Zonally-graded surfaces

Definitions

• the present invention relates to a polishing pad for use in chemical mechanical planarization applications. More particularly, the present invention relates to a pad used in the chemical mechanical planarization or polishing of semiconductor wafers.
• Semiconductor wafers are typically fabricated with multiple copies of a desired integrated circuit design that will later be separated and made into individual chips.
• a common technique for forming the circuitry on a semiconductor is photolithography. Part of the photolithography process requires that a special camera focus on the wafer to project an image of the circuit on the wafer. The ability of the camera to focus on the surface of the wafer is often adversely affected by inconsistencies or unevenness in the wafer surface. This sensitivity is accentuated with the current drive toward smaller, more highly integrated circuit designs.
• Semiconductor wafers are also commonly constructed in layers, where a portion of a circuit is created on a first level and conductive vias are made to connect up to the next level of the circuit.
• each layer of the circuit is etched on the wafer, an oxide layer is put down allowing the vias to pass through but covering the rest of the previous circuit level.
• Each layer of the circuit can create or add unevenness to the wafer that is preferably smoothed out before generating the next circuit layer.
• CMP Chemical mechanical planarization
• polishing pad used on the wafer polisher can greatly affect the removal rate profile across a semiconductor wafer. Ideally, a semiconductor wafer processed in a wafer polisher will see a constant removal rate across the entire wafer surface. Many polishing pads have been designed with one particular pattern of channels or voids to attempt to achieve a desired removal rate. These existing polishing pads often have a signature removal rate pattern that, for example, may remove material from the edge of a semiconductor wafer faster than the inner portion of the wafer. Accordingly, there is a need for a polishing pad that will enhance uniformity across the surface of a semiconductor wafer.
• a polishing member having a linear belt movable in a linear path. At least two serially linked polishing pad sections are attached to the belt.
• the polishing pad sections include a first polishing pad section having a first groove pattern formed in a side of the first polishing pad section.
• the first groove pattern is preferably made up of a plurality of grooves.
• a second polishing pad section has a non-grooved side opposite the linear belt.
• a polishing pad for chemical mechanical planarization of semiconductor wafers includes a plurality of serially linked polishing pad sections forming a linear belt.
• the plurality of serially linked polishing pad sections includes first and second polishing pad sections having respective first and second groove patterns.
• each of the groove patterns is preferably oriented parallel to the linear path of the pad.
• the pad sections may have non-parallel grooves.
• a method of producing a linear chemical mechanical planarization polishing pad having a plurality of polishing pad sections includes the step of empirically measuring the material removal rate profile on a semiconductor wafer for each of a plurality of groove patterns used in chemical mechanical planarization polishing pads, wherein each of the plurality of groove patterns is a unique groove pattern.
• the measured material removal rate profile for each of the plurality of groove patterns is then compared and a determination is made as to an appropriate combination of the different groove patterns to achieve improved removal rate uniformity across a semiconductor wafer.
• a polishing pad comprised of at least two serially linked polishing pad sections is fabricated, where at least two of the polishing pad sections include a different one of the selected groove patterns.
• FIG. 1 is a perspective view of a polishing member having a polishing pad according to a preferred embodiment of the present invention.
• FIG. 2 is a partial plan view of an alternative embodiment of the polishing pad of FIG. 1.
• FIG. 3 is a cross-sectional view of a grooved polishing pad section suitable for use in the polishing pad of FIGS. 1 or 2.
• FIG. 4 is a partial plan view of a second alternative embodiment of the polishing pad of FIG. 1.
• FIG. 5 is a plan view of a rotary polishing pad according to a preferred embodiment.
• FIG. 6 is a graphical representation of material removal rate measurements made according to a preferred embodiment of the method of the present invention.
• FIG. 7 is a graphical representation of the material removal rates obtained by combining selected polishing pad sections described in FIG. 4 according to a preferred embodiment. DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS
• CMP chemical mechanical planarization
• FIG. 1 illustrates a presently preferred embodiment of a CMP polishing pad 10 according to the present invention.
• the polishing pad 10 includes a plurality of polishing pad sections 12. Each polishing pad section 12 is positioned adjacent to the next so that the sections form an unbroken, serially linked chain on the supporting linear belt 14. Each polishing pad section is formed with its own respective groove pattern 16a-c. Also, each groove pattern 16a-c is arranged parallel to the direction of motion of the linear belt 14. Each pad section 12 may be constructed from a separate piece of pad material and connected together to form the complete polishing pad 10. Alternatively, the polishing pad sections 12 may be manufactured in a single piece of material. The polishing pad sections may either be mounted on a separate belt, as shown in FIG. 1 , or may form a polishing pad that is a stand-alone belt.
• the polishing pad 110 includes sections 1 12 having groove patterns 1 16a, 116c and a section completely lacking grooves (i.e. an unbroken polishing pad surface) 116b.
• the grooves are arranged parallel to the direction of motion of the linear belt 114.
• Each groove pattern in one preferred embodiment, is defined by a width, a depth, and a pitch.
• the width 18 of a groove 19 is the distance between opposing parallel walls of the groove.
• the depth 20 is the distance from the outer surface of the polishing pad to the bottom of the groove
• the pitch 22 is the distance from a first wall of a first groove to a respective first wall of the immediately adjacent groove.
• the groove pattern differs between pad sections but is preferably uniform within a given pad section 12, 112 so that the width, depth and pitch are the same for grooves within a particular pad section.
• the groove pattern within a particular pad section may include a width, depth, and pitch that varies between grooves in that pad section.
• the grooves are preferably formed having a rectilinear cross- section, the grooves may be formed having slanted or curved walls.
• a groove is defined as a channel that is cut or formed in the pad material where the length of the channel is greater than its width.
• a groove may or may not extend the entire length of a pad section.
• the grooves in a particular pad section may be non-parallel.
• a linear polishing pad 210 is shown including a polishing pad section 212 with a non-parallel groove pattern 216a.
• the non-parallel groove pattern 216a may have grooves that intersect.
• the polishing pad section 212 with the non- parallel groove pattern 216a may be combined with other polishing pad sections 212 having parallel groove patterns 216b - 216d.
• the parallel groove pattern may include pattern of serpentine grooves 216d or other curves that are disposed in either a parallel or a non-parallel relationship to each other.
• One or more polishing pad sections may have an embossed pattern of circular voids or dimples formed in the pad material, rather than grooves, in yet another embodiment.
• the semiconductor polishing pad may be a rotary polishing pad.
• FIG. 5 illustrates one rotary polishing pad 310 having a plurality of wedge-shaped sections 312 that are serially linked such that a semiconductor wafer is sequentially presented with a different section as the rotary polishing pad is rotated.
• Each section 312 preferably has a different groove pattern 316a - 316c.
• one or more sections 312 may each have a groove pattern that includes a plurality of concentric arc segments (see groove patterns 316a and 316c) centered about the center of the rotary pad.
• one or more sections 312 may have a groove pattern including a plurality of non-concentric groove patterns.
• One suitable pad material for use in constructing the polishing pad sections that make up the linear or rotary semiconductor polishing pad is a closed cell polyurethane such as IC1000 available from Rodel Corporation of Phoenix, Arizona.
• each pad section is preferably constructed of the same pad material, in other embodiments, one or more different pad materials may be used for each polishing pad section in the polishing pad.
• the pad materials may also be selected to have a different hardnesses or densities.
• the pad materials may have a Durometer hardness in the range of 50 - 70, a compressibility in the range of 4% - 16%, and a specific gravity in the range of 0.74 - 0.85.
• the grooves may be fabricated in the pad material using standard techniques used by any of a number of commercial semiconductor wafer polishing pad manufacturers such as Rodel Corp. Referring to FIGS.
• the polishing pad 10, 1 10, 210 may be mounted to a linear belt 14, 1 14 in one embodiment and utilized in a linear semiconductor wafer polisher such as the TERES TM polisher available from Lam Research Corporation of Fremont, California.
• a linear semiconductor wafer polisher such as the TERES TM polisher available from Lam Research Corporation of Fremont, California.
• the pad 10, 1 10, 210 is continuously moved along a linear direction while a semiconductor wafer holder (not shown) presses a semiconductor wafer against the surface of the pad.
• the semiconductor wafer holder may also rotate the wafer while holding the wafer against the pad.
• the pad 10, 110, 210 along with a slurry that is both chemically active and abrasive to the wafer surface, is used to polish layers on the wafer. Any of a number of known polishing slurries may be used. One suitable slurry is SS25 available from Cabot Corp.
• the groove pattern 16, 116, 216 including the absence grooves, on a pad section changes the ability of the pad to transport slurry underneath the wafer and therefore the groove pattern can affect the material removal rate profile as measured on a cross section of a wafer.
• polishing pads each having a single groove pattern and each completely covering the circumference of a different belt, are each used to polish a semiconductor wafer for a predetermined time.
• the same wafer polisher preferably the TERES TM polisher available from Lam Research Corporation, is used to test each of the polishing pads.
• the amount of material removed is measured at various points across the diameter of the wafer and recorded in a database on a computer. The removal rates are then compared at the respective measurement points used for each semiconductor wafer.
• the comparison of the material removal rates and determination of the appropriate combination of groove patterns may be accomplished using a personal computer running a program written in Excel by Microsoft Corporation. After calculating the predicted polishing pad sections that produce a polishing pad having a substantially uniform material removal rate across an entire wafer, a polishing pad is fabricated using commonly known fabrication techniques so that the appropriate section lengths for each chosen groove pattern are combined on a single belt.
• the pad may be a single, continuous strip having the appropriate groove patterns and lengths formed in it.
• separate pieces of pad material, each having its own groove pattern may be linked together on a single belt.
• FIG. 6 A graphical representation of material removal rates for various groove patterns is illustrated in FIG. 6.
• the x-axis of the graph in FIG. 6 represents the measurement point along the diameter of the semiconductor wafer in millimeters from the center of the wafer.
• the y-axis represents the measured removal rate in angstroms per minute.
• Each trace on the graph represents the measured removal rate for a pad having a particular grove pattern.
• the downforce (pressure applied to the semiconductor against the pad) for all measurements was 5 pounds per square inch, while the linear speed of the pad and the rotational speed of the wafer holder were 400 feet per minute and 20 revolutions per minute, respectively.
• the groove patterns corresponding to the illustrated material removal rates are as follows:
• the material removal rate and the removal rate profile vary significantly between the different groove patterns.
• a predicted removal rate profile may be calculated.
• the grooves are oriented parallel to the direction of motion of the pad on the linear belt. While various other groove dimensions are contemplated, the groove dimensions are preferably within the range of 0-30 thousandths of an inch (mils) wide, 5-30 mils deep, and have a pitch in the range of 25-200 mils.
• the K-GrooveTM trace 200 refers to a commercially available groove pattern from Rodel Corp.
• FIG. 7 illustrates a predicted removal rate profile 218 and the actual removal rate profile 220 measured from a polishing pad fabricated according to the method described above.
• the polishing pad used to generate the removal rate profiles 218, 220 included three polishing pad sections having equal lengths and constructed out of the same polishing pad material.
• the first polishing pad section included a groove pattern of 0.010" x 0.020" x 0.100" (depth x width x pitch)
• the second polishing section included a groove pattern of 0.020" x 0.020" x 0.050”
• the third polishing pad section had no grooves.
• Another polishing pad fabricated according to a preferred embodiment of the present invention, having improved material removal rate uniformity along the entire width of the wafer, is made up of five polishing pad sections: no groove, 12 x 20 x 50, 20 x 20 x 50, 10 x 20 x 100, and 20 x 20 x 100 (where the dimensions are in thousandths of an inch and refer to width x depth x pitch).
• no groove 12 x 20 x 50, 20 x 20 x 50, 10 x 20 x 100, and 20 x 20 x 100 (where the dimensions are in thousandths of an inch and refer to width x depth x pitch).
• the method provides for comparing removal rate profiles for different groove patterns and mathematically optimizing a resulting combination of polishing pad sections on a single platform to improve the removal rate profile.
• the resulting pad preferably has a more uniform material removal rate across a semiconductor wafer.
• a CMP polishing pad is also disclosed having a plurality of serially linked polishing pad sections.
• the plurality of pad sections may form a linear belt or may be mounted on a separate linear belt. Also, the pad sections may form a rotary polishing pad.
• Each polishing pad section includes a different groove pattern that, in a first embodiment, is made up of grooves oriented parallel to the direction of travel of the pad and, in another embodiment, may include grooves that are not parallel to the direction of travel.
• a polishing member for use in chemical mechanical planarization of semiconductor wafers comprising: a linear belt, the linear belt movable in a linear path; and at least two serially linked polishing pad sections attached to the belt, the polishing pad sections comprising: a first polishing pad section having a first groove pattern formed in a side of the first polishing pad section opposite the linear belt, wherein the first groove pattern comprises a plurality of grooves; and a second polishing pad section having a non-grooved side opposite the linear belt.
• polishing member of claim 1 wherein the plurality of grooves are oriented parallel to the linear path of the linear belt.
• polishing member of claim 1 wherein the at least two polishing pad sections further comprise a third polishing pad section having a third groove pattern, the third grove pattern having a plurality of grooves oriented parallel to the linear path of the linear belt, and wherein the third groove pattern differs from the first groove pattern.
• polishing member of claim 3 wherein the at least two polishing pad sections comprise at least two different levels of hardness.
• each of the at least two polishing pad sections comprise at least two different densities.

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• Engineering & Computer Science (AREA)
• Mechanical Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Mechanical Treatment Of Semiconductor (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

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Cited By (7)

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Citations (3)

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• 1999
  • 1999-05-21 US US09/316,166 patent/US6261168B1/en not_active Expired - Fee Related
• 2000
  • 2000-05-15 JP JP2000619588A patent/JP2003500843A/ja active Pending
  • 2000-05-15 EP EP03075541A patent/EP1329290A3/en not_active Withdrawn
  • 2000-05-15 EP EP00930746A patent/EP1178872B1/en not_active Expired - Lifetime
  • 2000-05-15 SG SG200306843-4A patent/SG152899A1/en unknown
  • 2000-05-15 KR KR1020017014762A patent/KR100706148B1/ko not_active IP Right Cessation
  • 2000-05-15 AT AT00930746T patent/ATE251524T1/de not_active IP Right Cessation
  • 2000-05-15 DE DE60005816T patent/DE60005816T2/de not_active Expired - Fee Related
  • 2000-05-15 WO PCT/US2000/013328 patent/WO2000071297A1/en active IP Right Grant
  • 2000-06-05 TW TW089109756A patent/TW462906B/zh not_active IP Right Cessation
• 2001
  • 2001-05-30 US US09/870,212 patent/US6634936B2/en not_active Expired - Fee Related
  • 2001-07-13 US US09/905,332 patent/US6585579B2/en not_active Expired - Fee Related

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