WO2000062119A1

WO2000062119A1 - Welding helmet with hybrid lens system and low power consumption control circuit therefor

Info

Publication number: WO2000062119A1
Application number: PCT/US1999/016742
Authority: WO
Inventors: Dennis A. Byrne; Jerry Charles Cole
Original assignee: Jackson Products, Inc.
Priority date: 1999-04-09
Filing date: 1999-07-23
Publication date: 2000-10-19
Also published as: AU5126399A

Abstract

A lens assembly (24) and associated control circuit (30) which provide an auto-darkening feature for a welding helmet (20) is comprised of a twisted neumatic lens (26) and a surface mode lens (28), each of which are separately electrically actuated to achieve a user's preselected shade. The control circuit (30) has a preprogrammed microprocessor for controlling the actuation of the filters (26, 28), and has a control scheme that minimizes the power consumption of the lens assembly to prolong battery life. The control scheme includes actuating the higher energy using filter separately and for at least the darkest shade at a different frequency than the lower energy using filter. The digital control circuitry includes digital potentiometers to permit the microprocessor to run a calibration routine to set the shade settings for the actual filters used.

Description

Welding Helmet With Hybrid Lens System and Low Power Consumption

Control Circuit Therefor

Background of the Invention

Welding helmets are known in the prior art, and have been used for years to protect the face and eyes of a welder as he does his work. Various improvements to the standard welding helmet have been made over the years, but perhaps the most dramatic has been the auto- darkening lens. As is known in the art, the welding helmet generally has a face shield and a viewing area through which the welder views his work. For many years, this viewing area was covered with a permanently shaded glass lens. Of course, this permanently shaded lens was appropriate for the actual welding operation itself, but made it inconvenient for a welder to use as he prepared his work or performed other tasks requiring him to see what he was doing. And, it led to the tendency of a welder to put on and take off his helmet many times during the course of a day's work. This was not only inconvenient, but with the helmet off, the welder's face and eyes were not protected from other hazards which lurked in the construction workplace.

A significant improvement to the welding helmet was the advent of the auto-darkening lens. As known in the art, the auto-darkening lens covers the viewing opening and is comprised of one or more liquid crystal filters which are electrically operable to adjust their "shade" level, or light transmissibility. Thus, as the welder moves about his workplace and does other things, he can wear his helmet but yet have relatively unimpeded vision through the substantially clear lens. Then, as he starts his welding, a photosensitive diode or other light sensing device senses the greatly increased light level impinging on the welder's helmet, and which might otherwise pass through the lens and operates a battery powered control circuit mounted on board the helmet to electrically actuate the filters and darken them to protect the welder's eyes. All this without the welder having to remember to put his helmet on. An example of such an auto-darkening lens arrangement is shown in US Patent Application Serial No. 08/623,972, filed March 29, 1996, the disclosure of which is incorporated herein by reference. Although this invention of the auto-darkening lens is a good and valuable invention with many features and benefits as more fully ' explained in the US Patent Application incorporated herein, a nagging problem persisted with this device. As the filters used in the lens require the application of an electrical signal to be actuated to convert to a dark shade, all the while the filter is actuated the batteries carried on board the helmet are draining. While typically a solar cell is provided as part of the helmet to help recharge the batteries and increase their useful life, the experience is that the battery life is a limiting factor in the acceptance of a true auto- darkening lens helmet . While several attempts have been made in the prior art, including those shown in US Patent No. 5,315,099 issued May 24, 1994, such attempts have been met with only limited success and commercial acceptance as the operating circuits and filters used did not reduce the operating power required to such a degree that the battery life lasted appreciably longer than before.

In order to solve these and other problems in the prior art, the inventors herein have succeeded in designing and developing a hybrid lens arrangement comprised of a twisted neumatic filter and a surface mode filter, and a microprocessor controlled control circuit providing a novel operating method that significantly reduces the power required to achieve a desired lens shade level so as to dramatically improve the on board battery life. The invention includes a lens comprised of two filters, one being twisted neumatic and the other surface mode, which are each separately electrically actuated in a predetermined combination to achieve the desired shade. The filters are preferably set up to operate the twisted neumatic (TN) filter at a constant shade as it generally draws less power to darken, and the surface mode (SM) filter at a variable shade to provide the variability desired between user selectable shade levels. As the SM filter requires greater power to achieve a particular shade, the control circuit is designed to actuate it at a fixed voltage for each of the user selectable shade levels and then adjust the voltage required for the TN filter to "tweak" it and complete the shade level adjustment.

Still another feature of the present invention is the particular calibration routine used to set up the control circuit for actuating the filters. With the preferred calibration routine, the voltage applied to the SM filter is fixed first as it the SM filter draws the most power to operate. Preferably, the inventors have found that for shade 9 the TN filter alone can be used so the voltage for the SM filter is 0 volts, for shade 10 the SM voltage is 6 volts, for shade 11 the SM voltage is 8 volts, and for shade 12 the SM voltage is 11.2 volts. The actuation voltage for the TN filter typically ranges from 4 to 6 volts. Thus, it can be understood that the SM filter consumes more power than the TN filter. Therefore, by fixing the actuation voltage for the SM filter, and adjusting the voltage for the TN filter in order to achieve the desired lens shade, the control circuit power requirements and the battery load are subject to less variation.

At the most commonly used user selectable shade setting, shade 12 which is the darkest shade, the control circuit further minimizes power consumption by dramatically lowering the frequency of the electrical signal used to power only the SM filter, thereby dramatically lowering the power it consumes. A much slower frequency is desirable in order to minimize power consumption, but a drawback is the tendency for a low frequency signal to produce a visible "flicker" caused by the rhythmic transition of the filter as the signal polarity is reversed which distracts the welder's attention and is objectionable. The "flicker" effect is well known in the art and results from the fact that the filter polarity must be reversed periodically in order to maintain it in a darkened state. However, during the time that the polarity is being reversed, the filter loses its shade and if the polarity reversals are made with a great enough frequency such as 32 Hz. which is 64 transitions each second, the eye doesn't react fast enough to pick them up. The minimum frequency to avoid the eye picking up this flicker is about 48 transitions per second and is known as the flicker frequency which is well known and used to avoid flicker in all kinds of visual displays, motion pictures, video screens and monitors, etc. In the present invention, by operating the two different filters at different frequencies, the TN filter transmits significantly more light energy during its transition such that it masks the SM "flicker" at least at the darkest lens shade setting and avoid the welder noticing any objectionable flicker.

Still another novel feature of the present invention is the use of a microprocessor which allows for a programmable control. In other words, the specific operation of the control is determined by the software loaded into the microprocessor and can be changed to provide additional operating routines, upgrades and improvements while a dedicated chip, such as an ASIC, which might provide the same initial operating routine can not be altered after it is made. This allows for the helmet to be retrofitted should new features be developed, and avoid the waste of discarding it in favor of a new helmet. All the other additional features and advantages of a microprocessor are also then available including the ability to fix unintended errors in circuit operation discovered only after a commercial roll out. The use of a microprocessor is considered an improvement over the ASIC and other fixed logic control circuits predominantly found in the prior art.

As an example of still another advantage provided by the programmable microprocessor, a number of potentiometers are typically provided in the control circuit to allow for adjustment of actuation voltage levels to ensure that the particular filter provided will achieve the desired shade level. As can be appreciated, there are manufacturing variances between the filters and these variances affect the voltage which must be applied to the filter to achieve the desired shade level. In order to allow factory adjustment of these shade levels, typically in the prior art analog potentiometers are provided in the control circuit which must be "tweaked" during final assembly. Not only is this labor intensive, but it can lead to misadjustment , either intentional or unintentional. With the microprocessor control of the present invention, digital pots are preferably used which the microprocessor can then adjust while executing a sub-routine that ensures digitally accurate adjustment with no possibility for human error. This feature thus offers greater accuracy at less overall cost. While the principal advantages and features are explained above, a fuller understanding of the invention may be attained by referring to the drawings and description of the preferred embodiment which follows.

Brief Description of the Drawings

Figure 1 is a side view of a helmet and lens assembly of the present invention;

Figure 2 is a plan view of the lens assembly, depicting the side that is externally exposed as the lens assembly is mounted in the helmet;

Figure 3 is a plan view of the lens assembly, depicting the side that is internally exposed as the lens assembly is mounted in the helmet; and

Figure 4 is an electrical schematic of the control circuit as contained inside the lens assembly.

Detailed Description of the Preferred Embodimen

As shown in fig. 1, the helmet 20 mounts to the head of welder by any convenient means, such as a head gear as known in the art, so that the welder's eyes 22 are aligned with the lens assembly 24. In the lens assembly of the present invention, the lens assembly 24 includes two filters, a TN filter 26 and an SM filter 28, which are sandwiched together. The control circuit 30 is included in the lower portion of the lens assembly and includes a plurality of pushbuttons as best shown in fig. 3. As shown in fig. 2, the externally exposed surface of the lens assembly contains the filters 26,28, a solar cell 32, and a pair of photosensitive transistors 34, or the like. The internal surface is shown in fig. 3 and includes the shade 36, sensitivity 38, and delay 40 pushbuttons to provide the functions as are customarily provided with an auto-darkening lens assembly. Pushbuttons such as are disclosed and described in the patent application incorporated by reference are preferably used in the present invention, although other types of buttons could be used as well. Thus, the physical arrangement and layout of the lens assembly of the present invention has been described. The control circuit as shown in fig. 4 will now be described as part of the preferred embodiment .

Microprocessor U7, XI, C8, C27, R42

The microprocessor is a Motorola 68MC705J1ADW. It executes the on board software program as shown in Appendix A attached hereto. The program provides output control (darkening and darkness level control of the viewing lens) on a timed basis and on an unscheduled, input derived basis. The microprocessor pin out and its functions are:

Pin 1 OSC1 Microprocessor on board crystal/resonator oscillator input

Pin 2 OSC2 Microprocessor on board crystal/resonator oscillator output.

Pin 3 PB5 Programmable input/output pin, B register — programmed as an output for serial clock input of U15, local signal Pin 4 PB4 Programmable input/output pin, B register — programmed as an output for level control of high voltage enable signal (HVEN) , global signal

Pin 5 PB3 Programmable input /output pin, B register — programmed as an output for switching frequency of the surface mode LCD. Signal is polarity input of U4, local signal. Pin 6 PB2 Programmable input/output pin, B register — programmed as an output for reset of the light sensor output, local signal. pin 7 PB1 Programmable input/output pin, B register — programmed as an output for serial clock to all devices connected to the serial bus, used with serial data, global signal. Pin 8 PB0 Programmable input/output pin, B register — programmed as an output for serial data to all devices connected to the serial bus, used with serial clock, global signal Pin 9 VDD Power input, high side — connected to VCC potential in the circuit Pin 10 VSS Power input, low side -- connected to ground potential in the circuit

Pin 11 PA7 Programmable input/output pin, A register — programmed as 1) as an input for test mode selected signal (15K resistor to ground potential2), used only upon start up from a reset, local signal, and 2) an output for U15 output latch clock, local signal .

Pin 12 PA6 Programmable input/output pin, A register — programmed as an output for U13, U14 output latch clock, local signal Pin 13 PA5 Programmable input/output pin, A register -- programmed as an output for Ulchip select (device enable) , local signal .

Pin 14 PA4 Programmable input/output pin, A register — programmed as an input for the low battery voltage detector output from U6, local signal.

Pin 15 PA3 Programmable input/output pin, A register — programmed as an input for the light sensor detector output from

U10B, local signal. pin 16 PA2 Programmable input/output pin, A register — programmed as an input for the switch closure output of SW3, local signal .

Pin 17 PA1 Programmable input/output pin, A register — programmed as an input for the switch closure output of SW2, local signal. Pin 18 PAO Programmable input/output pin, A register — programmed as an input for the switch closure output of SW1, local signal.

Pin 19 IRQ* Programmable (external) Interrupt Request input pin — programmed as a falling edge triggered interrupt. Pin 20 RESET* Schmidt triggered, low level active input pin

OSC1 and OSC2 of U7 are the input and output pins of the on board microprocessor frequency oscillator. The microprocessor has an on board feedback resistor. The ceramic resonator (XI) sets the microprocessor internal frequency at 4.00 MHz. Capacitors C8 and C27 provide power supply filtering to and from the microprocessor. R42 (27k) provides a test point for externally resetting the microprocessor alone (testing and development design requirement)

Master Reset U9 Gates A & B, R5, C31, D5

The master reset signal resets the microprocessor (U7), the external timing generator (Ull), and the twist neumatic display shift registers (U13, U14) to an internally established data state (usually low state output) . R5 and C31 provide the timing (length) of the reset signal. At power start up, C31 is discharged and begins to charge to VCC through R5. U9 Gate B is a Schmidt triggered input inverter switching its output from the high state to a low state in one R5/C31 time constant. U9 Gate B output drives the reset signal for Ull (high active) and the input of U9 Gate A. U9 Gate A then drives the reset inputs of U7, U13 and U1 .

External Timing Generator Ull, CIO, R19, R26, C37, C36, X2

Ull is CV4060BCM, a CMOS 14 stage binary ripple counter with on board oscillator capability. The pin out is:

Pin 1 Q12 Ripple counter output pin, stage 12 -- not used

Pin 2 Q13 Ripple counter output pin, stage 13 — not used

PPiinn 33 QQ1144 Ripple counter output pin, stage 14 — not used

Pin 4 Q6 Ripple counter output pin, stage 6 — not used

Pin 5 Q5 Ripple counter output pin, stage 5 — 1 kHz output is used as the signal for the very high voltage multiplier circuit. Pin 6 01 Ripple counter output pin, stage 7 — not used Pin 7 Q4 Ripple counter output pin, stage 4 — 2 kHz output is used as the drive for the voltage doubler circuit for the twist neumatic LCD drivers

Pin 8 VSS Power input, low side — connected to ground potential in the circuit Pin 9 FYO On board oscillator output buffer (inverted output of FYO*) — output is used as the drive for a voltage doubler circuit for the very high voltage (VHV) supply

Pin 10 FYO* On board oscillator output pin (inverted output of FYI) Pin 11 FYI On board oscillator input pin Pin 12 RESET Reset input (active high) pin

Pin 13 Q9 Ripple counter output pin, stage 9 -- 64 Hz output is uses as the IRQ* signal of U7

Pin 14 Q8 Ripple counter output pin, stage 8 — not used Pin 15 Q10 Ripple counter output pin, stage 10 — not used Pin 16 VDD Power input, high side — connected to VCC potential in the circuit R26 provides the oscillator bias for the Ull on board oscillator. R19, C37, C36, X2 with Ull constitute a parallel resonant, crystal oscillator operating at 32.768 kHz. The on board oscillator drives the 14 stage ripple counter (Ull) . The buffered output signal (Ull pin 9) is used to drive a voltage doubler circuit used in generating the very high voltage for the surface mode LCD. Ull pin 5 is used as the signal for the very high voltage multiplier. Capacitor CIO provides power supply filtering to and from the counter.

EEROM Data Storage Ul, C17, R4

Pin 1 CS Chip Select (active high) input — IC enable signal for read and write operations, Pin 2 CLK Data Clock input — serial digital data clock signal, global signal

Pin 3 DI Data input — serial digital data, global signal

Pin 4 DO Data output — serial digital data, local signal, high impedance output when device not selected Pin 5 VSS Power input, low side -- connected to ground potential in the circuit

Pin 6 NC Not connected

Pin 7 NC Not connected

Pin 8 VDD Power input, high side — connected to VCC potential in the circuit

The EEROM (Ul) is a read and write memory storage device that retains its data when power is removed. Its function is to retain all of the calibration data for operation of the device along with retaining the last operational state (shade, delay, sensitivity) prior to the microprocessor (U7) turning off the power. Data is transferred between the EEROM (Ul) and the microprocessor (U7) using the serial data and serial clock bus. The EEROM (Ul) is enables (activated) for communication when the CS line (Pin 1) has been taken to a "1". A read of the EEROM (Ul) memory requires a READ command and the starting EEROM memory address to be sent to the EEROM (Ul) before any data is read. When the command has been sent, continued clocking of the data clock line (Ul pin 2) causes data bits to be clocked out of the EEROM (Ul) in an MSB to LSB fashion. In this application, only 19 data bytes are read into the microprocessor (U7 pin 15) . Upon completion of the read operation, the CS (Ul pin 1) is returned to "0". A write operation requires the CS (pin 1) to be taken high, a serial WRITE_ENABLE command is sent and the CS returned to a low. The CS is again taken high and a WRITE command, the address (where a byte will be stored) , and the data byte are then sent to Ul pin 3. The CS (pin 1) is then taken low. The microprocessor (U7) then takes CS (pin 1) high and monitors DO (pin 4) until it changes from a low to a high, signaling the completion of the EEROM write cycle. A WRITE_DISABLE command sent in the same fashion as a WRITE_ENABLE command is sent. When all the data has been written to prepare the EEROM (Ul) to be powered off. The microprocessor (U7) writes to the EEROM (Ul) 19 bytes at the end of the calibration routine, and two bytes (device state) at the end of the normal operational routine. Both the calibration and operational routines read 19 bytes from the EEROM (Ul) at the beginning of the routine.

R4 provides a load impedance between the output of the light sensor detector output and the EEROM (Ul) data output. When the microprocessor (U7) communicates with the EEROM (Ul) , the data from the EEROM (U7) has priority over the light sensor detector output. R4 provides this function. Capacitor C17 provides power supply filtering.

Twist Neumatic Voltage Doubler Q8, R24, U3 pins 1-7, C19, Dl,

C29, D7, D6 U9 Gate C

The Twist Neumatic (TN) Voltage Doubler generates an output voltage (VLCD) up to double the VCC voltage for use as supply to the TN drivers (U13, U14). The design is a modification of the classic capacitor diode voltage doubler, with the addition of series resistance for current and voltage control. The drive signal is a 2 kHz digital square wave from Ull, pin 7. The signal goes into the parallel combination of Q8 and R2 . The gate of Q8 is driven from the high voltage enable (HV_ENABLE) signal through U9 Gate C. When HV ENABLE is high, U9 C inverts the signal and sends it to a P- channel FET Q8. Q8 then becomes a short circuit across R24 when high voltage (and higher current) is required for the TN display. During non-HV ENABLE, R24 is in the circuit limiting the voltage and current. After the signal passes through Q8 and/or R24, it passes through U3 Side 2, a digitally controlled potentiometer (pot) . The wiper (U3 pin 4) is attached to the top of the pot (U3 pin 3) and to Q8 & R24. The lower end of the pot (U3 pin 2) feeds the input of the voltage doubler. The output side of C19 is precharged to VCC by one half of Dl. The additional signal transferred through C19 raises the output of Dl to VCC minus the diode drop, plus the drive voltage level at the input of C19, minus the output diode drop. D7 precharges C29 to VCC limiting the voltage/current transfer of the circuit to the amount needed to maintain the output voltage (VLCD) above VCC. D6 is a zener diode added to limit the output voltage to 6.2 volts. This is required to prevent U13 and U14 from being over voltaged during calibration and operation of U3 and Q8.

The pot (U3 Side 2) is digitally controlled with a serial data stream containing the pot selected (side 1 or side 2) and the value of the pot setting (0-255) . The microprocessor selects the pot IC (U3) by bringing CS* (U3, pin 7) low through U15 pin 6. The serial data is then sent on the serial data bus to U3 pin 8 (MSB to LSB) and clocked into the IC by the serial data clock (U3 pin 9) . The digital pot setting is transferred to the analog pot output when CS* (U3 pin 7) is returned to the high level. Since the pot (U3) is always set to a value in the software, reset (RS*, U3, pin 10) and shut down (SHDN*, U3, pin 6) are not implemented. Capacitor C18 provides power supply filtering to and from the digital potentiometer.

Low Battery Detector U6, R8, R27, R7, U3 to Side 1

The low battery detector signals the microprocessor at (U7, pin 14) when the battery voltage falls below 2.5 Vdc. The battery voltage is fed into the resistive voltage divider network formed by R8 - R27 and U3 pin 12 & 13. U3 Side 1 is a digitally controlled potentiometer under the control of the microprocessor (U7) . The potentiometer (U3 Side 1) raises or lowers the voltage divider's ratio to adjust the reference to the comparator reference to U6 (U6 pin 7) . U6 contains an open drain output comparator and voltage reference. This comparator is used with the voltage divider to generate the low battery output (U6 pin 8). R7 is the pull up resistor for the comparator's output. Twisted Neumatic Display Drivers U13, U14, C9, Cll

The twisted neumatic (TN) LCD requires a voltage difference between the back plane and a segment to generate a dark area. The voltage polarity must be changed on a regular basis to maintain a proper dark state. Zero voltage between the back plane and the segment results in a clear area. The serial input, parallel output 8 bit shift registers with output latch (U13, U14) expand the output line capability of the microprocessor (U7) to drive all of the TN segments in this design. The microprocessor (U7) sets the bit pattern in U13 and U14 by sending the data on serial data bus (SER U13, pin 14) and clocking the data into the shift registers with the serial clock bus (SCK - U13, U14, pin 11) . Since data is a serial stream, U13 has a data output (pin 9) which feeds the data into U14 (pin 14). The data in the shift registers are transferred to the outputs (pins 1, 2, 3, 4, 5, 6, 7, 15) by clocking the output data latches (RCK, U13, U14, pin 12) . This is done with a separate signal line from the microprocessor (U7 pin 12) . The shift registers have data reset function (SCLR*, U13 & U14 pin 10), which is clocked by the master reset. At regular intervals, the microprocessor (U7) inverts the previous data pattern and writes it to the shift registers (U13, U14), maintaining the TN display.

The level of darkness achieved by the segment is a non-linear function of the voltage applied across the segment to the back plane. The microprocessor (U7) controls the darkness of the TN LCD by adjusting the supply voltage (VLCD) on the shift registers (U13, U14) supply pins (VCC, pin 16) . Capacitors C9, Cll provide power supply filtering to and from the shift registers.

VCC Supply U6, C28, R33, C39, L2, D12, R9, R21,

C34, Q18, R31, U10A, U17 A&B, R18, C26, U16, C6, C44

U6 is a low power DC to DC switching regulator IC. U6, L2, D12 and C34 form a standard switching regulator circuit. U6 contains a transistor that switches the output of the inductor (L2) to ground. This causes a current to flow in the inductor. When the transistor turns off the current, the inductor induces a voltage in the inductor higher than the input side. This higher voltage turns on the diode (D12) and allows inductor current to flow into the output capacitor (C34). The amount of current (charge) in the capacitor determines its voltage. The regulator IC (U6) monitors the output voltage by the feedback network of R9 and R21. The regulator IC (U6) adjusts the current in the inductor (L2) by how long the transistor is turned on (longer on times, more current through inductor, more current to the output) . The divider portion of the feedback network sets the output voltage level. R33 and C39 form a phase compensation circuit, required to minimize unwanted oscillations in the regulator circuit. Capacitor C28 provides power supply filtering to and from the VCC supply switching regulator (U6) . Capacitor C34 provides power supply output filtering.

VCC is turned ON when a light sensor detector has been triggered or an input switch has been pushed. This is accomplished through U16. U16 OR's the triggering signals from the three switches and the light sensor detectors into one signal (U16, pin 8) . If any signal goes high, it is sent to the inverter U17B. A low is then sent to U10A pin 4 (Preset), making Q* low (U10 pin 6). Power ON is then achieved by pulling the gate of Q10 and its resistor R31 low, allowing the battery to supply U6 pin 6.

VCC is turned OFF when the HYBRID has not had any input activity for a preset length of time (~15 minutes) . The microprocessor (U7) turn OFF signal, is a level signal (U15, pin 4), that C46 and R18 (pulse differentiator) turns into a pulse. A pulse is used to allow the turn ON signal to change the output state of U10A after a turn OFF signal is established. Since the microprocessor (U7) is affected by VCC turn OFF and could cause the turn off line to toggle during power down, the turn OFF signal is latched high by U15. Capacitors C6 and C44 provide power supply filtering to and from U10 and U17.

Microprocessor Data Expansion U15, C16

The microprocessor (U7) does not have enough output lines so a serial in, parallel output shift register with latched outputs (U15) provide the additional output lines . The serial data bus provides the input data (U15, pin 14) and the serial data clock (U15, pin 11) provides the clocking signal. The output latch of U15 is clocked by U7, pin 11. U15 is powered from C+, which is available at all times. This is required because some of the outputs of U15 need to be maintained when VCC is powered down (e.g. the light sensor detector gain) . Capacitor C16 provides power supply filtering to and from the shift register.

High Voltage Regulator (HVREG) U5, Qll, R40, Q14, R35, C38, C26,

LI, D10, C33, R16, R17, C33, R29, R15, R34, Q4, Q5, U2, C13

The high voltage regulator circuit provides an adjustable output voltage in the range of 6 to 16 volts. This voltage is used to control the darkness of the surface mode LCD. Shades 10, 11 and 12 of the HYBRID are primarily set by the voltage generated from HVREG (U5) . U5, R35, C38, C26, LI, D10, C33 are the same topology as the VCC switching regulator, and function in the same manner. The voltage divider feedback network for the HVREG is different than the VCC regulator. R16, R17 are the high voltage leg of the divider. C35 is added to compensate for the capacitance in the lower half of the divider. The lower leg of the voltage divider has R29 in series with the series combination of the digitally controlled potentiometers in U2. This combination provides one of four selectable voltage output windows for the HVREG (U5) . A second voltage window is achieved by applying a voltage to Q4. This places R34 in parallel with R29 reducing the value of the lower leg of the voltage divider. Lowering the resistance of the lower divider leg causes the regulator output to increase. In turn, applying a voltage to Q5 while holding the gate of Q4 off, places R34 in parallel with R29 creating a different output voltage window. Turn both Q4 and Q5 on generates the fourth possible voltage window.

The digitally controlled potentiometers in U2 are connected in series to provide sufficient resistance for the microprocessor (U7) to adjust the output voltage of the regulator. The potentiometers of U2 are controlled in the same manner as the potentiometers in U3 (serial input data, serial data clock, chip select) . The chip select input of U2 is from U15 pin 5. Qll, R40 and Q10 are the ON/OFF voltage switch for the HVREG. U15, pin 3 under the control of the microprocessor (U7), controls the switch. A high level on the gate of Q14 turns Qll ON and a low level turns Qll OFF. The HVREG is turned on when the HYBRID is in the dark mode and turned off when the HYBRID is in the clear mode.

Very High Voltage (VHV) Supply U12D, C20, D18, D19, C47, Cl, C2, C3, C4, D2, D3, D , D8,

C24, C25, Q12, R43, Q9, R28, C32, D9

The very high voltage supply is used when the surface mode LCD is changed from the clear state to the dark state. This voltage provides for a very dark shade in a very short length of time. The VHV output is 35-40 volts.

D18, C47 and C20 are the classic design of a capacitor voltage doubler. C47 is the drive capacitor being driven by the 23KHZ signal from Ull pin 9. Diode D102 allows the voltage on C20 to start at VCC reducing the overall power requirements of C47. The output of this voltage doubler is the supply voltage for the CMOS level shifter U12. U12 pin 9 (DIN) is driven with a 1 kHz signal from Ull, pin 5. The output of U12 pin 10 (DOUT) drives another classical capacitor voltage multiplier with enough stages to achieve 5 times the voltage gain. Cl is the drive capacitor in the 5 times multiplier. C2, C3, and C4 are the pumping capacitor, while C21, C22, C23 and D2, D4, D8 provide voltage storage. The output half of D8 rectifies the output of C4 and stores the voltage in the parallel combination of C24 and C25. The very high voltage is stored until the surface mode LCD is switched to dark.

The high voltage enable signal (HVEN) is generated by the microprocessor (U7 pin 4) in response to a light sensor detector output. The HVEN signal switches the very high voltage (VHV) to the surface mode display driver by means of Q9 R43 and Q12. The HVEN signal is a high level for the duration of time that the display needs to remain dark. C32 and R20 (differentiator) change the level signal into a pulse. The pulse is needed to turn off the VHV and allow the shade of the surface mode LCD to be controlled by HVREG (U5) . D9 is a blocking diode that keeps the VHV from affecting the HVREG circuit.

Surface Mode (SM) LCD display driver The SM LCD is driven by U4. The SM LCD is similar to the TN LCD in that enough voltage differential between the back plane and a segment of the SM LCD will cause a segment to be dark. The SM LCD differs from the TN LCD in that the SM LCD darkness is linear with the voltage across it and the clear state of the SM LCD requires a small voltage differential. (The TN LCD requires a zero voltage differential to be clear.) U4 is designed to provide the drive for SM LCD devices. U4 has two voltage inputs for SM LCD drive. LVIN (U4 pin 1) is the low voltage input for the clear state of the SM LCD. HVIN (U4 pin 7) is the high voltage input for the dark state. HVOUT1 (U4 pin 8) and HVOUT2 (U4 pin 5) are complementary (inverted) outputs that drive the SM LCD segment (1/2 shutter) . The outputs are always an inversion of each other because the SM LCD always requires a voltage differential. The input logic of U4 is supplied power from VCC through (U4 pin 6) . The control input of HVEN (U4, pin 3) switches the output between high voltage and low voltage. The POL input (U4 pin 2) controls the switching rate of the driver (i.e. the frequency of the drive signal) . The switching rate comes from the microprocessor (U7 pin 5) and is switched at 64 transitions (32 Hz) during shades 9, 10 and 11. This rate avoids flicker. In shade 12 the rate is reduced to l/16th the normal rate to minimize power consumption.

Input Selector Switches SW1, SW2, SW3, RI, R36, R2, R37, R6, R38, U16 A&B, C5

The HYBRID has three user controlled parameters of operation. They are SHADE (darkness of the lens), DELAY (how long the display stays dark after the light sensor detector quits signaling the microprocessor), and SENSITIVITY (level of light that causes the light sensor detector to trigger) . When any switch is pressed, the VCC power control is signaled to be ON by logically combining all of the switches with OR gates (U16 A&B) . RI, R2 and R6 provide logic low levels when the switches are open. R36, R37, R38 are in series with the inputs of the microprocessor (U7, pins 16, 17, 18) to limit the current drawn from the switch supply (C+) when the microprocessor (U7) is powered OFF. When the microprocessor (U7) is powered ON, the resistors work with RI, R2, R6 to provide a logic low level when a switch is not pressed. Capacitor C5 provides power supply filtering to and from U16.

When a switch is pressed, the microprocessor (U7) performs a software debounce to eliminate false switch contacts. The software then increments the parameter selected and changes the TN LCD display segment to provide a feedback and indicate to the operator a change has occurred.

Low Voltage Power Supplies Battery, C41, Dll, Solar Cell, C42, C40, VRl, D15, D16, D17, C43

The HYBRID uses three low level power supplies. The first is A+ (raw battery) used in the low battery detection circuit and the voltage bias circuit for the light sensor detector gain and comparator. C41 provides filtering of this supply.

B+ (Dll) is the combination of A+ and the output of the solar cell. C42 and C40 filter this supply. VRl is a precision voltage reference that draws minimal power below 4 Vdc. VRl is required to keep the solar cell from over voltaging the VCC regulator in very high light conditions. VRl is similar to a zener diode in that it shunts current through itself above a threshold level. At high light levels the extra current drawn by VRl hold the solar cell voltage to the required level.

C+ is the combination of A= (D16) , B+ (D15) and VCC (D17) . This supply powers all of the devices that remain on when VCC power is removed. VCC is used in this supply to maintain voltage compatible levels between devices when VCC is ON. A+ is routed through a separate diode (D16) to minimize the voltage drop when B+ is not being powered by the solar cell. C43 provides filtering of this supply.

Light Sensor D13, D14, R3, R25, C7, Ql, Q2, R14

The light sensor is the parallel combination of two photo diodes (D13, D14) operated in the photo current mode. The photo current mode requires the photo diode to be reverse biased allowing the photo current produced in the photo diode to change in response to the light falling on the semiconductor junction of the diode. R25, C7, Ql, Q2 and R14 are configured in a DC current sink. R25 and C7 make a low pass filter that removes the AC component from the signal. Their output provides bias into the transistors in a Darlington configuration. The emitter resistor, R14, provides additional circuit output resistance over other designs, maintaining the current sink output resistance at moderate levels of photo current signal. This improves the linearity and extends the range of the photo diodes at higher photo currents.

R3 limits the resistance the photo diodes work into a low photo current level. The Darlington current sink has a very high resistance (megaohms) at low photo current levels and decreases to a moderate level at tens of microamps of photo current. This causes the linearity of the photo current to voltage to be very non-linear. R3 sets a maximum resistance the photo diode will see. The combination of R3 and R14 in the circuit maintains the linearity of the photo diode to 3 db over 3 decades of photo current.

Light Sensor Gain U8B, C30, R39, RIO, R22, Q3, R23, Q6,

R12

The low current operational amplifier (U8B) is configured as a positive gain amplifier. The positive input (U8 pin 5) has a single pole high pass filter (C30, R39) attached. This filter minimizes frequencies below 100 Hz. Gain is controlled by the feedback resistor network (R10, R22, Q3, R23, Q6, R12) . R12 is always in the circuit setting the minimum gain. Q3 acts as a switch adding R22 in parallel with R12 increasing the gain. In the same fashion Q6 and R23 increase the amplifier gain. More gain cannot be achieved with using a smaller resistor due to the gain/frequency limitations of the amplifier itself. The junction of Q3, Q4 and R12 are attached to a voltage bias point above ground. Control of Q3 and Q6 is provided by the microprocessor (U4) through U15 pins 1 and 2.

Light Sensor Detector and Bias U8A, R32, Rll, C15, R28, C14,

R13, U17 C&D, U10B, C45, R30

The second operational amplifier in U8 is configured as a comparator. The AC signal from U8B rides on a DC bias signal into the positive input of the amplifier (U8A pin 3) . The negative input (U8 pin 2) has a series resistor to the bias network that is a voltage level above the gain amplifier's DC bias point. This difference is the comparator threshold level. No positive feedback is used to prevent oscillation of the comparator (U8A) since any change in output triggers a D-type Flip Flop (U10B0 to capture the event. The output of the comparator (U8A pin 1) is inverted in U17C since U10 uses negative logic for its active input. The output of U10B (pin 8) signals the microprocessor (U7) that a light sensor detection has occurred.

The light sensor detector signal is reset by the microprocessor (U7) . C45 and R30 are used to minimize the light sensor detector output reset pulse and to block any DC signal into U17D when the power OFF occurs. U17D inverts the reset signal for U10B.

The inventors have described the invention in the context of a preferred embodiment. However, the invention is not to be considered as limited to the particular embodiment disclosed herein. Various changes and modifications such as would be apparent to those of ordinary skill in the art are included as part of the invention which is limited only by the scope of the claims appended hereto, and their legal equivalents.

Claims

What Is Claimed Is:

1. A welding helmet having a lens through which the wearer views his work, said lens having a plurality of liquid crystal filters, at least two of said filters being electrically operable to vary their shade, and a control circuit for operating said at least i two filters, said control circuit being configured to actuate said filters using control signals having different electrical characteristics for at least one of said shades.

2. The welding helmet of claim 1 wherein said control circuit is configured to actuate said filters with control signals having different frequencies.

3. The welding helmet of claim 1 wherein said control is further configured to adjust the light transmission of said filters to select one of a plurality of shades by adjusting the electrical control signal to less than all of said shades.

4. The welding helmet of claim 3 wherein said control includes a digitally programmable control device.

5. The welding helmet of claim 4 wherein said control circuit includes at least one variable electrical device for adjusting the electrical signal as necessary to properly actuate one of said filters for one of a preselected shade setting, said at least one

5 variable electrical device being connected to said digitally programmable control device and configured so that said digitally programmable control device adjusts said variable electrical device as it executes a stored program.

6. The welding helmet of claim 3 wherein said lens includes two filters, one of said filters consuming more energy than the other of said filters to achieve the same level of light transmission therethrough, and wherein said control circuit is configured to

5 actuate said more energy consuming filter with a control signal having a lower frequency than the control signal used for said other filter.

7. The welding helmet of claim 6 wherein said control circuit is configured to produce electrical actuation signals which are in phase.

8. A lens assembly for a protective helmet or the like, said lens assembly including a plurality of filters, said lens assembly including a control circuit configured to actuate said filters with electrical signals having different characteristics in order to achieve at least one of a plurality of preselected shade levels.

9. The lens assembly of claim 8 wherein said control circuit is configured to produce electrical actuation signals having different frequencies.

10. The lens assembly of claim 9 wherein one of said filters is a TN filter and the other of said filters is an SM filter, said control circuit being configured to actuate the SM filter with an electrical signal having a lower frequency than the electrical signal i used to actuate the TN filter.

11. The lens assembly of claim 9 wherein said control circuit includes a digitally programmable device.

12. The lens assembly of claim 11 wherein said control circuit is configured to produce electrical actuation signals which are in phase.

13. The lens assembly of claim 8 wherein said control circuit is configured to produce electrical actuation signals having different characteristics for only one of said shade levels.

14. A welding helmet having a lens through which the wearer views his work, said lens having a plurality of liquid crystal filters, at least two of said filters being electrically operable to vary their shade, and a control circuit for operating said at least

5 two filters, said control circuit being configured to adjust said lens to one of a plurality of shades by adjusting the shade of less than all of said filters.

15. The welding helmet of claim 14 wherein said control circuit is configured to adjust said lens to one of a plurality of shades by adjusting the shade of only one of said filters.

16. The welding helmet of claim 15 wherein said lens includes only two of said filters.

17. The welding helmet of claim 16 wherein said control circuit includes a digitally programmable device.

18. The welding helmet of claim 14 wherein said control circuit is configured to adjust the shade of said filters by producing electrical signals having different characteristics.

19. The welding helmet of claim 18 wherein said control circuit is configured to adjust the shade of said filters by producing electrical signals having different frequencies.

20. The welding helmet of claim 19 wherein said lens includes only two filters and wherein one of said filters consumes more power than the other of said filters to achieve the same shade, and wherein said control circuit is configured to apply the electrical signal of lower frequency to said more power consumptive filter.

21. The welding helmet of claim 20 wherein said control circuit is configured to apply electrical signals of different frequency to said filters only for a limited number of an available number of shades to which said lens may be adjusted.

22. The welding helmet of claim 21 wherein said control circuit is configured to apply electrical signals of different frequency to said filters only for one of said shades.