WO2000059088A1

WO2000059088A1 - Power line protection devices and methods capable of preventing false fault reporting

Info

Publication number: WO2000059088A1
Application number: PCT/US2000/007217
Authority: WO
Inventors: Justin Chiang; Adrian I. Cogan; Paul Wiener
Original assignee: Tyco Electronics Corporation
Priority date: 1999-03-29
Filing date: 2000-03-17
Publication date: 2000-10-05
Also published as: TW478232B

Abstract

The present invention provides an improved power line protection device (50) and method suitable for protecting data bus and power lines such as in the USB (Universal Serial Bus) configurations and other power management circuits. The invention eliminates false fault flag signals generated when large capacitive loads are present. According to the invention, an integrated switch device (60) is provided and used in the improved power line protection device. The integrated device is controllable by an external enable signal for switching on and off power supplied on a power line. The switch device comprises a fault detection circuit, a switch (61) and an external flag generation circuit (70). The fault detection circuit detects fault conditions (e.g., an overcurrent condition) and generates an internal flag signal upon detecting a fault condition. The switch is controllable by the external enable signal and the internal flag signal for switching on and off the power supplied to the power line. The external flag generation circuit is connected to the fault detection circuit to receive the internal flag signal. If the internal flag signal lasts longer than a predetermined duration, the external flag generation circuit generates an external flag signal after the predetermined duration has elapsed since receiving the internal flag signal. In this way, false fault reporting is effectively prevented.

Description

POWER LINE PROTECTION DEVICES AND METHODS CAPABLE OF PREVENTING FALSE FAULT REPORTING

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to two commonly assigned applications being filed on the same day as this application, by the same inventors, entitled "Power Line Protection Devices and Methods for Providing Overload Protection to Multiple Outputs" and "Integrated Switch Device with Enhanced Functionalities," respectively, attorney's docket numbers MP1687-US1 and MP1689-US1, respectively. The disclosures of these two applications are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The invention relates generally to protection devices, and more particularly to those used in computer power bus lines, which power downstream electronic components and power management circuits.

Modern technologies have allowed more and more computers to be connected to one another by way of networking. Each computer may have numerous peripheral devices connected to it. Peripheral devices include not only the traditional ones such as a keyboard or a mouse, but also those with new applications, e.g., a digital camera. In a typical network system, a hub is connected to a number of nodes, each of which may be connected to a number of sub-nodes. Each node or sub-node may be a computer or a peripheral device. Each sub-node may be connected to additional sub-sub-nodes, and so on. In such a network system, power is typically distributed to the various nodes and sub-nodes, etc. One example of such a network environment relates to the recent USB (Universal Serial Bus) standards, e.g., USB-IF, USB Specification, Rev. 1.1, 1998.

In such a network system, each network node is continuously monitored. Normal operation as well as fault conditions (e.g., overcurrent, over-temperature, under-voltage, etc.) are constantly reported to a control circuit. When a fault condition, e.g., overcurrent condition, occurs at one node or sub-node, it is important that any point of failure not affect the operation of the remaining portions of the network system. In other words, the failure must be localized and isolated in order to achieve high performance in a network system.

Various power bus line protection devices have been proposed. Figure 1 illustrates a typical power management and protection device used in a personal computer. In Figure 1, a host 10 communicates with a peripheral device 11 via a USB port 12. Peripheral device 11 communicates with another peripheral device (not shown) via another USB port 32. USB port 12 includes a power line 13, two data lines 14,15 and a return line 16. Similarly, USB port 32 includes a power line 33, two data lines 34,35 and a return line 36. Peripheral device 11 includes a power management and protection device 20, which includes a USB controller 22, a power integrated circuit (PIC) switch 30 and external pull-up resistors R1,R2. Controller 22 may be a TUSB 2040 or TUSB 2070 device which is commercially available from Texas Instruments of Dallas, Texas. An example of PIC switch 30 is the MIC 2526 power switch which is commercially available from Micrel, Inc., San Jose, California. PIC switches generally include self-protection mechanisms and are typically used in power management in computer hardware environments, such as the USB applications.

Host 10 periodically checks peripheral device 11 and other connected peripheral devices (not shown) to determine their status, e.g., whether there is a data request, a fault condition report, etc. Under normal conditions, controller 22 enables switch 30 by sending an active VEN signal (low or high) via its PC (power control) node, and power is supplied on power line 33 to the other peripheral device via port 32. When an overcurrent condition occurs, controller 22 receives a fault flag signal VFG from PIC switch 30, via the OC (overcurrent) node and informs host 10 of the fault condition. Host 10 then instructs controller 22 to disable PIC switch 30 by sending a complementary active VEN signal to the switch, via the PC node, to turn off the power on power line 33. In some cases, it is also possible for controller 22 to turn off the power on power line 33 independent of any instructions from host 10, while simultaneously reporting the fault condition to host 10. By turning off the power, the fault is isolated and the switch is protected.

The circuit in Figure 1 suffers from a serious drawback when a peripheral device or a load with a large internal capacitance, e.g., a scanner or a digital camera, is connected to port 32, as in many practical applications. Such a drawback is illustrated in Figures 2A and 2B. Figure 2A illustrates the operation of the circuit in Figure 1 in which host 10 provides instructions to controller 22 for turning off the power on the power line when a fault condition occurs. During the period between 0 and tl, PIC switch 30 is operated under the normal condition and VEN is active (assuming an active VEN is at high level). When power is applied to such a load, while the internal capacitance of the load is being charged and the load voltage VL increases, the inrush load current II may exceed the current limit of PIC switch 30. When the current limit is reached at time tl, PIC switch 30 sets a fault flag signal VFG and sends it to controller 22 via the OC node, indicating an overcurrent condition. This overcurrent condition is communicated to host 10, which then instructs controller 22 to disable PIC switch 30 by sending an inactive VEN signal (assuming an inactive VEN is at low level) to the switch at tl . The power on power line 33 is thus turned off to protect the switch. Once the internal capacitance of the load is fully charged at time t2, the load current II will be reduced to a lower, nominal value. After I decreases below the current limit of PIC switch 30 at t2, the switch resets fault flag signal VFG and so informs controller 22, which then communicates to host 10. Host 10 in turn instructs controller 22 to send an active VEN signal to PIC switch 30 at t2 to turn the power on. This sequence of setting and resetting the fault flag signal to indicate, respectively, the presence and absence of a fault condition is very undesirable, since the overcurrent condition due to the large internal capacitance of the load or peripheral device lasts only for a very short time period, e.g., 2 to 10 ms. It unnecessarily interrupts the power supplied to the peripheral device via the USB port, with the result that the peripheral device may never reach the normal operation status.

Figure 2B illustrates the operation of the circuit in Figure 1 in which controller 22 controls, independent of any instructions from host 10, switching off the power on the power line when a fault condition occurs. During the period between 0 and t_a, PIC switch 30 is operated under the normal condition and VEN is active (assuming again an active VEN is at high level). When power is applied to a peripheral device or a load with a large internal capacitance, while the internal capacitance of the load is being charged and the load voltage VL increases, the inrush load current II may exceed the current limit of PIC switch 30. When the current limit is reached at time t_a, PIC switch 30 sets a fault flag signal VFG and sends it to controller 22 via the OC node, indicating an overcurrent condition. After a time delay of tj, controller 22 disables PIC switch 30 by sending an inactive VEN signal (assuming again an inactive VEN is at low level) to the switch at t_j- and simultaneously reports the fault condition to host 10. The power on power line 33 is thus turned off to protect the switch. At tj,, the load voltage VL decreases, the load current II is reduced to zero, and fault flag signal VFG is reset. The same drawback is again present since the overcurrent condition due to the large internal capacitance of the load or peripheral device lasts only for an extremely short duration, e.g., 100 μs. The consequence is that the peripheral device may never reach the normal operation status.

A solution has been proposed to the above drawback and is illustrated in Figure 3. In Figure 3, an external fault flag delay circuit 31 is connected between USB controller 22 and PIC switch 30. Circuit 31 provides a delayed fault flag signal VFG' to USB controller 22, in order to minimize false fault reporting.

However, adding such an external delay circuit in the circuit of Figure 1 is very expensive and results in complex circuit structure. Moreover, the use of external pull-up resistors further adds complexity to the circuit structure.

Therefore, there is a need to provide a simple, reliable and cost-effective solution to prevent such false fault reporting when a peripheral device with a large internal capacitance is connected to a peripheral port.

SUMMARY OF THE INVENTION

The present invention solves the above problem by providing an integrated switch device and a protection device that report a fault condition (e.g., an overcurrent condition) to an external control element only if the fault condition lasts longer than a predetermined duration. A typical range for the predetermined duration is between 2 to 10 ms. In this way, the false fault reporting problem associated with the use of a conventional power line protection device is effectively eliminated.

According to an embodiment of the present invention, an integrated switch device is provided and is controllable by an external enable signal for switching on and off power supplied on a power line. The switch device comprises a fault detection circuit for detecting a fault condition (e.g., an overcurrent condition) and for generating an internal flag signal upon detecting the fault condition; a switch, controllable by the external enable signal and the internal flag signal, for switching on and off the power supplied on the power line; and an external flag generation circuit, coupled to the fault detection circuit, for receiving the internal flag signal and if the internal flag signal lasts longer than a predetermined duration, for generating an external flag signal. According to one aspect of the integrated switch device of the invention, if the internal flag signal lasts longer than the predetermined duration, the external flag generation circuit generates the external flag signal after the predetermined duration has elapsed since receiving the internal flag signal. Furthermore, if the internal flag signal lasts longer than the predetermined duration, the external flag generation circuit resets the external flag signal if the fault condition disappears.

According to another aspect of the integrated switch device of the invention, the external flag generation circuit comprises a logic delay circuit for generating a pulse with the predetermined duration upon receiving the internal flag signal; a logic AND gate for generating a control signal, the AND gate having an input coupled to receive the internal flag signal and an inverted input coupled to receive the pulse from the logic delay circuit; and a power switch, controlled by the control signal from the AND gate, for generating the external flag signal.

According to yet another aspect of the integrated switch device, the switch device further comprises a first input terminal for receiving the power supplied on the power line; a second input terminal for receiving the external enable signal; an output terminal for outputting the external flag signal; a first pull-up resistor connected between the first and second input terminals; and a second pull-up resistor connected between the first input terminal and the output terminal. The switch device also includes a voltage limiter connected between the output terminal and a ground level.

According to another embodiment of the invention, a protection device is provided and is controllable by a host for protecting a power line. The protection device comprises a switch circuit and a controller. The switch circuit is controllable by an external enable signal for switching on and off power supplied on the power line. The switch circuit comprises a fault detection circuit for detecting a fault condition (e.g., an overcurrent condition) and for generating an internal flag signal upon detecting the fault condition; a switch, controllable by the external enable signal and the internal flag signal, for switching on and off the power supplied on the power line; and an external flag generation circuit, coupled to the fault detection circuit, for receiving the internal flag signal and if the internal flag signal lasts longer than a predetermined duration, for generating an external flag signal. The controller is coupled to the switch circuit and is responsive to the external flag signal for providing the external enable signal to control the switch circuit. Upon detecting the external flag signal, the controller reports the fault condition to the host and causes the switch circuit to switch off the power.

According to one aspect of the protection device of the invention, if the internal flag signal lasts longer than the predetermined duration, the external flag generation circuit generates the external flag signal after the predetermined duration has elapsed since receiving the internal flag signal. Furthermore, if the internal flag signal lasts longer than the predetermined duration and if the fault condition disappears, the external flag generation circuit resets the external flag signal to cause the controller to report disappearance of the fault condition to the host. It also causes the controller to enable the switch circuit to switch on the power.

According to yet another embodiment of the invention, a method for protecting a power line is provided. The method comprises the steps of detecting a fault condition (e.g., an overcurrent condition); generating an internal flag signal upon detecting the fault condition; if the internal flag signal lasts longer than a predetermined duration, generating an external flag signal; and causing switching off the power supplied on the power line upon detecting the external flag signal. The method also includes a step of reporting the fault condition upon detecting the external flag signal.

According to one aspect of the method of the invention, the step of generating an external flag signal generates the external flag signal after the predetermined duration has elapsed since the generation of the internal flag signal.

According to another aspect of the method of the invention, the method further comprises, if the flag signal lasts longer than the predetermined duration and the fault condition disappears, the steps of resetting the external flag signal; reporting the disappearance of the fault condition; and switching on the power supplied on the power line.

Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings wherein like reference symbols refer to like parts:

Figure 1 shows a conventional power management and protection device used in a personal computer;

Figures 2 A and 2B illustrate the operations of the device in Figure 1 under different circumstances;

Figure 3 shows a conventional solution to the drawback of the device in Figure 1 ;

Figure 4 shows a functional block diagram illustrating an application of a power protection device according to an embodiment of the present invention;

Figure 5 shows a PIC switch according to an embodiment of the present invention;

Figure 6 shows a logic truth table illustrating the operation of a PIC switch according to an embodiment of the present invention; and

Figures 7A and 7B are timing diagrams illustrating the operations of the PIC switch according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Figure 4 shows a functional block diagram illustrating an application of a power protection device 50 according to an embodiment of the present invention. For simplicity, description of the elements with the same reference numerals as those illustrated in Figure 1 is omitted. Power protection device 50 includes a USB controller 22 and a power integrated circuit (PIC) switch 60.

Figure 5 shows an exemplary embodiment of PIC switch 60. PIC switch 60 comprises a current sensing resistor Rs, pull-up resistors RE and RF, a voltage limiter 58, a power switch 61, a gate control circuit 62, a current limit circuit 64, and an external flag generation circuit 70. Voltage limiter 58 may be a 3.5 V zener diode, for example and is used for protecting the input terminal OC of USB controller 22. Current limit circuit 64 is a conventional circuit and monitors the current supplied to the load. Current limit circuit 64 will send a control signal to gate control circuit 62 if overcurrent occurs. As will be understood by those skilled in the art, PIC switch 60 also includes other conventional circuits (not shown) which provide basic circuit functions, such as voltage reference, etc. Moreover, in an alternative embodiment, the PIC switch also includes conventional circuits for detecting over-temperature, overvoltage, undervoltage conditions, etc. and for controlling switching off the power supplied to the load in response to any one of these conditions.

Under a normal condition, VEN is active (assuming an active VEN is at logic 1) and power switch 61 is turned on. Thus, power is supplied from +Vbus to another peripheral device (not shown) via PIC switch 60, as illustrated in Figure 4. In the case of overcurrent, current limit circuit 64 sends a control signal to gate control circuit 62 which will turn off switch 61. Current limit circuit 64 also generates an internal flag signal VIF, indicating an overcurrent condition. The internal flag signal VIF, however, is not directly sent to USB controller 22 (in Figure 4), but is instead sent to external flag generation circuit 70. External flag generation circuit 70 comprises a logic delay circuit 72, an AND gate 74 with an inverted input terminal connected to the output VD of logic delay circuit 72, and an output transistor 76 connected to the output VA of AND gate 74. Upon receiving an internal flag signal VIF, logic delay circuit 72 generates a pulse VD with a predetermined duration which may be 2 to 10 ms, for example. VIF and VD are input to AND gate 74, which produces an output VA that controls output transistor 76. In this embodiment, logic delay circuit 72 may be a monostable circuit, such as a "single-shot" circuit, which generates a pulse signal with a duration of 2 to 10 ms, upon being enabled.

In Figure 5, any of pull-up resistors RE and RF and voltage limiter 58 may be disconnected, at the option of the customer, by way of masking at the time of fabrication to accommodate circuit boards with pre-mounted external pull-up resistors and/or voltage limiter.

Figure 6A shows timing diagrams illustrating the operation of external flag generation circuit 70 when overcurrent briefly occurs. As shown in Figure 6A, between the time period 0 to Tl there is a normal operating condition in which no overcurrent is present, and VIF is inactive (assuming an inactive VIF signal is at logic 0). Since there is no overcurrent, logic delay circuit 72 does not output any pulse and its output VD is at logic 0. Thus, the output VA of AND gate 74 is also at logic 0. Therefore, output transistor 76 is in the off state, and no external flag is generated so that VEF remains at logic 1 (assuming an active external flag is at logic 0, i.e., VEF = logic 0).

As illustrated in Figure 6 A, overcurrent occurs at Tl and lasts for a brief period of (T2-T1). The internal overcurrent flag VIF is set active (assuming an active VIF is at logic 1) by current limit circuit 64 for a corresponding time period of (T2-T1). Upon receiving an active VIF, logic delay circuit 72 generates a pulse VD with a predetermined duration of (T3-T1). Therefore, the output VA of AND gate 74 is at logic 0 for the predetermined duration of (T3-T1). As a result, during the time period of (T3-T1), output transistor 76 remains in the off state and VEF stays at logic 1 during this time period. Since the overcurrent did not last beyond the predetermined time period of (T3-T1), no external overcurrent signal is generated, and false fault reporting is prevented.

Figure 6B shows timing diagrams illustrating the operation of external flag generation circuit 70 when overcurrent persists, e.g., in a situation in which a resistive load RL is connected to PIC switch 60. As shown in Figure 6B, between the time period 0 to Tl, there is a normal operating condition, as in Figure 6A. Overcurrent occurs at Tl and lasts until T4. Thus, VIF is set active for the time period (T4-T1) which is longer than the predetermined duration of (T3-T1) in which pulse VD is active. This indicates a normal overcurrent condition.

In Figure 6B, during the predetermined duration of (T3-T1), the output VA of AND gate 74 is at logic 0, as in Figure 6 A. At T3, pulse VD is reset. Between T3 and T4, since VIF is still at logic 1 but VD is reset logic 0, the output VA of AND gate 74 becomes logic 1 , which turns on output transistor 76 and sets the external flag signal VEF to active, i.e., logic 0. The overcurrent condition, as signaled by the active VEF, is then communicated to USB controller 22.

As can be seen from the above, external flag generation circuit 70 essentially cuts off a predetermined initial portion of the internal flag signal VIF and outputs an external flag signal VEF to controller 22, representing any remaining portion of the internal flag signal VIF. Thus, controller 22 will not be able to receive any indication of overcurrent until after a predetermined time duration has elapsed since the generation of the internal flag signal VIF . Figures 7A and 7B show timing diagrams illustrating overcurrent conditions and the operation of PIC switch 60. Figure 7A illustrates how PIC switch 60 operates in the presence of a large capacitive load. Before overcurrent is detected, USB controller 22 enables PIC switch 60 with an active VEN (assuming an active VEN is at high level). When a large capacitive load is connected to PIC switch 60, the load voltage VL increases, and the load experiences a large initial load current II which quickly reaches the current limit of PIC switch 60. When II reaches and exceeds the current limit at Ta, an internal flag signal VIF is generated and set active by current limit circuit 64. At this time, upon receiving an active VIF, logic delay circuit 72 generates a pulse VD with a predetermined duration of (Tc-Ta). The internal flag signal VIF remains set for as long as the load current II is at or above the current limit of PIC switch 60.

At time Tb, the capacitive load is fully charged, the load voltage VL becomes constant, and the load current II is reduced to a lower current value below the current limit of PIC switch 60. At this time, the overcurrent condition disappears, which causes current limit circuit 64 to reset the internal flag signal VIF to a low level.

At time Tc, external flag generation circuit 70 would output any remaining portion of VIF that lasts longer than the predetermined duration of the pulse VD. In this case, since the duration of the internal flag signal VIF is less than that of the pulse VD, the external flag signal VEF output by external flag generation circuit 70 remains inactive at logic 1. In this way, external flag signal generation circuit 70 effectively eliminates any false fault reporting. Moreover, USB controller 22 does not have to act on any internal overcurrent flag signal that lasts less than the predetermined duration of the pulse. Thus, VEN remains set. According to the present invention, a typical range for the predetermined duration is 2 to 10 ms, which ensures normal operation.

Figure 7B illustrates how PIC switch 60 operates in the presence of a resistive load. Before overcurrent is detected, USB controller 22 enables PIC switch 60 with an active VEN. AS the load voltage VL increases, the load current II increases correspondingly. At time Ta, II reaches the current limit of PIC switch 60. At this time, the internal flag signal VIF is set active by current limit circuit 64. An active VIF causes logic delay circuit 72 to generate, at Ta, a pulse VD with a predetermined duration of (Tc- Ta). At time Tc, the pulse VD is reset. Since the overcurrent condition persists, i.e., VIF is still at a high level, the external flag signal VEF is set active at logic 0 by external flag generation circuit 70. The active VEF is communicated to USB controller 22 and then to host 10. Host 10 instructs USB controller 22 to reset VEN to an inactive level (logic 1) at Tc, to turn off the power supplied on power line 32 and protect PIC switch 60.

Alternatively, USB controller 22 can reset VEN, independent of any instructions from host 10. In Figure 7B, as in Figure 7A, external flag generation circuit 70 allows USB controller 22 to receive any remaining portion of the internal flag signal VIF only after a predetermined duration of (Tc - Ta) since the generation of the pulse VD. Thus, by using the present invention, the overall operation efficiency can be achieved, while keeping all circuit components in their normal operating ranges.

While the invention has been described in conjunction with several specific embodiments, it is evident to those skilled in the art that many further alternatives, modifications and variations will be apparent in light of the foregoing description. Thus, the invention described herein is intended to embrace all such alternatives, modifications and variations as may fall within the spirit and scope of the appended claims.

Claims

What is claimed is:

1. An integrated switch device, controllable by an external enable signal, for switching on and off power supplied on a power line, the device comprising:

a fault detection circuit for detecting a fault condition and for generating an internal flag signal upon detecting the fault condition; a switch, controllable by the external enable signal and the internal flag signal, for switching on and off the power supplied on the power line; and an external flag generation circuit, coupled to said fault detection circuit, for receiving the internal flag signal and if the internal flag signal lasts longer than a predetermined duration, for generating an external flag signal.

2. The device of claim 1 wherein if the internal flag signal lasts longer than the predetermined duration, said external flag generation circuit resets the external flag signal if the fault condition disappears.

3. The device of claim 1 wherein said external flag generation circuit comprises:

a logic delay circuit for generating a pulse with the predetermined duration upon receiving the internal flag signal, a logic AND gate for generating a control signal, said AND gate having an input coupled to receive the internal flag signal and an inverted input coupled to receive the pulse from said logic delay circuit, and a power switch, controlled by the control signal from said AND gate, for generating the external flag signal.

4. The device of claim 1, further comprising:

a first input terminal for receiving the power supplied on the power line; a second input terminal for receiving the external enable signal; an output terminal for outputting the external flag signal; a first pull-up resistor connected between said first and second input terminals; and a second pull-up resistor connected between said first input terminal and said output terminal.

5. The device of claim 4, further comprising a voltage limiter connected between said output terminal and a ground level.

6. An integrated switch device, controllable by an external enable signal, for switching on and off power supplied on a power line, the device comprising: a fault detection circuit for detecting a fault condition and for generating an internal flag signal upon detecting the fault condition; a switch, controllable by the external enable signal and the internal flag signal, for switching on and off the power supplied on the power line; and an external flag generation circuit, coupled to said fault detection circuit, for receiving the internal flag signal and if the internal flag signal lasts longer than a predetermined duration, for generating an external flag signal, said external flag generation circuit comprising:

7. The device of claim 6 wherein the fault condition includes an overcurrent condition.

8. A protection device, controllable by a host, for protecting a power line, the device comprising:

a switch circuit, controllable by an external enable signal, for switching on and off power supplied on the power line, said switch circuit comprising:

a fault detection circuit for detecting a fault condition and for generating an internal flag signal upon detecting the fault condition, a switch, controllable by the external enable signal and the internal flag signal, for switching on and off the power supplied on the power line, and an external flag generation circuit, coupled to said fault detection circuit, for receiving the internal flag signal and if the internal flag signal lasts longer than a predetermined duration, for generating an external flag signal; and

a controller, coupled to said switch circuit and responsive to the external flag signal, for providing the external enable signal to control said switch circuit and upon detecting the external flag signal, for reporting the fault condition to the host and causing said switch circuit to switch off the power.

9. The device of claim 8 wherein if the internal flag signal lasts longer than the predetermined duration and if the fault condition disappears, said external flag generation circuit resets the external flag signal to cause said controller to report disappearance of the fault condition to the host and enable said switch circuit to switch on the power.

10. The device of claim 1, 7, or 8 wherein the predetermined duration is 2 to 10 ms .

11. The device of claim 1 or 8 wherein the fault condition includes an overcurrent condition.

12. A method for protecting a power line, the method comprising the steps of:

detecting a fault condition; generating an internal flag signal upon detecting the fault condition; generating an external flag signal if the internal flag signal lasts longer than a predetermined duration, preferably 2 to 10 ms; and causing switching off the power supplied on the power line upon detecting the external flag signal.

13. The method of claim 12, further including a step of reporting the fault condition upon detecting the external flag signal.

14. The method of claim 12 wherein the fault condition includes an overcurrent condition.

15. The method of claim 12, further comprising, if the flag signal lasts longer than the predetermined duration and the fault condition disappears, the steps of: resetting the external flag signal; reporting the disappearance of the fault condition; and switching on the power supplied on the power line.