JP2006025547A - Switching power supply device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching power supply device that can properly cope with an overcurrent in accordance with its cause in a range not to be excessive. <P>SOLUTION: In the switching power supply device that feeds current supply from a master power supply 1 to load 5, 6 by switching it by an output transistor 2 and smoothing it by a coil 3 and a capacitor 4, a voltage detected by an output current of the output transistor 2 is compared with reference values of two levels by comparators 11, 12, and counted by a counter 22 only in a period that the detected voltage reaches the second reference value after reaching the first reference value. When the detected voltage reaches the second reference value before the counter 22 reaches a first reference time, the current supply is stopped. When the counter 22 reaches a second reference time before the detected voltage reaches the second reference value, a duty ratio is lowered and the load 6 is disconnected. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a switching power supply apparatus that supplies power to a load via a switching element. More specifically, the present invention relates to a switching power supply device having a protection function against overcurrent.

Conventionally, some power supply devices of this type have a protection function in case of overcurrent due to a short circuit or the like. This is because, when an overcurrent flows, the load is destroyed or components inside the power supply device itself are destroyed. Therefore, for example, the device described in Patent Document 1 includes an element for detecting a short-circuit state. Then, when the state in which the short circuit signal is detected continues for a predetermined time or more, it is determined that the short circuit has occurred, and the circuit is stopped as a short circuit process. This protects against overcurrent caused by a short circuit.
No. 7-46981

  However, the above-described conventional power supply device has the following problems. That is, when a short circuit determination is made, a short circuit process is performed in which the circuit is stopped regardless of the cause. On the other hand, there are various causes of short-circuit determination, and depending on the cause, there is excessive protection. For example, when a short circuit occurs in some of a plurality of loads connected in parallel, power supply to a normal load that is not short-circuited is also stopped.

  The present invention has been made to solve the above-described problems of the prior art. That is, an object of the present invention is to provide a switching power supply apparatus that can take an appropriate measure so as not to become excessive according to the cause in the case of an overcurrent.

  The switching power supply device of the present invention made for the purpose of solving this problem includes a switching element that switches a current supply in response to a pulse signal, and a coil on a current path that is switched by the switching element. , A first overcurrent detection means for detecting an overcurrent of the switching element by comparison with a first reference value, and a first overcurrent of the switching element corresponding to a current larger than a current corresponding to the first reference value. The second overcurrent detection means for detecting by comparison with the reference value of 2 and any one of two or more types of abnormal signals depending on the time difference between the overcurrent detection by the first overcurrent detection means and the second overcurrent detection means An abnormality determination unit that outputs data and a protection unit that performs different protection operations according to an abnormality signal of the abnormality determination unit.

  In this switching power supply device, the current supplied to the load by the switching element is monitored by the first overcurrent detection means and the second overcurrent detection means. When the current increases more than usual and reaches or exceeds the current corresponding to the first reference value, the first overcurrent detection means detects the overcurrent. When the current further increases and reaches or exceeds the current corresponding to the second reference value, the second overcurrent detection means detects the overcurrent. Here, the abnormality determination unit outputs one of two or more types of abnormality signals depending on the time difference between the overcurrent detections by both detection means. Then, the protection unit performs a protection operation according to the abnormal signal.

  The reason why the content of the protection operation is changed according to the time difference of the overcurrent detection is that the content of the protection operation to be performed differs depending on the cause of the overcurrent. This is because the time difference of overcurrent detection differs depending on the cause of overcurrent. For example, consider the case where the current increases due to a short circuit in the load. In this case, there is still an inductance of the coil provided on the current path of the switching element. Therefore, the time difference is large because it takes time to increase the current. In this case, a relatively light protection operation is sufficient. On the other hand, consider the case where the coil itself is short-circuited. In this case, the coil inductance no longer exists. Therefore, since the current increases quickly, the time difference is small. In this case, the influence of overcurrent tends to be large, so the content of the protection operation needs to be suitable for it.

  Here, the abnormality determination unit includes a first abnormality signal output unit that outputs an abnormality signal when the time difference is shorter than the first reference time, and a first reference time after detection of the overcurrent by the first overcurrent detection means. It is desirable to have a second abnormal signal output unit that outputs an abnormal signal when the second overcurrent detection means does not detect an overcurrent even when a second reference time that is not shorter has elapsed. In this case, it is desirable that the protection unit has an output stop operation unit that turns off the switching element by the abnormality signal of the first abnormality signal output unit. In addition, a duty reduction operation unit that reduces the duty ratio of the pulse signal to the switching element by the abnormal signal of the second abnormal signal output unit, and current supply to at least some of the loads by the abnormal signal of the second abnormal signal output unit It is desirable to have at least one of the load separation operation part to interrupt.

  In this way, in the case of a rapid overcurrent, such as when a short circuit occurs in the coil, the time difference between overcurrent detections by both detection means is shorter than the first reference time. For this reason, in the abnormality determination part, an abnormality signal is output by the first abnormality signal output part. As a result, the protection unit performs a process of turning off the switching element by the output stop operation unit. Thus, adequate protection against rapid overcurrent is activated.

  On the other hand, in the case of a gradual overcurrent, such as when a short circuit occurs in the load, the time difference between the overcurrent detections by both detection means is longer than the second reference time. For this reason, in the abnormality determination part, an abnormal signal is output by the second abnormality signal output part. Thereby, in the protection unit, processing by the duty reduction operation unit or the load separation operation unit is performed. That is, the duty ratio of the pulse signal to the switching element is reduced, or current supply to at least some of the loads is interrupted. Alternatively, both processes are performed. Thus, adequate protection against excessive overcurrent is provided.

  Here, it is preferable that the second reference time is longer than the first reference time. In this case, the abnormality determination unit can include a third abnormality signal output unit that outputs an abnormality signal when the time difference is longer than the first reference time and shorter than the second reference time. Thereby, the time difference of the overcurrent detection by both detection means can be classified into three stages, and processing suitable for each can be performed.

  In the switching power supply of the present invention, it is desirable to have a counter that counts from detection of overcurrent by the first overcurrent detection means to detection of overcurrent by the second overcurrent detection means. By having this counter, the first abnormal signal output unit outputs an abnormal signal when the second overcurrent detection means detects an overcurrent before the count value of the counter reaches a value corresponding to the first reference time. can do. The second abnormality signal output unit can output an abnormality signal when the count value of the counter reaches a value corresponding to the second reference time. The fact that the count value has reached a value corresponding to the second reference time is that the second overcurrent detection means has not yet detected an overcurrent even after the second reference time has elapsed. . Further, the third abnormality signal output unit is configured so that the second overcurrent detection means detects whether the counter value reaches a value corresponding to the second reference time after the count value of the counter reaches a value corresponding to the first reference time. When an overcurrent is detected, an abnormal signal can be output.

  According to the present invention, there is provided a switching power supply apparatus that can take an appropriate measure not to be excessive in accordance with the cause of an overcurrent.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the best mode for embodying the present invention will be described in detail with reference to the accompanying drawings. The switching power supply according to this embodiment is configured as shown in the circuit diagram of FIG. That is, the switching power supply device 100 of the present embodiment has a main power supply 1, an output transistor 2, a coil 3, and a capacitor 4. As a result, the switching power supply of the present embodiment basically switches the current supply from the original power supply 1 by the output transistor 2, smoothes it by the coil 3 and the capacitor 4, and supplies it to the loads 5 and 6. For this reason, the switching power supply of this embodiment further includes the following elements.

  First, a comparator 7 and a level shifter 8 are provided for duty control of the output transistor 2. A triangular wave is input to the negative input terminal of the comparator 7, and an error amplifier output is input to the positive input terminal. The level of the error amplifier output is between the peaks and peaks of the triangular wave in the normal operating state. As a result, a pulse signal having a duty ratio corresponding to the level of the error amplifier output is input to the gate electrode of the output transistor 2. The switching power supply of this embodiment is further provided with a backflow bypass diode 9.

  In addition to these, the switching power supply according to the present embodiment is provided with a configuration for dealing with overcurrent. First, there are a resistor 10 and comparators 11 and 12 for detecting an overcurrent. The resistor 10 is provided between the main power supply 1 and the output transistor 2. The voltage at the node between the resistor 10 and the output transistor 2 depends on the output current of the output transistor 2. Hereinafter, this voltage is referred to as a detection voltage. Each of the comparators 11 and 12 compares the detected voltage with a predetermined reference value. Thereby, when the output current exceeds the current corresponding to each reference value, the outputs of the comparators 11 and 12 are inverted. The second reference value that is the reference value of the comparator 12 is a value that corresponds to a larger current compared to the first reference value that is the reference value of the comparator 11.

  Further, an abnormality determination unit 13 that determines the type of overcurrent according to the outputs of the comparators 11 and 12 is provided. The abnormality determination unit 13 outputs three types of abnormality signals, that is, an operation stop signal 101, a load cutoff signal 102, and a maximum duty reduction signal 103. An operation stop transistor 14 that is turned on by the operation stop signal 101, a load cutoff transistor 15 that is turned off by the load cut signal 102, and a maximum duty reduction operation unit 16 that is operated by the maximum duty reduction signal 103 are provided. The operation stop transistor 14 is provided between the output transistor 2 and the ground. The load breaking transistor 15 is provided between the coil 3 and the load 6. A level shifter 17 is attached to the gate electrode of the load cutoff transistor 15. The maximum duty reduction operation unit 16 is connected to the positive input terminal of the comparator 7. The operation stop transistor 14, the load cutoff transistor 15, and the maximum duty reduction operation unit 16 perform a protective operation in response to an abnormality detected by the abnormality determination unit 13.

  The abnormality determination unit 13 is configured as shown in the circuit diagram of FIG. In the abnormality determination unit 13 that receives the outputs of the comparators 11 and 12, an SR flip-flop 21 is provided. The output signal of the comparator 11 is input to the set terminal, and the output signal of the comparator 12 is input to the reset terminal. The abnormality determination unit 13 is provided with a counter 22. The output signal of the SR flip-flop 21 is input to the enable terminal of the counter 22. An operation clock of the abnormality determination unit 13 is input to the clock terminal of the counter 22. Thus, the counter 22 counts the number of pulses of the operation clock only while the output of the SR flip-flop 21 is high. The counter 22 has a plurality of output terminals Q1, Q2,. The counter value is expressed in binary notation by the output of each output terminal. Note that an inverted output of an AND gate 31, which will be described later, is input to the clear terminal of the counter 22.

  The abnormality determination unit 13 is further provided with an OR gate 23. One of the input terminals is connected to the output terminal Qn of the counter 22. The abnormality determination unit 13 is also provided with a D flip-flop 24. The output signal of the OR gate 23 is input to the D terminal. An operation clock is input to the clock terminal. The output signal of the output terminal Q is input to the other input terminal of the OR gate 23. The abnormality determination unit 13 is provided with an AND gate 25. The output signal of the output terminal Q of the D flip-flop 24 is inverted and input to one of the input terminals. The output signal of the comparator 12 is input to the other input terminal. Further, the abnormality determination unit 13 is provided with an OR gate 26. One of the input terminals is connected to the output terminal of the AND gate 25. The abnormality determination unit 13 is also provided with a D flip-flop 27. The output signal of the OR gate 26 is input to the D terminal. An operation clock is input to the clock terminal. The output signal of the output terminal Q is input to the other input terminal of the OR gate 26 and input to the gate electrode of the operation stop transistor 14 in FIG.

  The abnormality determination unit 13 is provided with an OR gate 28. One of the input terminals is connected to the output terminal Qm (n <m) of the counter 22. The output terminal Qm is not necessarily the final output terminal. The abnormality determination unit 13 is further provided with an AND gate 29. The duty limit self-return signal is input to one of the input terminals. The duty limit self-return signal is a pulse signal having a longer period than the operation clock. The abnormality determination unit 13 is also provided with an AND gate 30. To this, the output of the OR gate 28 and the inverted output of the AND gate 29 are input. The inverted output of the AND gate 29 is also input to the clear terminal of the counter 22 as described above. The abnormality determination unit 13 is provided with a D flip-flop 31. The D terminal is connected to the output terminal of the AND gate 30. An operation clock is input to the clock terminal. The output signal of the output terminal Q is input to the other input terminal of the OR gate 28 and the AND gate 29, and is input to the maximum duty reduction operation unit 16 in FIG.

  Further, the abnormality determination unit 13 is provided with an OR gate 32. One of the input terminals is connected to the output terminal of the D flip-flop 31. The output signal is input as a load cutoff signal 102 to the gate electrode of the load cutoff transistor 15 via the level shifter 17 in FIG. The abnormality determination unit 13 is also provided with a D flip-flop 33. The output signal of the OR gate 32 is input to the D terminal. An operation clock is input to the clock terminal. The output signal of the output terminal Q is input to the other input terminal of the OR gate 32.

  The abnormality determination unit 13 is provided with a multi-input AND gate 34. This includes the output signal of the comparator 12, the output signal of the output terminal Q of the D flip-flop 24, the inverted signal of the output of the output terminal Q of the D flip-flop 31, the inverted signal of the output of the output terminal Q of the D flip-flop 33, These four signals are input. The abnormality determination unit 13 is further provided with an OR gate 35. One input terminal is connected to the output terminal of the multi-input AND gate 34. The abnormality determination unit 13 is also provided with a D flip-flop 36. The D terminal is connected to the output terminal of the OR gate 35. An operation clock is input to the clock terminal. The output signal of the output terminal Q is input to the other input terminal of the OR gate 35 and also serves as an overvoltage detection signal 104.

  FIG. 3 shows a circuit diagram of the maximum duty reduction operation unit 16 in FIG. The maximum duty reduction operation unit 16 is configured around the transistor 41. The emitter of the transistor 41 is connected to the positive input terminal of the comparator 7 in FIG. The base voltage of the transistor 41 is a voltage obtained by dividing the voltage of the sub power supply 42. A transistor 43 for operating the base voltage of the transistor 41 is provided. The base voltage of the transistor 43 is changed by the maximum duty reduction signal 103. The resistance value of each resistor in FIG. 3 is set so that the error amplifier output in FIG. 1 is normally input to the comparator 7 when the maximum duty reduction signal 103 is low.

  Next, the operation of the switching power supply apparatus 100 of this embodiment will be described. The operation of the switching power supply device 100 is to control the current supply from the main power supply 1 to the loads 5 and 6 by switching the output transistor 2. That is, a pulse wave with a duty ratio corresponding to the level of the error amplifier output is output by the action of the comparator 7. The current is duty-controlled by inputting it to the gate electrode of the output transistor 2 via the level shifter 8. The current is smoothed by the coil 3 and the capacitor 4.

  Here, the current flowing through the output transistor 2 is output to the comparators 11 and 12 as a detection voltage by the resistor 10. The comparators 11 and 12 compare this with the first and second reference values. In a normal operation state, the detected voltage does not exceed either the first or second reference value, so that the outputs of the comparators 11 and 12 are both low. For this reason, the abnormality determination part 13 does not operate. That is, the operation stop signal 101, the load cutoff signal 102, and the maximum duty reduction signal 103 all remain low. Since the operation stop signal 101 is low, the operation stop transistor 14 is off. Therefore, the output of the level shifter 8 is input to the gate electrode of the output transistor 2. Since the load shedding signal 102 is low, the load shedding transistor 15 is off. For this reason, current is supplied not only to the load 5 but also to the load 6. Since the maximum duty reduction signal 103 is low, the error amplifier output is normally input to the comparator 7.

  Next, the operation at the time of abnormality will be described. Here, it is assumed that the current flowing through the output transistor 2 becomes excessive as an abnormality. There are two main causes for the current of the output transistor 2 being excessive, that is, an abnormality occurs in the load 5 or 6 in FIG. 1 and a short circuit of the coil 3 in FIG.

  First, consider a case where an abnormality occurs in the load 5 or 6 and an overcurrent occurs (hereinafter referred to as a load abnormality). In this case, the current gradually increases as shown in FIG. This is because the inductance of the coil 3 is effective. Therefore, there is a slight time lag between the time when the current of the output transistor 2 reaches the first reference value (time t1) and the second reference value (time t2). Depending on the degree of overcurrent, the current of the output transistor 2 may not reach the second reference value, but the procedure is the same even in that case. The operation of the switching power supply apparatus 100 of FIG. 1 when a load abnormality occurs will be described with reference to the timing chart of FIG.

  When the current of the output transistor 2 reaches the first reference value (time t1), the output of the comparator 11 goes up. As a result, the output of the SR flip-flop 21 in FIG. Therefore, the counter 22 starts counting up the clock signal. In the case of a load abnormality, the outputs of the output terminals Qn and Qm of the counter 22 rise up before the output of the comparator 12 goes up at time t2. This is because there is a slight time lag between time t1 and time t2 as described above. In other words, the output terminal that rises during the time lag in the case of load abnormality is selected as the output terminal Qm. As an output terminal Qn, an output terminal that goes up higher than the output terminal Qm is naturally selected.

When the count value of the counter 22 exceeds 2 ⁿ⁻¹ , the output of the output terminal Qn increases. As a result, the output of the D flip-flop 24 is kept high thereafter. That is, one input to the AND gate 25 is kept low thereafter. For this reason, even if the output of the comparator 12 goes up at the subsequent time t2, the output of the AND gate 25 does not go up. Therefore, the operation stop signal 101 does not rise up.

When the count value of the counter 22 exceeds 2 ^m−1 , the output of the output terminal Qm increases. As a result, the output of the AND gate 30 increases. This is latched in the D flip-flop 31 at the subsequent clock. Thus, the maximum duty reduction signal 103 is increased. That is, a duty limiting operation for reducing the maximum duty is performed by the maximum duty reduction operation unit 16 in FIG.

  Further, when the output of the D flip-flop 31 is increased, the output of the OR gate 32, that is, the load cutoff signal 102 is also increased. For this reason, the load breaking transistor 15 is turned off. As a result, the load 6 is disconnected from the output transistor 2. Only the load 6 is interrupted, and the load 5 is not interrupted.

  Thereafter, the inverted output of the AND gate 29 is temporarily lowered by the pulse of the duty limit self-return signal. As a result, the count value of the counter 22 is reset and the output of the D flip-flop 31 is lowered.

  In the case of a load abnormality, the output of the D flip-flop 27, that is, the operation stop signal 101 does not rise up. Until the time t2, the output of the comparator 12 is low, while the output of the D flip-flop 24 goes up earlier than the time t2. For this reason, the output of the AND gate 25 does not increase. Further, the output of the D flip-flop 36, that is, the overvoltage detection signal 104 does not rise up. Until the time t2, the output of the comparator 12 is low, while the output of the OR gate 32 goes up earlier than the time t2. For this reason, the output of the multi-input AND gate 34 does not rise up.

  The above is the operation when the load is abnormal. As is clear from this, when a load abnormality occurs, a part of the load is cut off and the maximum duty reduction operation is performed. Of these, the maximum duty reduction operation will be described with reference to FIGS. FIG. 6 is a timing chart showing the relationship between the input / output signal of the comparator 7 and the maximum duty reduction signal 103.

  The left half portion in FIG. 6 shows the situation before the maximum duty reduction operation is performed. The duty ratio is determined according to the error amplifier output level. When the maximum duty reduction signal 103 increases, the base voltage of the transistor 43 in FIG. 3 increases accordingly. As a result, the transistor 43 is turned on, and the base voltage of the transistor 41 is lowered. Then, since the base-emitter voltage of the transistor 41 is constant, the emitter voltage of the transistor 41 also decreases. For this reason, the input voltage to the positive input terminal of the comparator 7 is forcibly lowered, resulting in the situation on the right half in FIG. This is the maximum duty reduction operation. That is, the duty ratio of the output pulse of the comparator 7 is lowered by forcibly lowering the error amplifier output from the normal time. As a result, the current of the output transistor 2 is lowered to prevent the overcurrent state from continuing.

  In the case of a load abnormality, the current does not rise sharply even if an abnormality occurs. For this reason, it is not necessary to stop the operation of the switching power supply device itself. Therefore, in this embodiment, as described above, a part of the load is cut off and the maximum duty reduction operation is stopped. Thereby, the current supply to the load 5 is continued even when the overcurrent abnormality is being dealt with. Therefore, a load for which current supply is not to be stopped as much as possible may be connected directly without going through the load breaking transistor 15. This is the load 5. Conversely, a load that does not need to continue to supply current may be connected via the load breaking transistor 15. This is the load 6. Alternatively, a load that is likely to fail may be the load 6, and a load that is unlikely to fail may be the load 5. In this case, the current supply to the load 5 that is considered not to be in failure is continued while the current supply to the load 6 that is considered to be out of order is stopped.

  Next, let us consider a case where the coil 3 in FIG. In this case, as shown in FIG. 7, the current value rises sharply with the occurrence of an abnormality. This is because the inductance of the coil 3 does not act. For this reason, the time lag from when the current of the output transistor 2 reaches the first reference value until it reaches the second reference value is very short, and it looks almost the same in FIG. The operation of the switching power supply device 100 of FIG. 1 when a coil abnormality occurs will be described with reference to the timing chart of FIG.

  When the current of the output transistor 2 reaches the first reference value (time t1), the output of the comparator 11 goes up. As a result, the output of the SR flip-flop 21 in FIG. Therefore, the counter 22 starts counting up the clock signal. In the case of a coil abnormality, the output of the comparator 12 increases at time t2 before the outputs of the output terminals Qn and Qm of the counter 22 increase. This is because the time lag from time t1 to time t2 is very small as described above. In other words, an output terminal that does not increase during the time lag in the case of a coil abnormality is selected as the output terminal Qn. Of course, the output terminal Qm is selected as an output terminal that goes up after the output terminal Qn.

  Therefore, the counter 22 stops counting up to time t2. For this reason, the output of the output terminal Qn of the counter 22 does not rise up. Therefore, the output of the D flip-flop 24 does not rise up. For this reason, the output of the AND gate 25 is increased at time t2 when the output of the comparator 12 is increased. This is latched in the D flip-flop 27 in the subsequent clock. Thus, the operation stop signal 101 is increased. As a result, the operation stop transistor 14 in FIG. 1 is turned on, and the gate voltage of the output transistor 2 becomes the ground level. For this reason, the output transistor 2 is turned off. That is, the operation of the switching power supply device stops.

  Further, when the coil is abnormal, the output of the output terminal Qm of the counter 22 does not increase. For this reason, the outputs of the OR gate 28 and the AND gate 30 do not increase. Therefore, the output of the D flip-flop 31 does not rise up. That is, the load cutoff signal 102 and the maximum duty reduction signal 103 do not increase up.

  In addition, since the output of the D flip-flop 24 does not increase, the output of the multi-input AND gate 34 does not increase. For this reason, the output of the D flip-flop 36, that is, the overvoltage detection signal 104 does not rise up.

  The above is the operation when the coil is abnormal. As is clear from this, when the coil is abnormal, the operation of the switching power supply itself is stopped. In the case of a coil abnormality, the current value rises steeply as described above, so that protection is insufficient when the maximum duty is reduced or some loads are disconnected.

  Next, the time lag from when the current of the output transistor 2 reaches the first reference value (time t1) to the second reference value (time t2) is an intermediate between the case of load abnormality and the case of coil abnormality. Consider the case of a typical value. In this case, the output of the output terminal Qn of the counter 22 increases at time t2, but the output of the output terminal Qm does not increase. As a cause of such an abnormality, for example, it is conceivable that some abnormality occurs in the main power supply 1 in FIG. 1 and the voltage rises. This is hereinafter referred to as overvoltage abnormality. 1 will be described with reference to the timing chart of FIG. 9 when an overvoltage abnormality occurs.

  When the current of the output transistor 2 reaches the first reference value (time t1), the output of the comparator 11 goes up. As a result, the output of the SR flip-flop 21 in FIG. Therefore, the counter 22 starts counting up the clock signal. In the case of an overvoltage abnormality, the output of the comparator 12 goes up at time t2 after the output of the output terminal Qn of the counter 22 goes up and before the output of the output terminal Qm goes up. Therefore, the counter 22 stops counting up to time t2. For this reason, the output of the output terminal Qm of the counter 22 does not rise up.

When the count value of the counter 22 exceeds 2 ⁿ⁻¹ , the output of the output terminal Qn increases. As a result, the output of the D flip-flop 24 is kept high thereafter. Therefore, at time t2, the output of the comparator 12 is raised, and the output of the multi-input AND gate 34 is raised. This is latched in the D flip-flop 36 at the subsequent clock. Thus, the overvoltage detection signal 104 is increased. Thereby, it is detected that an overvoltage abnormality has occurred.

  In the case of an abnormal overvoltage, the output of the D flip-flop 27, that is, the operation stop signal 101 does not rise up. Until the time t2, the output of the comparator 12 is low, while the output of the D flip-flop 24 goes up earlier than the time t2. For this reason, the output of the AND gate 25 does not increase. Further, since the output of the output terminal Qm of the counter 22 does not increase up, the output of the D flip-flop 31, that is, the maximum duty reduction signal 103 does not increase up. For the same reason, the output of the OR gate 32, that is, the load cutoff signal 102 does not rise up. The above is the operation when an overvoltage abnormality occurs.

  As described above in detail, in the switching power supply according to the present embodiment, the detection voltage due to the output current of the output transistor 2 is compared with a reference value of two levels. The counter 22 counts the clock signal only during the period from when the detected voltage reaches the first reference value until it reaches the second reference value.

If the detected voltage reaches the second reference value before the count value of the counter 22 reaches 2 ⁿ⁻¹ (the output terminal Qn does not rise up), the operation of the switching power supply device is stopped. Like to do. That is, the current supply is forcibly stopped immediately in the case of an abnormality in which the current rises steeply, such as a coil abnormality. Thereby, each part other than the coil 3 is protected.

In addition, when the count value of the counter 22 reaches 2 ^m-1 before the detection voltage reaches the second reference value (the output terminal Qm rises high), the maximum duty reduction operation is partially disconnected from the load. Like to do. That is, when the current rise is not so rapid as in the case of load abnormality, current supply is continued only to a part of the loads (load 5) while suppressing the current.

  As a result, a switching power supply apparatus has been realized that can take an appropriate measure in the event of an overcurrent in accordance with the cause of the overcurrent.

  This embodiment is merely an example and does not limit the present invention. Naturally, the present invention can be variously modified and improved without departing from the spirit of the present invention. For example, in the circuit diagram of FIG. 1 and the like, the specific configuration of the circuit may not be as illustrated. Other configurations having similar functions may be used. Further, when an overvoltage abnormality is detected, some specific measures may be taken (maximum duty reduction or the like).

  Or conversely, overvoltage abnormality may not be detected. In that case, the abnormality determination unit 53 of FIG. 10 may be used instead of the abnormality determination unit 13 shown in FIG. The abnormality determination unit 53 removes the OR gate 23, the D flip-flop 24, the multi-input AND gate 34, the OR gate 35, and the D flip-flop 36 from the abnormality determination unit 13 of FIG. The output signal of the output terminal Q of the group 31 is input. The operation of the switching power supply using the abnormality determination unit 53 of FIG. 10 is the same as that described in this embodiment except for the detection of an overvoltage abnormality.

  It is also possible to change the abnormality determination method. Specifically, when the maximum duty reduction operation is performed due to the abnormality as shown in FIG. In that case, it may be determined that the coil is abnormal and the operation is stopped. When an abnormality as shown in FIG. 7 is detected, the maximum duty reduction operation is first performed, and if the abnormality still does not disappear, it is determined that the coil is abnormal and the operation is stopped.

1 is a circuit diagram of a switching power supply device according to an embodiment. It is a circuit diagram of an abnormality determination part. It is a circuit diagram of a maximum duty reduction operation part. It is a graph of the overcurrent by load abnormality. It is a timing chart explaining operation | movement of the switching power supply device at the time of load abnormality. It is a timing chart which shows the relationship between the input / output signal of a comparator, and a 3rd abnormality signal. It is a graph of the overcurrent by coil abnormality. It is a timing chart explaining operation | movement of the switching power supply device at the time of coil abnormality. It is a timing chart explaining operation | movement of the switching power supply device at the time of overvoltage abnormality. It is a circuit diagram of the abnormality discrimination | determination part which concerns on a modification.

Explanation of symbols

2 Output transistor (switching element)
3 Coil 11 Comparator (first overcurrent detection means)
12 Comparator (second overcurrent detection means)
13 Abnormality determination unit 14 Operation stop transistor (output stop operation unit)
15 Load cutoff transistor (load disconnection operation unit)
16 Maximum duty reduction operation unit 22 Counter 26 OR gate (first abnormal signal output unit)
27 D flip-flop (same as above)
30 AND GATE (second abnormal signal output part)
31 D flip-flop (same as above)
32 or gate (same)
34 Multi-input AND Kate (Third abnormal signal output part)
35 OR Gate (same as above)
36 D flip-flop (same as above)

Claims (6)

In a switching power supply comprising a switching element that switches current supply in response to a pulse signal, and a coil on a current path that is switched by the switching element,
First overcurrent detection means for detecting an overcurrent of the switching element by comparison with a first reference value;
Second overcurrent detection means for detecting an overcurrent of the switching element by comparison with a second reference value corresponding to a current larger than a current corresponding to the first reference value;
An abnormality determination unit that outputs one of two or more types of abnormality signals according to a time difference between overcurrent detections by the first overcurrent detection unit and the second overcurrent detection unit;
A switching power supply device comprising: a protection unit that performs different protection operations according to an abnormality signal of the abnormality determination unit. The switching power supply device according to claim 1,
The abnormality determination unit
A first abnormality signal output unit that outputs an abnormality signal when the time difference is shorter than the first reference time; and a second reference that is not shorter than the first reference time after the overcurrent is detected by the first overcurrent detection means. A second abnormal signal output unit that outputs an abnormal signal when the second overcurrent detection means does not detect an overcurrent even if time has elapsed;
The protective part is
An output stop operation unit for turning off the switching element by an abnormal signal of the first abnormal signal output unit;
A switching power supply device comprising: a duty reduction operation unit that reduces a duty ratio of a pulse signal to the switching element by an abnormal signal of the second abnormal signal output unit. The switching power supply device according to claim 1,
The abnormality determination unit
A first abnormality signal output unit that outputs an abnormality signal when the time difference is shorter than the first reference time; and a second reference that is not shorter than the first reference time after the overcurrent is detected by the first overcurrent detection means. A second abnormal signal output unit that outputs an abnormal signal when the second overcurrent detection means does not detect an overcurrent even if time has elapsed;
The protective part is
An output stop operation unit for turning off the switching element by an abnormal signal of the first abnormal signal output unit;
A switching power supply apparatus comprising: a load separation operation unit that cuts off current supply to at least a part of a load by an abnormality signal of the second abnormality signal output unit. In the switching power supply device according to claim 2 or 3,
The second reference time is longer than the first reference time,
The switching power supply apparatus according to claim 1, wherein the abnormality determination unit includes a third abnormality signal output unit that outputs an abnormality signal when the time difference is longer than the first reference time and shorter than the second reference time. In the switching power supply device according to claim 2 or 3,
A counter that counts from detection of overcurrent by the first overcurrent detection means to detection of overcurrent by the second overcurrent detection means;
The first abnormal signal output unit outputs an abnormal signal when the second overcurrent detection means detects an overcurrent before the count value of the counter reaches a value corresponding to a first reference time.
The switching power supply device, wherein the second abnormality signal output unit outputs an abnormality signal when a count value of the counter reaches a value corresponding to a second reference time. The switching power supply device according to claim 4,
A counter that counts from detection of overcurrent by the first overcurrent detection means to detection of overcurrent by the second overcurrent detection means;
The third abnormal signal output unit includes the second overcurrent detection means between the time when the count value of the counter reaches a value corresponding to a first reference time and a value corresponding to a second reference time. A switching power supply that outputs an abnormal signal when an overcurrent is detected.

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