TW478232B - Power line protection devices and methods capable of preventing false fault reporting - Google Patents

Abstract

The present invention provides an improved power line protection device (50) and method suitable for protecting data bus and power lines such as in the USB (universal serial bus)configurations and other power management circuits. The invention eliminates false fault flag signals generated when large capacitive loads are present. According to the invention, an integrated switch device (60) provided and used in the improved power line protection device. The integrated device is controllable by an external enable signal for switching on and off power supplied on a power line. The switch device comprises a fault detection circuit, a switch (61) and an external flag generation circuit (70). The fault detection circuit detects fault conditions (e.g., an overcurrent condition) and generates an internal flag signal upon detecting a fault, condition. The switch is controllable by the external enable signal and the internal flag signal for switching on and off the power supplied to the power line. The external flag generation circuit is connected to the fault detection circuit to receive the internal flag signal. If the internal flag signal lasts longer than a predetermined duration, the external flag generation circuit generates an external flag signal after the predetermined duration has elapsed since receiving the internal flag. In this way, false fault reporting is effectively prevented.

Description

Printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs 478232 A7 _B7_ V. Description of the invention (1) Cross-reference to related patents Power Line Protection Devices and Methods for Providing Overload Protection to Multiple Outputs " and `` Integrated Switch Device with Enhanced Functionalities ... '', the agent numbers are MP 1687-US1 and MP 1689-US1, respectively. The disclosures of these two applications are listed here for reference only. BACKGROUND OF THE INVENTION The present invention generally relates to protection devices, and more specifically to protection devices used in computer bus lines, which can supply power to downstream electronic components and power to management circuits. Now connected technology has allowed more computers to interconnect with each other via the network. Each computer has many peripherals connected to it. Peripheral devices include not only conventional devices such as a keyboard or a mouse, but also new applications such as digital cameras. In a typical network system, a concentrator is connected to many nodes, and each of these nodes is connected to many subnodes. Each node or child node can be a computer or a peripheral device. Each child node can be connected to additional secondary child nodes, etc. In this network system, power is typically distributed to various nodes and child nodes. This network environment example is related to the recent universal serial bus (USB) standard, such as the USB-IF and USB specifications revised in 1998 for 1.1. In this network system, each network node is continuously supervised. Normal operation and missing conditions (such as overcurrent, overtemperature, undervoltage, etc.) are continuously reported to a control circuit. When a missing condition such as an overcurrent condition occurs -4- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----------- install ------ --Order --------- (Please read the notes on the back before filling this page) 478232

V. Description of the invention (2) The clothing printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs When born at -nodes or subnodes, the most important thing is that any missing points cannot affect the operation of the rest of the network system. In other words, the lack must be controlled and isolated in order to achieve the high efficiency of the network system. Various non- @ power bus line protection devices have been proposed. Item 1 describes the use of-a typical power management and protection device in a personal computer. In FIG. I, the king machine 10 communicates with a peripheral device via the USB port 12. The peripheral device u communicates with another peripheral device (not shown in the figure) via another USB connection 珲 32. The USB port 12 includes a power line 3, two data lines j 4 15 η and a return line 16. Similarly, the USB port 32 includes a power line 33, two data lines 34, 35, and a loopback line%. The peripheral device η includes a power management and protection device 20, which includes a USB controller 22, a power integrated circuit (pic) switch 30, and external pull-up resistors R2 and R2. The controller 22 may be a TUSB 2040 or TUSB 2070 device, which is a commercial part available from Texas Instruments, Dallas, Texas, USA. An example of a power integration circuit switch 30 is a commercial iMIC 2526 power switch available from Inc. of San Jose, California. Power integrated circuits Switches usually include self-protection mechanisms and are typically used for power management in computer hardware environments, such as USB applications. The host 10 can periodically check the peripheral device n and other connected peripheral devices (not shown in the figure) to determine their status, such as whether there is a data request, a missing condition report, and the like. Under normal circumstances, the controller 22 can activate the switch 3 by transmitting an active vEN signal (low or high) through the power control (PC) node, and the power is provided to the power line 33 via the port 32 Other peripherals. When an over-current situation occurs, the controller 2 2 can be installed via oc (the paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)) ------- (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478232 A7 --_ B7 V. Description of the invention (3) Electric current) The printed points are received from the power supply One of the integrated circuits p, c, and switch 3 is missing the flag signal ^ VFG, and notifies the host of the lack of 10. The host 10 then transmits a complementary active Ven signal to the switch through the PC to make the controller 22 turn off the power integration circuit PIC switch 30 to turn off the power on the power line 33. In some cases, it can also cause the controller 22 to turn off the power on the power line 33 without being affected by any command from the host 10, and at the same time report the lack to the host 10. By turning off the power, the absence is isolated and the switch is protected. The circuit of Fig. 1 suffers from serious disadvantages when it has a large internal capacitance, such as a scanner or digital camera I, a peripheral device or a load, and is connected to the port 32 as in many practical applications. This disadvantage is described in Figures 2 and 26. Fig. 2A illustrates the circuit operation of Fig. I, in which the host 10 can instruct the processor 22 to turn off the power on the power line when a missing condition occurs. During the time between 0 and t1, the power integration circuit PIC switch 30 is operated under normal conditions and VEN is active (assuming an active VEN is at a high level). When the power source is used in this load, and the internal capacitance of the load is charged, and the load current IVL increases, the load current 1 may exceed the current limit of the power integrated circuit PIC switch 30. When the current limit is reached at time η, the power integration circuit switch 30 sets a missing flag signal Vfg and transmits it to the controller 22 from the OC node to indicate an over-current condition. This overcurrent condition is to communicate with the host 10, and then cause the controller 22 to turn off the power integration circuit PIC switch 30 by transmitting a non-active vEN signal (assuming an inactive Ven is at a low level) to the switch. On the power line The power on 33 can be turned off to protect the switch. As long as the internal capacitance of the load is within the time ^ ^ strong clothes -------- order --------- (Please read the precautions on the back before (Fill in this page)

A7

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

2. Where the king is not%, the load current 1 l will be reduced to a lower rated value. After the operation of 12 is reduced to be lower than the current limit of the power integration circuit pic switch 3 (), the switch resets the missing flag to the signal I, thus notifies the controller η, and then communicates with the machine 10 ′. The host 10 then causes the controller 22 to transmit an active ven: number to the power integration circuit pic switch 30 at t2 to start the power. Both] The large internal capacitance in the load or peripheral devices only lasts for a short time, such as 2 to 10 亳 seconds, so the process of setting and resetting the missing flag signal separately to indicate whether or not a missing condition occurs is very undesirable. need. No need: The power supplied to the peripheral device via the USB port, as a result, the peripheral device cannot reach the normal operating state. 2: The operation of the circuit of Fig.1, when a missing condition occurs, ΐΙΓ is controlled on the power line by the host 1G without any instructions. During the time between 0 and ", the power supply integrated circuit PIC; often operates, and VEN is active (assuming-active #w # 斤 在 呵呵 准 准). When the power is used in the vicinity of the-internal capacitor The load's internal capacitor is charging and the load voltage is increased. The limit current IlT can exceed the current of the power integration circuit pic switch 30: two! Two: the current limit arrival time. When the power integration circuit switch 30 is over The flag signal V is missing and the controller 22, Ye Yi Er = D is transmitted to 乂 “-over-current condition via 0C Lang point. After a delay time of td, the power integration circuit can be transmitted to the switch by transmitting the “non-active ~ signal (assume re = gate == low level) to the switch at the same time and report the missing condition to the host 10 .If the power on the source line 3 3 will be turned off to protect the switch. At the time M -------- Order ------ (Please read the precautions on the back before filling this page)

HII nn · This paper size is in accordance with China National Standard (CNS) A4 specification (210: 297 mm) 478232 A7 B7 Integrated switch settings are available, V. Description of the invention (5) tb 'Load voltage VL will decrease, load The current IL is reduced to zero and the missing flag signal VFG is reset. Since overcurrent conditions last only for a very short time, such as one hundred microseconds, due to the large internal capacitance of the load or peripheral devices, the same disadvantages reappear. The result is that the peripheral devices do not reach normal operating conditions. A solution has been proposed to address the above disadvantages, and is described in FIG. In FIG. 3, a missing flag delay circuit 3 is connected between the USB controller 22 and the% source integration circuit PI switch 30. The circuit 31 can provide a delay missing flag signal VFG to the USB controller η, in order to reduce the false missing report. However, adding this external delay circuit to the circuit of FIG. 1 is very expensive and causes a complicated circuit structure. In addition, the use of external pull-up resistors will further complicate the circuit structure. Therefore, when a peripheral device with a large internal capacitance is connected to the _peripheral connection ，, it is necessary to provide a simple, faithful and low-cost solution to avoid this false report. f Λ Summary of the invention The present invention can provide an integrated switching device with a problem described above, and only if the missing condition lasts longer than the -pre-waiting device can a missing condition (eg, ": hold-time, child control element. Book The time gate & over% condition) is reported to a typical range of waiting time and time. In this way, the AND-traditional power line reporting problem of 110 milliseconds can be effectively removed. According to a specific embodiment of the present invention, the use of side devices is according to a specific embodiment of the invention, • 8 (Please read the precautions on the back before filling out this page) | Install -------- Order ------ -n 1 n

V. Description of the invention (6 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs can be controlled by an external enable signal to turn on and off the power supply on the power line. The control device includes a missing detection circuit. Used to detect missing conditions (for example, an overcurrent condition) and generate an internal Shao flag signal when the two conditions are reached; a switch, which can be external. This L4 internal flag signal is used to start and close Supply to the private source line (power supply; 1_external flag generation circuit, which is coupled to the missing detection circuit to receive the internal flag signal, and if the internal Shao flag signal lasts longer than a predetermined duration, it is used to generate According to an aspect of the integrated switching device of the present invention, since the internal flag signal is received, if the internal flag signal is longer than-a predetermined duration, the external flag generating circuit can be used after the predetermined duration elapses. Generates a flag signal from outside Shao. In addition, if the internal flag signal lasts longer than the pre-footing duration and should be missing If the signal is lost, the external flag generating circuit resets the external flag signal. According to another aspect of the integrated switch device of the present invention, the external flag generating circuit includes a logic delay circuit, each of which can be used when receiving the signal of # ㈣ Generate a pulse with a pre-foot duration; a logic AND gate to generate a control bluff, the AND gate has an input coupled to receive an internal flag signal and a reverse input coupled to receive a pulse from a logic delay circuit With a power switch, which can be controlled by a control signal from the AND gate to generate the external flag signal. Still according to another aspect of the integrated switching device, the switching device further includes a first input terminal for receiving power at the power source. Power supply online; first install -------- order --------- (Please read the precautions on the back before filling this page)

478232

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (7) Two input terminals for receiving the external enable signal;-Output terminal for outputting the external flag signal; a first pull-up resistor, which Connected between the first and second input terminals t; and a second pull-up resistor connected between the first input terminal and the output terminal. The switching device also includes a voltage limiter connected between the output terminal and a ground level. According to another embodiment of the present invention, a protection device may be provided and controlled by a host to protect a power line. The protection device includes a switching circuit and a controller. The switch-off circuit can be controlled by an external enable signal: used to turn on and off the power supply on the power line. The switch circuit includes a missing detection circuit for detecting a missing condition (for example, a power-over condition) and for detecting the missing condition-an internal flag signal two switches, which can be enabled by the external The signal is controlled by the internal flag signal. Used to start and shut off the power supply on the power line; and an external flag generating circuit 'which is connected to the missing detection circuit to receive the internal flag k, and if the internal flag signal is longer than a predetermined The sequence time 7 'is used to generate: external flag signal. The controller is coupled to the switch circuit 22: = Shao flag signal, which is used to switch the external enable signal on and off. As long as the external flag signal is detected and detected, the controller :: reports the absence to the host ’causing the switch circuit to turn off the power. : According to the viewpoint of the protection of the present invention, the internal flag has a predetermined duration. Since the internal flag signal is received, so! After the time has elapsed, the external flag generation circuit will generate two: signal. In addition, if the internal flag signal is persistent Hold for a long time,... Η and if the missing condition disappears, the external flag • ^ installed -------- order --------- (Please read the precautions on the back before filling this page)

t (CNS) A4 (210 297 mm) V. Description of the invention (8 flag: Tiger signal 'to cause the controller to disappear the missing condition ㈣ cause the controller to allow the circuit to power on. According to another specific of the present invention An embodiment is provided to protect the method. The method includes the steps of detecting a missing situation (for example, late = situation); whenever the missing situation is detected, a Deng banner signal is generated; if the The internal flag signal lasts for a long time: when the disease persists :: the external flag signal; and as long as the external signal is detected; the signal will cause the power on the power line to be turned off. This method also includes only ^ detecting the external Shao flag signal and reporting the Missing case-step. "According to an aspect of the present invention, since the internal flag signal is generated: after the predetermined duration of the child disappears, the step of generating an external flag signal generates an external flag signal. According to another aspect of the method of the present invention, if the flag signal is long lasting, the predetermined duration and the missing condition disappear, the method further includes the following ten thousand; these steps, reset External flag signals, reports of the missing situation, and start of the power supply on the power line. / For other purposes and to achieve a complete understanding of the present invention will become more apparent through the patent application below and with the accompanying drawings The same reference numerals in the figure indicate the same parts: Figure 1 shows a traditional power management and protection device used by π in a personal computer; Figures 2A and 2B describe the operation of the device in different environments; Figure; 3 Shows a traditional solution to the shortcomings of the device of Figure 1; 11 ^ Zhang scales are applicable to Chinese national standards (CNSM4 specifications, 297 issued

1 -------- Order --------- (Please read the notes on the back before filling out this page) Slave: Printed by the Consumer Consumption Cooperative of the Ministry of Economic Affairs and Intellectual Property of the Ministry of Justice 478232 V. Invention Explanation (9) FIG. 4 is a functional block diagram applied according to a specific embodiment of the present invention; FIG. 5 is a diagram illustrating a switch according to the present invention, and a switch; A power integration circuit PI == the specific embodiment of the present invention is shown-the PIC switch operation of the power integration circuit <logic table; and the diagram is a timing diagram of a specific implementation of the circuit switching operation according to the present invention. Explain that Figure 4 is a _function &quot; of 50 applications according to the present invention: ^ Mutation and display of the original protection device k character element :: For simplicity, the same description as in Figure 1 with reference to 22 also. Name slightly The power protection device 50 includes a USB control port A and a source integrated circuit (PIC) switch 60. The original switch 61, the gate control circuit 62 / tun 5 64, and an external flag generation circuit 70 .Voltage limit = :: for example, a 3.5V Zener diode, and it is used for two 'and ... ίinput 0 °. Current limit Circuit 64 is a traditional circuit that controls the current supplied to the load. If an overcurrent occurs, the current is limited: 4 will send a control signal to the control circuit μ. It can be understood that the power integration circuit pic switch 6. Also = Circuit = circuit (not shown in the figure), can provide basic &quot;% such as voltage reference, etc. In addition, in another embodiment, the power integration circuit is turned on.

This paper scale shed + (CNS) A4 (210 X 297) 478232 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 V. Description of the invention (10) The key also includes traditional circuits used to detect over-temperature and excessive voltage, And the plastic should wait for any of the cases and turn off the power supply to the load. In a normal situation, νΕΝ * —active (assuming an active Ven is at logic 1), and the power switch 61 is turned on. Therefore, as described in FIG. 4, power can be supplied from + Vbus to another peripheral device via the power integration circuit PIC switch 60 (not shown in the figure). In the case of an overcurrent, the current limiting circuit may transmit a control signal to the gate control circuit 62, which then closes the switch 61. The current limiting circuit 64 also generates an internal flag signal Vif to indicate an over-current condition. However, the internal flag signal Vif is not directly transmitted to the usb controller 22 (in FIG. 4), but instead is transmitted to the external flag generation circuit 70. The external flag generation circuit 70 includes a logic delay circuit 72, an and gate 74, and its reverse input end is connected to the output vd of the logic delay circuit 72, and an output transistor 76 connected to the output VA of the AND gate 74. . As long as a VIF signal is received, the logic delay circuit 72 generates a pulse%, and a predetermined duration may be, for example, 2 to 1 () milliseconds. v_Vd is ^^ AND gate 74, which can control the redundant output of the output transistor. In this specific embodiment, the logic delay circuit 72 may be, for example, a single-shot circuit, a monostable circuit, as long as it is activated, This circuit can generate a pulse signal with a run time of ⑴ ^ s. In FIG. 5, any one of the pull-up resistor_RF and the voltage limiter 58 is selected by the customer through a cover method at the time of manufacture to fit a circuit substrate in which external pull-up resistors and / or voltage limiters are installed in advance. One can be cut off. Figure ": Shows the timing diagram of the operation of the external flag generation circuit 70 when an overcurrent occurs briefly. As shown in Figure 6A 'is in time. Between τι is normal operation X 297 Public love 7 ------- -^ --------- (Please read the notes on the back before filling out this page) -13 478232 Printed clothing A7 B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of invention (11) Working conditions' Among them, no overcurrent will occur, and a VIF is inactive (assuming an inactive VIF signal is at logic 0). Since there is no overcurrent, the logic delay circuit 72 will not output any pulse and its output vd at logic 0. Therefore, AND The output VA of the gate 74 is also in logic 0. Therefore, the output transistor 76 is in the off state and no external flag is generated, so Vef remains at logic 1 (assuming an active external Shao flag is at logic 0, that is, VEF = logic 0). As described in FIG. 6A, the overcurrent occurs at 71 and lasts for a short time (T2-T1). The internal overcurrent flag Vif is set by the current limit circuit 64 at a corresponding time (T2-TI) Become active (assuming an active Vif is in logic 丨). Just connect Upon receiving an active VIF, the logic delay circuit 72 generates a pulse Vd of a predetermined duration (T3-T1). Therefore, the output of the AND logic gate 74 is at logic 0 for the predetermined duration (T3-T1). As a result, At time (T3_τι / 'the output transistor 76 remains in the off state, and Vef is at logic 1 during this time. Since the overcurrent will not exceed the predetermined time (τ 3 τ! Λ, u J 1 i), so No external overcurrent signal is generated, and false reports can be prevented. Figure 6B shows that when an overcurrent continues when the load is connected to a power-supply integrated circuit switch 60, for example, the external flag generation circuit 7 The timing diagram of the operation is shown in Figure 6. As shown in Figure 6B, between 0 and τ1, 、, 丄, as shown in Figure 6A, there is normal operation. Overcurrent occurs at T1, and what to do Until T 4. Therefore, the VIF is set to active at time (T 4-Τ 1), with a time greater than the predetermined duration (T 3-T 1), where the pulse v D is active. Over-current condition. Indicated in Figure 6B, when scheduled (T3_T1) As shown in period 6A, the output V a of AND gate 7 4 is at logic 0. At T 3, the pulse v_D will be reset. 14- This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) ----------- Installation -------- Order --------- (Please read the precautions on the back before filling this page) 478232 A7 B7 12 V. Description of the invention (. Between T3 and T4 &lt; &apos; since it is still at logic 1, but ν〇 is reset to logic 0 &apos; and the output of the AND gate 74 becomes a logic 1, so that the output transistor 76 is turned on, and the external flag signal vef is set Become active, that is, logic 0. The over-current condition notified through Wangdong VEF will of course communicate with USB controller 22. As can be seen from the above, the external flag generation circuit 70 essentially cuts off the predetermined initial portion of the internal flag signal VIF and outputs an external flag signal ~ to the controller 22, which means any other portion of the internal flag signal &amp;. Therefore, both; ,, and: generate an internal impulse flag signal, so the controller 2 will not be able to connect to j phase until a pre-footing duration has elapsed. Figures 7A and 7B show timing diagrams for overcurrent conditions and power switch integrated circuit pic operation. Figure 7A illustrates how the power integration circuit pic switch operates when a large capacitive load is present. Prior to detecting the overcurrent, the controller 22 allows the power integration circuit pic to switch 60—active v⑽ (assuming an active VEN is at a high level). When a large capacitive load is connected to the power integration circuit switch, the load voltage VL increases, and the load will experience—a large initial load electric sensation, and this current will quickly reach the current limit of the power integration circuit switch ⑼. When 1L is reached and the current limit is exceeded, the internal flag vIF will be generated and set by the current limit circuit 64 to be active. At this time, as long as the receive-active V1F, the logic delay circuit generates a pulse Vd, such as a predetermined hold time (TC-Ta). As long as the load current ^ is in the OR circuit switch 6. Current limit of the internal flag signal να This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm-15 &lt; 478232 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ) At time Tb, the capacitive load is fully charged, and the load current IL will decrease 丨 Rentai ”% L will become solid t ^ ^ ^ 0 ^ ^ ^ ^: I5! P &quot; M 60, resulting in a current limiting circuit 64 The internal flag will disappear from the quasi-VIF. F is reset to F—the low-order is at time Te, and the external flag generation circuit 70 will remove any other part of the predetermined duration of Vd; this = in pulse The duration of the internal flag signal V is less than the duration of the pulse: 2 ::: ^: Power generation: 7. The output of the external flag signal v '= anything not-I. The circuit 70 can effectively remove Γ and missing reports In addition, the USB controller 22 is active for any duration of less than 卞 month = any pre-sufficient internal overcurrent flag ^: Therefore: ^ stay set. According to the present invention, the 持续 range of the predetermined duration is 疋 2 to 10 耄 seconds to ensure normal operation. ', FIG. 7B describes how the power integration circuit pic switch works before a resistor is negative. Before detecting and detecting an overcurrent, the USB controller 22 starts two: The power integration circuit switch 6 of vEN is activated. When the load voltage Vl increases At this time, the standby load current lL increases considerably. At this time, P a, II reaches the current limit of the power integration circuit switch 60. At this time, the internal flag signal vif is set to be active by the current limit circuit 64. An active Vif causes logic The delay circuit η generates a pulse with a predetermined duration (Tc_Ta) at Ta. At time Tc, the pulse Vd is reset. Since the continuous overcurrent condition, that is, vIF is still at a high level, the external flag signal Vef is at logic 0. The external flag generation circuit 70 is set to active. The active Vef is connected to the USB controller 22 -------- order --------- (Please read the precautions on the back before filling this page ) 16 478232 Patent Application No. 89105127 Revised Chinese Manual (December 90) V. Description of Invention (14)

Communicate 'and then communicate with the host 10. The host 1G resets the VEN to the inactive level (logic υ) at Te to delete the controller 22 to turn off the power supplied on the power line ㈣ and protects the power integration circuit switch 60. The controller 22 The resettable Ve can be reset without any instructions from the host. "In Fig. 7B, as shown in Fig. 7A, since the pulse ^ is generated, the Xibu Department flag generation circuit 70 allows the USB controller 22 to only hold the time and continue (Tc_Ta) Any other part of the internal flag signal V1F is then received. Therefore, the entire operating efficiency can be achieved by using the present invention, and all circuit elements are maintained ^ their normal operating range. _ Although the present invention has been implemented with several special implementations Examples, but those skilled in the art will know that many further choices, modifications, and changes will be apparent from the previously described point of view. Therefore, the invention described herein is intended to cover all such choices, modifications, and changes without prejudice. The spirit and scope of Yu Dabei's patent application scope. Symbol description of main components of the drawing 10 Host 11 Peripheral device 12 USB port 13 Power line 14 Data line 15 16 feed line 20 return line protection device 22 USB Controller • 17-

478232 Patent Application No. 89105127 Revised Chinese Manual (December 1990) 5

Description of the invention (14a) 30 Power integrated circuit (PIC) switch 3 1 Circuit 32 USB port 3 3 Power line 34 Data line 3 5 Data line 36 Loopback line 50 Power protection device 5 8 Voltage limiter 60 Power integrated circuit (PIC ) Switch 6 1 Switch 62 Gate control circuit 64 Current limit circuit 70 External flag generation circuit 72 Logic delay circuit 74 AND gate 76 Output transistor -17a- This paper size applies to China National Standard (CNS) A4 specification (210 x 297 mm )

Claims (1)

478232 Patent Application No. 89105127 Chinese Patent Application Amendment (December 90) Patent Application Amendment 2. 3. Amend an integrated switch device that can be controlled by an external enable signal to enable and disable the supply on a power line The power supply of the device includes a missing detection circuit. As long as the missing condition is detected, it is used to detect a missing condition and to generate an internal flag signal. A switch can be enabled by the external The signal and the internal flag signal are used to enable and disable the power supplied on a power line; and an external flag generating circuit is coupled to the missing detection circuit to receive the internal flag signal, and if the internal flag signal is The flag signal lasts longer than a predetermined duration, and an external flag signal is generated by the public. For example, if the device of claim 1 is applied, the external flag generation circuit resets the external flag signal if the internal flag signal persists longer than the predetermined duration. For example, the device of the scope of patent application, wherein the external flag generation circuit includes: a logic delay circuit, as long as it receives the internal flag signal, used to generate a pulse that violates the pre-satisfaction performance time, a logic AND gate, and To generate a control signal, the AND gate has an input adapted to receive the internal flag signal, and a reverse input coupled to receive a pulse from the logic delay circuit, and a power switch which can be received from the AND gate Controlled by the control signal is used to generate the external flag signal. For example, the device under the scope of patent application of claim 1 further includes: a first input terminal for receiving the power supply on the power line. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Love) Tune eight; ^ m VA receives the external enable signal; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The terminal is used to output the external chess number signal:: Pull-up resistor 'It is connected between the first and second input terminals, and Two-one pull-up resistor' It is connected to the first inputs Between the terminal and the output terminal t. For example, the patent application item No. 4 _Coinfoot device further includes a voltage limiter between the output terminal and a ground potential. An integrated switching device that can be activated by an external enable signal to turn on and off the power supplied on the power line. The device includes a missing detection private circuit, which detects a missing as long as the missing condition is detected. Condition and used to generate an internal flag signal; a switch that can be controlled by the external enable signal and the internal flag signal to turn on and off the power supplied on a power line; and an external flag generation circuit that is coupled to The missing detection circuit is used to receive the internal flag signal, and if the internal flag signal is longer than a predetermined duration, it is used to generate an external flag signal. The external flag generation circuit includes a logic delay circuit, which As long as the internal flag signal is received to generate a pulse of the predetermined duration, a logical AND gate is used to generate a control signal, the and gate has an input coupled to receive one of the internal flag signals, and a coupled to receive from One of the pulses of the logic delay circuit is a reverse input, and a power switch is provided by the Controlled by the control signal --------- 丨 丨 丨 丨 € (Please read the precautions on the back before filling this page) Enter -Φ · -Line n 1 n 2- This paper size applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 478232 '1 &gt; ". 丄: Supplement i 6. Patent application scope system to generate the external flag signal. 8. == The device of the range 6 item, wherein the missing condition includes a machine control to protect the protective circuit of the power supply line and a switching circuit, which can be controlled by an external enable signal to enable and disable the power supply line. Power supply, the switch circuit package. A missing detection circuit, as long as the missing condition is detected / used to # detect a missing condition and used to generate a flag signal in the Ministry; The enable signal and the internal flag signal control are used to turn on and off the power supplied on a power line. The P flag generation circuit is coupled to the missing detection circuit to receive the internal flag signal, and if the internal flag signal lasts longer than a predetermined duration, it is used to generate an external signal; and. -The controller 'its Hanhe to the switch circuit and responds to the external flag signal' is used to enable the external signal to control the switch circuit, and the second is to detect the external flag signal to detect the absence Reported to the host, causing the switch circuit to turn off the power. 9. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed a device such as the scope of patent application No. 8, wherein if the internal flag signal lasts longer than the predetermined duration and the missing condition disappears, the external flag generates a private road and resets the exterior. # 号 信 ㉟, to cause the controller to report the disappearance of the missing Sui / Brother to the host, and allow the switch circuit to turn on the power. 10. If the integrated switchgear of item i of the scope of patent application, where the predetermined holding size 3- this paper size applies to the Chinese national standard ^ ks) A4 specification (210 x 297 mm A8 08, 々, patent application scope -4- ^ — ~ The duration is 2 to 10 milliseconds. 1 1. 12. 13. 14 · 15 · 16. 17. 18. If the device of the scope of patent application item 7 is applied, the predetermined duration B to 10 milliseconds. The protection device in the scope of patent application No. 8 in which the predetermined interval is 2 to 10 leap seconds. 1 f If the integrated switch device in scope of patent application No. 1 in which the missing condition includes an overcurrent situation. The protection device of scope item 8, wherein the missing condition includes an overcurrent condition. A method for protecting the edge_power line, the method includes the following steps; detecting a missing condition;-... as long as the missing condition is detected An internal flag signal is generated; if the internal flag signal lasts longer than a predetermined duration, an external flag signal is generated, and its ideal range is about 2 to 10 milliseconds; and as long as the external flag signal is detected, Cheng will turn off the power supply on the power line. For example, the method in the scope of patent application No. 15 further includes a step of reporting the missing condition as long as an external flag signal is detected.丨 The method of 5 items, wherein the missing condition includes an over-current condition. For example, the method of claim 15 of the scope of patent application, further includes if the flag signal lasts longer than the predetermined duration, and the missing condition disappears, etc. Steps: Reset the external flag signal; -4-This paper size applies to China National Standard (CNS) A4 (210X297 mm) 478232 8 8 8 8 AB c D 6. Scope of patent application Reporting the disappearance of the missing condition; and • Turn off the power supply on the power line. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)