WO2000057559A1 - Procede et unite processeur pour representer des informations presentant une serie de valeurs variables sur des mots de code - Google Patents

Procede et unite processeur pour representer des informations presentant une serie de valeurs variables sur des mots de code Download PDF

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Publication number
WO2000057559A1
WO2000057559A1 PCT/DE2000/000605 DE0000605W WO0057559A1 WO 2000057559 A1 WO2000057559 A1 WO 2000057559A1 DE 0000605 W DE0000605 W DE 0000605W WO 0057559 A1 WO0057559 A1 WO 0057559A1
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WO
WIPO (PCT)
Prior art keywords
information
tfci
word
mapped
code words
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Application number
PCT/DE2000/000605
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German (de)
English (en)
Inventor
Bernhard Raaf
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2000057559A1 publication Critical patent/WO2000057559A1/fr

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W99/00Subject matter not provided for in other groups of this subclass

Definitions

  • the invention relates to a method and a processor unit for mapping information with a variable value range onto code words, in particular onto code words with a variable value range.
  • the range of values of at least one code word is reduced, the range of values of the code words differing as little as possible.
  • the invention is therefore based on the idea of using a priori information about a restricted value range of the information to be mapped onto the code words when decoding the code words, so that only a reduced value range of the code words is used during the decoding.
  • a further development of the invention provides for the number of relevant bit positions of at least one binary code word to be reduced in the case of a restricted value range of the information to be mapped, the number of relevant bit positions of the code words differing by a maximum of 1.
  • the number is to use information as efficiently as possible the bit positions relevant for coding and decoding are the same for all code words or differ by 1.
  • a further development of the invention provides for the information to be mapped onto code words in such a way that the number of relevant bit positions of a code word is constant over a large interval of the value range of the information to be mapped when the value range of the information to be mapped changes, and the number of relevant bit positions of a code word if the value range of the information to be mapped is changed in steps of at most 1.
  • FIG. 1 block diagram of a mobile radio system
  • FIG. 2 block diagram of a processor unit
  • FIG. 3 shows schematic representations of the mapping of information onto binary code words
  • Figure 4 Representation of an optimized scheme for mapping information to code words.
  • FIG. 1 shows a cellular mobile radio network, such as the GSM (Global System for Mobile Communication) system, which consists of a large number of mobile switching centers MSC which are networked with one another or which provide access to a fixed network PSTN / ISDN . Furthermore, these mobile switching centers are each at least MSC connected to a base station controller BSC, which can also be formed by a data processing system.
  • GSM Global System for Mobile Communication
  • BSC base station controller
  • a similar architecture can also be found in a UMTS (Universal Mobile Telecommunication System).
  • UMTS Universal Mobile Telecommunication System
  • Each base station controller BSC is in turn connected to at least one base station BS.
  • a base station BS is a radio station which can establish a radio connection to other radio stations, so-called mobile stations MS, via a radio interface.
  • Information can be transmitted between the mobile stations MS and the base station BS assigned to these mobile stations MS by means of radio signals.
  • the range of the radio signals of a base station essentially define a radio cell FZ.
  • Base stations BS and a base station controller BSC can be combined to form a base station system BSS.
  • the base station system BSS is also responsible for radio channel management and allocation, data rate adaptation, monitoring of the radio transmission link, hand-over procedures and, in the case of a CDMA system, for the allocation of the spreading code sets to be used, and transmits them necessary signaling information to the mobile stations MS.
  • data can be accessed via a
  • Radio interface can be efficiently transmitted, separated and assigned to one or more specific connections or the corresponding subscriber.
  • a time multiple access TDMA, a frequency multiple access FDMA, a code multiple access CDMA or a combination of several of these multiple access methods can be used for this purpose.
  • the resulting physical channels are assigned to logical channels according to a defined scheme.
  • logical channels There are two basic types of logical channels:
  • Signaling channels for the transmission of signaling information (or control information) and Traffic channels (TCH) for the transmission of user data.
  • the signaling channels are further divided into:
  • the group of broadcast channels includes the broadcast control channel BCCH, through which the MS receives radio information from the base station system BSS.
  • the Random Access Channel R ⁇ CH is one of the common control channels.
  • information about the data rate of data transmitted in a radio frame will be transmitted via a DPCCH (Dedicated Physical Control Channel) using a so-called Transport Format Combination Indicator (TFCI).
  • DPCCH Dedicated Physical Control Channel
  • TFCI Transport Format Combination Indicator
  • FIG. 2 shows a processor unit PE, which can be contained in particular in a functional unit, such as a communication device, a base station BS or a mobile station MS. It contains a control device STE, which essentially consists of a program-controlled microcontroller, and a processing device VE, which consists of a processor, in particular a digital signal processor, both of which have write and read access to memory modules SPE.
  • a control device STE which essentially consists of a program-controlled microcontroller
  • VE which consists of a processor, in particular a digital signal processor, both of which have write and read access to memory modules SPE.
  • the microcontroller controls and monitors all essential elements and functions of the functional unit that contains the processor unit PE.
  • the microcontroller, the digital signal processor, part of the digital signal processor or a special processor is responsible for carrying out the mapping of information onto code words.
  • An input / output interface I / O is used for the input / output of user or control data, for example to an MMI control unit, which contain a keyboard and / or a display can.
  • the elements of the processor unit PE can be connected to one another by means of a digital bus system BUS.
  • processor unit PE Using such a processor unit PE, information can be mapped to code words using one of the methods described below.
  • FIG. 3 a known scheme for mapping information with a variable value range onto two code words, each with five bit positions, is shown on the left-hand side.
  • the following is an example of the illustration of information that comprises at least 65 values. Information that contains less than 65 values can be encoded accordingly.
  • the value range of the information to be mapped comprises a maximum of 128 values
  • these 128 values are mapped to 7 bit positions, 5 bit positions of the first code word Word1 and 2 bit positions of the second code word Word2 being occupied.
  • the value range of the information to be mapped comprises a maximum of 256 values
  • 8 bit positions are occupied, again 5 bit positions of the first code word Word1 and 3 bit positions of the second code word Word2 being occupied.
  • this illustration on the left in FIG. 3 this illustration is also continued accordingly for a range of values which comprises a maximum of 512 values and a range of values which comprises a maximum of 1024 values. Obviously, such a distribution of information over two code words is unbalanced, which leads to an inefficient use of the a priori information when decoding such coded information.
  • information to be mapped includes a range of values that comprises a maximum of 128 values 7 bit positions are occupied, 4 bit positions of the first code word Word1 are occupied and 3 bit positions of the second code word Word2 are occupied.
  • 8 occupied bit positions 4 bit positions of the first code word Word1 and 4 bit positions of the second code word Word2 are occupied.
  • 9 occupied bit positions 5 bit positions of the first code word Word1 and 4 bit positions of the second code word Word2 are occupied. If the range of values of the information to be mapped comprises more than 512 values, then all bit positions of both code words are occupied.
  • One embodiment variant provides that the information is first mapped to an intermediate code word, the bit positions of this intermediate code word being numbered starting from zero, the least important bit position (LSB) being assigned to the number zero.
  • the bit positions of the intermediate code word are then mapped to the two code words in accordance with the diagram on the right in FIG. 3, the zero bit position of the intermediate code word being mapped to the zero position of the first code word Word1, the first
  • Bit position of the intermediate code word is mapped to the zeroth bit position of the second code word Word2, the second bit position of the intermediate code word is mapped to the first bit position of the first code word Word1, the third bit position of the intermediate code word is mapped to the first bit position of the second code word Word2, the fourth bit position of the Intermediate code word is mapped to the second bit position of the first code word Word1, the fifth bit position of the intermediate code word is mapped to the second bit position of the second code word Word2 etc., that is to say the bit positions of the two
  • Code words are alternately occupied with the bit positions of the intermediate code word.
  • mapping scheme shown on the right in FIG. 3 only provides for the case of the same number of occupied
  • Bit positions in both code words a balanced distribution of the information.
  • the information is subsequently distributed with a finer granularity than corresponds to a single information bit. This is possible because a biorthogonal decoder can not only use a priori information about the number of bit positions to be decoded, but also use information about the number of code words used, that is to say in principle possible to be decoded. This property is explained in more detail using the following example:
  • the information to be mapped contains 81 different values, nine different code words are assigned to the first code word and nine different code words are also assigned to the second code word.
  • the information to be mapped is mapped to the two code words as follows: The value of the information to be mapped is divided by the smallest integer that is greater than or equal to the square root of the number of possible values of the information to be mapped. The first code word Word1 is then equal to the integer division result and the second code word Word2 is equal to the remainder of the division.
  • an optimized coding scheme is presented below, which distributes the information TFCI to the code words as evenly as possible and also a change in the mapping rule from information to be mapped TFCI to code words is not necessary even in the event of a change in the range of values of the information to be mapped TFCI.
  • This mapping of TFCI values to binary code words takes place according to the following rules: if TFCI ⁇ n ⁇ 2 + n, a first code word (Wordl) has the value n and a second code word (Word2) has the value TFCI - n ⁇ 2, otherwise a second code word (Word2) has the value n and a first code word (Wordl) the value n ⁇ 2 + 2 * n - TFCI, where
  • TFCI is the value of the information to be mapped (TFCI), and n is the largest integer that is less than or equal to the square root of TFCI.
  • the coding scheme generated by these rules is shown in FIG. 4, the values of the information to be displayed being shown in decimal form (numbers 0 to 1023) in a Word1 / Word2 diagram. The values of the five-digit code words are described in decimal form (0 to 31).
  • a corresponding decoding can be implemented as follows:
  • n: maxQVor dl, Word!)
  • TFCI n 2 + n + Word2 - Wordl
  • Another embodiment variant of the invention provides a coding rule which generates the following trip ice: TFCI; Codewortl (Wordl) in decimal representation, Codewort2 (Word2) in decimal representation 0; 0, 0 (1; 1.0 2; 0.1 3; 1.1) (4; 2.0 5; 2.1 6; 0.2 7; 1.2
  • TFCI transport format combination indicator
  • DPCCH dedicated physical control channel

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

Selon l'invention, des informations présentant une série de valeurs variables sont représentées sur deux mots de code de la façon suivante, la valeur a priori de la fonction à représenter étant connue : la valeur de la fonction à représenter est divisée par le plus petit nombre entier qui est supérieur ou égal à la racine carrée du nombre de valeurs possibles de la fonction à représenter. Le premier mot de code (mot1) autorise des valeurs comprises entre 0 et le résultat entier de la division, et le deuxième mot (mot2) autorise des valeurs comprises entre 0 et le reste de la division. Ceci permet d'obtenir une répartition équilibrée des mots de code et de réduire la propagation d'erreurs.
PCT/DE2000/000605 1999-03-18 2000-03-01 Procede et unite processeur pour representer des informations presentant une serie de valeurs variables sur des mots de code WO2000057559A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19912241 1999-03-18
DE19912241.5 1999-03-18

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WO2000057559A1 true WO2000057559A1 (fr) 2000-09-28

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2620736A1 (de) * 1975-05-12 1976-11-25 Gen Instrument Corp Einrichtung zur bildung eines eins-aus-zehn-codes zur speicheradressierung
US5455823A (en) * 1990-11-06 1995-10-03 Radio Satellite Corporation Integrated communications terminal
US5801649A (en) * 1995-08-03 1998-09-01 Seagate Technology, Inc. Matched spectral null encoder/decoder

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2620736A1 (de) * 1975-05-12 1976-11-25 Gen Instrument Corp Einrichtung zur bildung eines eins-aus-zehn-codes zur speicheradressierung
US5455823A (en) * 1990-11-06 1995-10-03 Radio Satellite Corporation Integrated communications terminal
US5801649A (en) * 1995-08-03 1998-09-01 Seagate Technology, Inc. Matched spectral null encoder/decoder

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